0b9ffe87a6bd34ee571161cb7b374e9b0b9240ff
[mesa.git] / src / mesa / drivers / dri / intel / intel_regions.c
1 /**************************************************************************
2 *
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /* Provide additional functionality on top of bufmgr buffers:
29 * - 2d semantics and blit operations
30 * - refcounting of buffers for multiple images in a buffer.
31 * - refcounting of buffer mappings.
32 * - some logic for moving the buffers to the best memory pools for
33 * given operations.
34 *
35 * Most of this is to make it easier to implement the fixed-layout
36 * mipmap tree required by intel hardware in the face of GL's
37 * programming interface where each image can be specifed in random
38 * order and it isn't clear what layout the tree should have until the
39 * last moment.
40 */
41
42 #include <sys/ioctl.h>
43 #include <errno.h>
44
45 #include "main/hash.h"
46 #include "intel_context.h"
47 #include "intel_regions.h"
48 #include "intel_blit.h"
49 #include "intel_buffer_objects.h"
50 #include "intel_bufmgr.h"
51 #include "intel_batchbuffer.h"
52
53 #define FILE_DEBUG_FLAG DEBUG_REGION
54
55 /* This should be set to the maximum backtrace size desired.
56 * Set it to 0 to disable backtrace debugging.
57 */
58 #define DEBUG_BACKTRACE_SIZE 0
59
60 #if DEBUG_BACKTRACE_SIZE == 0
61 /* Use the standard debug output */
62 #define _DBG(...) DBG(__VA_ARGS__)
63 #else
64 /* Use backtracing debug output */
65 #define _DBG(...) {debug_backtrace(); DBG(__VA_ARGS__);}
66
67 /* Backtracing debug support */
68 #include <execinfo.h>
69
70 static void
71 debug_backtrace(void)
72 {
73 void *trace[DEBUG_BACKTRACE_SIZE];
74 char **strings = NULL;
75 int traceSize;
76 register int i;
77
78 traceSize = backtrace(trace, DEBUG_BACKTRACE_SIZE);
79 strings = backtrace_symbols(trace, traceSize);
80 if (strings == NULL) {
81 DBG("no backtrace:");
82 return;
83 }
84
85 /* Spit out all the strings with a colon separator. Ignore
86 * the first, since we don't really care about the call
87 * to debug_backtrace() itself. Skip until the final "/" in
88 * the trace to avoid really long lines.
89 */
90 for (i = 1; i < traceSize; i++) {
91 char *p = strings[i], *slash = strings[i];
92 while (*p) {
93 if (*p++ == '/') {
94 slash = p;
95 }
96 }
97
98 DBG("%s:", slash);
99 }
100
101 /* Free up the memory, and we're done */
102 free(strings);
103 }
104
105 #endif
106
107
108
109 /* XXX: Thread safety?
110 */
111 GLubyte *
112 intel_region_map(struct intel_context *intel, struct intel_region *region,
113 GLbitfield mode)
114 {
115 /* We have the region->map_refcount controlling mapping of the BO because
116 * in software fallbacks we may end up mapping the same buffer multiple
117 * times on Mesa's behalf, so we refcount our mappings to make sure that
118 * the pointer stays valid until the end of the unmap chain. However, we
119 * must not emit any batchbuffers between the start of mapping and the end
120 * of unmapping, or further use of the map will be incoherent with the GPU
121 * rendering done by that batchbuffer. Hence we assert in
122 * intel_batchbuffer_flush() that that doesn't happen, which means that the
123 * flush is only needed on first map of the buffer.
124 */
125
126 _DBG("%s %p\n", __FUNCTION__, region);
127 if (!region->map_refcount++) {
128 intel_flush(&intel->ctx);
129
130 if (region->tiling != I915_TILING_NONE)
131 drm_intel_gem_bo_map_gtt(region->bo);
132 else
133 drm_intel_bo_map(region->bo, true);
134
135 region->map = region->bo->virtual;
136 ++intel->num_mapped_regions;
137 }
138
139 return region->map;
140 }
141
142 void
143 intel_region_unmap(struct intel_context *intel, struct intel_region *region)
144 {
145 _DBG("%s %p\n", __FUNCTION__, region);
146 if (!--region->map_refcount) {
147 if (region->tiling != I915_TILING_NONE)
148 drm_intel_gem_bo_unmap_gtt(region->bo);
149 else
150 drm_intel_bo_unmap(region->bo);
151
152 region->map = NULL;
153 --intel->num_mapped_regions;
154 assert(intel->num_mapped_regions >= 0);
155 }
156 }
157
158 static struct intel_region *
159 intel_region_alloc_internal(struct intel_screen *screen,
160 GLuint cpp,
161 GLuint width, GLuint height, GLuint pitch,
162 uint32_t tiling, drm_intel_bo *buffer)
163 {
164 struct intel_region *region;
165
166 region = calloc(sizeof(*region), 1);
167 if (region == NULL)
168 return region;
169
170 region->cpp = cpp;
171 region->width = width;
172 region->height = height;
173 region->pitch = pitch;
174 region->refcount = 1;
175 region->bo = buffer;
176 region->tiling = tiling;
177 region->screen = screen;
178
179 _DBG("%s <-- %p\n", __FUNCTION__, region);
180 return region;
181 }
182
183 struct intel_region *
184 intel_region_alloc(struct intel_screen *screen,
185 uint32_t tiling,
186 GLuint cpp, GLuint width, GLuint height,
187 bool expect_accelerated_upload)
188 {
189 drm_intel_bo *buffer;
190 unsigned long flags = 0;
191 unsigned long aligned_pitch;
192 struct intel_region *region;
193
194 if (expect_accelerated_upload)
195 flags |= BO_ALLOC_FOR_RENDER;
196
197 buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "region",
198 width, height, cpp,
199 &tiling, &aligned_pitch, flags);
200 if (buffer == NULL)
201 return NULL;
202
203 region = intel_region_alloc_internal(screen, cpp, width, height,
204 aligned_pitch / cpp, tiling, buffer);
205 if (region == NULL) {
206 drm_intel_bo_unreference(buffer);
207 return NULL;
208 }
209
210 return region;
211 }
212
213 bool
214 intel_region_flink(struct intel_region *region, uint32_t *name)
215 {
216 if (region->name == 0) {
217 if (drm_intel_bo_flink(region->bo, &region->name))
218 return false;
219
220 _mesa_HashInsert(region->screen->named_regions,
221 region->name, region);
222 }
223
224 *name = region->name;
225
226 return true;
227 }
228
229 struct intel_region *
230 intel_region_alloc_for_handle(struct intel_screen *screen,
231 GLuint cpp,
232 GLuint width, GLuint height, GLuint pitch,
233 GLuint handle, const char *name)
234 {
235 struct intel_region *region, *dummy;
236 drm_intel_bo *buffer;
237 int ret;
238 uint32_t bit_6_swizzle, tiling;
239
240 region = _mesa_HashLookup(screen->named_regions, handle);
241 if (region != NULL) {
242 dummy = NULL;
243 if (region->width != width || region->height != height ||
244 region->cpp != cpp || region->pitch != pitch) {
245 fprintf(stderr,
246 "Region for name %d already exists but is not compatible\n",
247 handle);
248 return NULL;
249 }
250 intel_region_reference(&dummy, region);
251 return dummy;
252 }
253
254 buffer = intel_bo_gem_create_from_name(screen->bufmgr, name, handle);
255 if (buffer == NULL)
256 return NULL;
257 ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle);
258 if (ret != 0) {
259 fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",
260 handle, name, strerror(-ret));
261 drm_intel_bo_unreference(buffer);
262 return NULL;
263 }
264
265 region = intel_region_alloc_internal(screen, cpp,
266 width, height, pitch, tiling, buffer);
267 if (region == NULL) {
268 drm_intel_bo_unreference(buffer);
269 return NULL;
270 }
271
272 region->name = handle;
273 _mesa_HashInsert(screen->named_regions, handle, region);
274
275 return region;
276 }
277
278 void
279 intel_region_reference(struct intel_region **dst, struct intel_region *src)
280 {
281 _DBG("%s: %p(%d) -> %p(%d)\n", __FUNCTION__,
282 *dst, *dst ? (*dst)->refcount : 0, src, src ? src->refcount : 0);
283
284 if (src != *dst) {
285 if (*dst)
286 intel_region_release(dst);
287
288 if (src)
289 src->refcount++;
290 *dst = src;
291 }
292 }
293
294 void
295 intel_region_release(struct intel_region **region_handle)
296 {
297 struct intel_region *region = *region_handle;
298
299 if (region == NULL) {
300 _DBG("%s NULL\n", __FUNCTION__);
301 return;
302 }
303
304 _DBG("%s %p %d\n", __FUNCTION__, region, region->refcount - 1);
305
306 ASSERT(region->refcount > 0);
307 region->refcount--;
308
309 if (region->refcount == 0) {
310 assert(region->map_refcount == 0);
311
312 drm_intel_bo_unreference(region->bo);
313
314 if (region->name > 0)
315 _mesa_HashRemove(region->screen->named_regions, region->name);
316
317 free(region);
318 }
319 *region_handle = NULL;
320 }
321
322 /*
323 * XXX Move this into core Mesa?
324 */
325 void
326 _mesa_copy_rect(GLubyte * dst,
327 GLuint cpp,
328 GLuint dst_pitch,
329 GLuint dst_x,
330 GLuint dst_y,
331 GLuint width,
332 GLuint height,
333 const GLubyte * src,
334 GLuint src_pitch, GLuint src_x, GLuint src_y)
335 {
336 GLuint i;
337
338 dst_pitch *= cpp;
339 src_pitch *= cpp;
340 dst += dst_x * cpp;
341 src += src_x * cpp;
342 dst += dst_y * dst_pitch;
343 src += src_y * src_pitch;
344 width *= cpp;
345
346 if (width == dst_pitch && width == src_pitch)
347 memcpy(dst, src, height * width);
348 else {
349 for (i = 0; i < height; i++) {
350 memcpy(dst, src, width);
351 dst += dst_pitch;
352 src += src_pitch;
353 }
354 }
355 }
356
357 /* Copy rectangular sub-regions. Need better logic about when to
358 * push buffers into AGP - will currently do so whenever possible.
359 */
360 bool
361 intel_region_copy(struct intel_context *intel,
362 struct intel_region *dst,
363 GLuint dst_offset,
364 GLuint dstx, GLuint dsty,
365 struct intel_region *src,
366 GLuint src_offset,
367 GLuint srcx, GLuint srcy, GLuint width, GLuint height,
368 bool flip,
369 GLenum logicop)
370 {
371 uint32_t src_pitch = src->pitch;
372
373 _DBG("%s\n", __FUNCTION__);
374
375 if (intel == NULL)
376 return false;
377
378 assert(src->cpp == dst->cpp);
379
380 if (flip)
381 src_pitch = -src_pitch;
382
383 return intelEmitCopyBlit(intel,
384 dst->cpp,
385 src_pitch, src->bo, src_offset, src->tiling,
386 dst->pitch, dst->bo, dst_offset, dst->tiling,
387 srcx, srcy, dstx, dsty, width, height,
388 logicop);
389 }