1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 /* Provide additional functionality on top of bufmgr buffers:
29 * - 2d semantics and blit operations
30 * - refcounting of buffers for multiple images in a buffer.
31 * - refcounting of buffer mappings.
32 * - some logic for moving the buffers to the best memory pools for
35 * Most of this is to make it easier to implement the fixed-layout
36 * mipmap tree required by intel hardware in the face of GL's
37 * programming interface where each image can be specifed in random
38 * order and it isn't clear what layout the tree should have until the
42 #include <sys/ioctl.h>
45 #include "intel_context.h"
46 #include "intel_regions.h"
47 #include "intel_blit.h"
48 #include "intel_buffer_objects.h"
49 #include "intel_bufmgr.h"
50 #include "intel_batchbuffer.h"
51 #include "intel_chipset.h"
53 #define FILE_DEBUG_FLAG DEBUG_REGION
55 /* This should be set to the maximum backtrace size desired.
56 * Set it to 0 to disable backtrace debugging.
58 #define DEBUG_BACKTRACE_SIZE 0
60 #if DEBUG_BACKTRACE_SIZE == 0
61 /* Use the standard debug output */
62 #define _DBG(...) DBG(__VA_ARGS__)
64 /* Use backtracing debug output */
65 #define _DBG(...) {debug_backtrace(); DBG(__VA_ARGS__);}
67 /* Backtracing debug support */
73 void *trace
[DEBUG_BACKTRACE_SIZE
];
74 char **strings
= NULL
;
78 traceSize
= backtrace(trace
, DEBUG_BACKTRACE_SIZE
);
79 strings
= backtrace_symbols(trace
, traceSize
);
80 if (strings
== NULL
) {
85 /* Spit out all the strings with a colon separator. Ignore
86 * the first, since we don't really care about the call
87 * to debug_backtrace() itself. Skip until the final "/" in
88 * the trace to avoid really long lines.
90 for (i
= 1; i
< traceSize
; i
++) {
91 char *p
= strings
[i
], *slash
= strings
[i
];
101 /* Free up the memory, and we're done */
109 /* XXX: Thread safety?
112 intel_region_map(struct intel_context
*intel
, struct intel_region
*region
)
114 intelFlush(&intel
->ctx
);
116 _DBG("%s %p\n", __FUNCTION__
, region
);
117 if (!region
->map_refcount
++) {
119 intel_region_cow(intel
, region
);
121 if (region
->tiling
!= I915_TILING_NONE
&&
122 intel
->intelScreen
->kernel_exec_fencing
)
123 drm_intel_gem_bo_map_gtt(region
->buffer
);
125 dri_bo_map(region
->buffer
, GL_TRUE
);
126 region
->map
= region
->buffer
->virtual;
133 intel_region_unmap(struct intel_context
*intel
, struct intel_region
*region
)
135 _DBG("%s %p\n", __FUNCTION__
, region
);
136 if (!--region
->map_refcount
) {
137 if (region
->tiling
!= I915_TILING_NONE
&&
138 intel
->intelScreen
->kernel_exec_fencing
)
139 drm_intel_gem_bo_unmap_gtt(region
->buffer
);
141 dri_bo_unmap(region
->buffer
);
146 static struct intel_region
*
147 intel_region_alloc_internal(struct intel_context
*intel
,
149 GLuint width
, GLuint height
, GLuint pitch
,
152 struct intel_region
*region
;
154 if (buffer
== NULL
) {
155 _DBG("%s <-- NULL\n", __FUNCTION__
);
159 region
= calloc(sizeof(*region
), 1);
161 region
->width
= width
;
162 region
->height
= height
;
163 region
->pitch
= pitch
;
164 region
->refcount
= 1;
165 region
->buffer
= buffer
;
167 /* Default to no tiling */
168 region
->tiling
= I915_TILING_NONE
;
169 region
->bit_6_swizzle
= I915_BIT_6_SWIZZLE_NONE
;
171 _DBG("%s <-- %p\n", __FUNCTION__
, region
);
175 struct intel_region
*
176 intel_region_alloc(struct intel_context
*intel
,
178 GLuint cpp
, GLuint width
, GLuint height
, GLuint pitch
,
179 GLboolean expect_accelerated_upload
)
182 struct intel_region
*region
;
184 /* If we're tiled, our allocations are in 8 or 32-row blocks, so
185 * failure to align our height means that we won't allocate enough pages.
187 * If we're untiled, we still have to align to 2 rows high because the
188 * data port accesses 2x2 blocks even if the bottom row isn't to be
189 * rendered, so failure to align means we could walk off the end of the
192 if (tiling
== I915_TILING_X
)
193 height
= ALIGN(height
, 8);
194 else if (tiling
== I915_TILING_Y
)
195 height
= ALIGN(height
, 32);
197 height
= ALIGN(height
, 2);
199 /* If we're untiled, we have to align to 2 rows high because the
200 * data port accesses 2x2 blocks even if the bottom row isn't to be
201 * rendered, so failure to align means we could walk off the end of the
204 height
= ALIGN(height
, 2);
206 if (expect_accelerated_upload
) {
207 buffer
= drm_intel_bo_alloc_for_render(intel
->bufmgr
, "region",
208 pitch
* cpp
* height
, 64);
210 buffer
= drm_intel_bo_alloc(intel
->bufmgr
, "region",
211 pitch
* cpp
* height
, 64);
214 region
= intel_region_alloc_internal(intel
, cpp
, width
, height
,
217 if (tiling
!= I915_TILING_NONE
) {
218 assert(((pitch
* cpp
) & 127) == 0);
219 drm_intel_bo_set_tiling(buffer
, &tiling
, pitch
* cpp
);
220 drm_intel_bo_get_tiling(buffer
, ®ion
->tiling
, ®ion
->bit_6_swizzle
);
226 struct intel_region
*
227 intel_region_alloc_for_handle(struct intel_context
*intel
,
229 GLuint width
, GLuint height
, GLuint pitch
,
230 GLuint handle
, const char *name
)
232 struct intel_region
*region
;
236 buffer
= intel_bo_gem_create_from_name(intel
->bufmgr
, name
, handle
);
238 region
= intel_region_alloc_internal(intel
, cpp
,
239 width
, height
, pitch
, buffer
);
243 ret
= dri_bo_get_tiling(region
->buffer
, ®ion
->tiling
,
244 ®ion
->bit_6_swizzle
);
246 fprintf(stderr
, "Couldn't get tiling of buffer %d (%s): %s\n",
247 handle
, name
, strerror(-ret
));
248 intel_region_release(®ion
);
256 intel_region_reference(struct intel_region
**dst
, struct intel_region
*src
)
259 _DBG("%s %p %d\n", __FUNCTION__
, src
, src
->refcount
);
261 assert(*dst
== NULL
);
269 intel_region_release(struct intel_region
**region_handle
)
271 struct intel_region
*region
= *region_handle
;
273 if (region
== NULL
) {
274 _DBG("%s NULL\n", __FUNCTION__
);
278 _DBG("%s %p %d\n", __FUNCTION__
, region
, region
->refcount
- 1);
280 ASSERT(region
->refcount
> 0);
283 if (region
->refcount
== 0) {
284 assert(region
->map_refcount
== 0);
287 region
->pbo
->region
= NULL
;
289 dri_bo_unreference(region
->buffer
);
291 if (region
->classic_map
!= NULL
) {
292 drmUnmap(region
->classic_map
,
293 region
->pitch
* region
->cpp
* region
->height
);
298 *region_handle
= NULL
;
302 * XXX Move this into core Mesa?
305 _mesa_copy_rect(GLubyte
* dst
,
313 GLuint src_pitch
, GLuint src_x
, GLuint src_y
)
321 dst
+= dst_y
* dst_pitch
;
322 src
+= src_y
* dst_pitch
;
325 if (width
== dst_pitch
&& width
== src_pitch
)
326 memcpy(dst
, src
, height
* width
);
328 for (i
= 0; i
< height
; i
++) {
329 memcpy(dst
, src
, width
);
337 /* Upload data to a rectangular sub-region. Lots of choices how to do this:
339 * - memcpy by span to current destination
340 * - upload data as new buffer and blit
342 * Currently always memcpy.
345 intel_region_data(struct intel_context
*intel
,
346 struct intel_region
*dst
,
348 GLuint dstx
, GLuint dsty
,
349 const void *src
, GLuint src_pitch
,
350 GLuint srcx
, GLuint srcy
, GLuint width
, GLuint height
)
352 _DBG("%s\n", __FUNCTION__
);
359 dsty
== 0 && width
== dst
->pitch
&& height
== dst
->height
)
360 intel_region_release_pbo(intel
, dst
);
362 intel_region_cow(intel
, dst
);
365 LOCK_HARDWARE(intel
);
366 _mesa_copy_rect(intel_region_map(intel
, dst
) + dst_offset
,
369 dstx
, dsty
, width
, height
, src
, src_pitch
, srcx
, srcy
);
371 intel_region_unmap(intel
, dst
);
372 UNLOCK_HARDWARE(intel
);
375 /* Copy rectangular sub-regions. Need better logic about when to
376 * push buffers into AGP - will currently do so whenever possible.
379 intel_region_copy(struct intel_context
*intel
,
380 struct intel_region
*dst
,
382 GLuint dstx
, GLuint dsty
,
383 struct intel_region
*src
,
385 GLuint srcx
, GLuint srcy
, GLuint width
, GLuint height
,
388 _DBG("%s\n", __FUNCTION__
);
395 dsty
== 0 && width
== dst
->pitch
&& height
== dst
->height
)
396 intel_region_release_pbo(intel
, dst
);
398 intel_region_cow(intel
, dst
);
401 assert(src
->cpp
== dst
->cpp
);
403 return intelEmitCopyBlit(intel
,
405 src
->pitch
, src
->buffer
, src_offset
, src
->tiling
,
406 dst
->pitch
, dst
->buffer
, dst_offset
, dst
->tiling
,
407 srcx
, srcy
, dstx
, dsty
, width
, height
,
411 /* Attach to a pbo, discarding our data. Effectively zero-copy upload
415 intel_region_attach_pbo(struct intel_context
*intel
,
416 struct intel_region
*region
,
417 struct intel_buffer_object
*pbo
)
421 if (region
->pbo
== pbo
)
424 _DBG("%s %p %p\n", __FUNCTION__
, region
, pbo
);
426 /* If there is already a pbo attached, break the cow tie now.
427 * Don't call intel_region_release_pbo() as that would
428 * unnecessarily allocate a new buffer we would have to immediately
432 region
->pbo
->region
= NULL
;
436 if (region
->buffer
) {
437 dri_bo_unreference(region
->buffer
);
438 region
->buffer
= NULL
;
441 /* make sure pbo has a buffer of its own */
442 buffer
= intel_bufferobj_buffer(intel
, pbo
, INTEL_WRITE_FULL
);
445 region
->pbo
->region
= region
;
446 dri_bo_reference(buffer
);
447 region
->buffer
= buffer
;
451 /* Break the COW tie to the pbo and allocate a new buffer.
452 * The pbo gets to keep the data.
455 intel_region_release_pbo(struct intel_context
*intel
,
456 struct intel_region
*region
)
458 _DBG("%s %p\n", __FUNCTION__
, region
);
459 assert(region
->buffer
== region
->pbo
->buffer
);
460 region
->pbo
->region
= NULL
;
462 dri_bo_unreference(region
->buffer
);
463 region
->buffer
= NULL
;
465 region
->buffer
= dri_bo_alloc(intel
->bufmgr
, "region",
466 region
->pitch
* region
->cpp
* region
->height
,
470 /* Break the COW tie to the pbo. Both the pbo and the region end up
471 * with a copy of the data.
474 intel_region_cow(struct intel_context
*intel
, struct intel_region
*region
)
476 struct intel_buffer_object
*pbo
= region
->pbo
;
479 intel_region_release_pbo(intel
, region
);
481 assert(region
->cpp
* region
->pitch
* region
->height
== pbo
->Base
.Size
);
483 _DBG("%s %p (%d bytes)\n", __FUNCTION__
, region
, pbo
->Base
.Size
);
485 /* Now blit from the texture buffer to the new buffer:
488 LOCK_HARDWARE(intel
);
489 ok
= intelEmitCopyBlit(intel
,
491 region
->pitch
, pbo
->buffer
, 0, region
->tiling
,
492 region
->pitch
, region
->buffer
, 0, region
->tiling
,
494 region
->pitch
, region
->height
,
497 UNLOCK_HARDWARE(intel
);
501 intel_region_buffer(struct intel_context
*intel
,
502 struct intel_region
*region
, GLuint flag
)
505 if (flag
== INTEL_WRITE_PART
)
506 intel_region_cow(intel
, region
);
507 else if (flag
== INTEL_WRITE_FULL
)
508 intel_region_release_pbo(intel
, region
);
511 return region
->buffer
;
514 static struct intel_region
*
515 intel_recreate_static(struct intel_context
*intel
,
517 struct intel_region
*region
,
518 intelRegion
*region_desc
)
520 intelScreenPrivate
*intelScreen
= intel
->intelScreen
;
523 if (region
== NULL
) {
524 region
= calloc(sizeof(*region
), 1);
525 region
->refcount
= 1;
526 _DBG("%s creating new region %p\n", __FUNCTION__
, region
);
529 _DBG("%s %p\n", __FUNCTION__
, region
);
532 if (intel
->ctx
.Visual
.rgbBits
== 24)
535 region
->cpp
= intel
->ctx
.Visual
.rgbBits
/ 8;
536 region
->pitch
= intelScreen
->pitch
;
537 region
->width
= intelScreen
->width
;
538 region
->height
= intelScreen
->height
;
540 if (region
->buffer
!= NULL
) {
541 dri_bo_unreference(region
->buffer
);
542 region
->buffer
= NULL
;
546 assert(region_desc
->bo_handle
!= -1);
547 region
->buffer
= intel_bo_gem_create_from_name(intel
->bufmgr
,
549 region_desc
->bo_handle
);
551 ret
= dri_bo_get_tiling(region
->buffer
, ®ion
->tiling
,
552 ®ion
->bit_6_swizzle
);
554 fprintf(stderr
, "Couldn't get tiling of buffer %d (%s): %s\n",
555 region_desc
->bo_handle
, name
, strerror(-ret
));
556 intel_region_release(®ion
);
560 if (region
->classic_map
!= NULL
) {
561 drmUnmap(region
->classic_map
,
562 region
->pitch
* region
->cpp
* region
->height
);
563 region
->classic_map
= NULL
;
565 ret
= drmMap(intel
->driFd
, region_desc
->handle
,
566 region
->pitch
* region
->cpp
* region
->height
,
567 ®ion
->classic_map
);
569 fprintf(stderr
, "Failed to drmMap %s buffer\n", name
);
574 region
->buffer
= intel_bo_fake_alloc_static(intel
->bufmgr
,
577 region
->pitch
* region
->cpp
*
579 region
->classic_map
);
581 /* The sarea just gives us a boolean for whether it's tiled or not,
582 * instead of which tiling mode it is. Guess.
584 if (region_desc
->tiled
) {
585 if (IS_965(intel
->intelScreen
->deviceID
) &&
586 region_desc
== &intelScreen
->depth
)
587 region
->tiling
= I915_TILING_Y
;
589 region
->tiling
= I915_TILING_X
;
591 region
->tiling
= I915_TILING_NONE
;
594 region
->bit_6_swizzle
= I915_BIT_6_SWIZZLE_NONE
;
597 assert(region
->buffer
!= NULL
);
603 * Create intel_region structs to describe the static front, back, and depth
604 * buffers created by the xserver.
606 * Although FBO's mean we now no longer use these as render targets in
607 * all circumstances, they won't go away until the back and depth
608 * buffers become private, and the front buffer will remain even then.
610 * Note that these don't allocate video memory, just describe
611 * allocations alread made by the X server.
614 intel_recreate_static_regions(struct intel_context
*intel
)
616 intelScreenPrivate
*intelScreen
= intel
->intelScreen
;
618 intel
->front_region
=
619 intel_recreate_static(intel
, "front",
621 &intelScreen
->front
);
624 intel_recreate_static(intel
, "back",
628 /* Still assumes front.cpp == depth.cpp. We can kill this when we move to
631 intel
->depth_region
=
632 intel_recreate_static(intel
, "depth",
634 &intelScreen
->depth
);