src/mesa/drivers/dri/intel/intel_regions.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /* Provide additional functionality on top of bufmgr buffers:
  29  *   - 2d semantics and blit operations
  30  *   - refcounting of buffers for multiple images in a buffer.
  31  *   - refcounting of buffer mappings.
  32  *   - some logic for moving the buffers to the best memory pools for
  33  *     given operations.
  34  *
  35  * Most of this is to make it easier to implement the fixed-layout
  36  * mipmap tree required by intel hardware in the face of GL's
  37  * programming interface where each image can be specifed in random
  38  * order and it isn't clear what layout the tree should have until the
  39  * last moment.
  40  */
  41
  42 #include <sys/ioctl.h>
  43 #include <errno.h>
  44
  45 #include "intel_context.h"
  46 #include "intel_regions.h"
  47 #include "intel_blit.h"
  48 #include "intel_buffer_objects.h"
  49 #include "dri_bufmgr.h"
  50 #include "intel_bufmgr.h"
  51 #include "intel_batchbuffer.h"
  52 #include "intel_chipset.h"
  53
  54 #define FILE_DEBUG_FLAG DEBUG_REGION
  55
  56 /* XXX: Thread safety?
  57  */
  58 GLubyte *
  59 intel_region_map(struct intel_context *intel, struct intel_region *region)
  60 {
  61    DBG("%s\n", __FUNCTION__);
  62    if (!region->map_refcount++) {
  63       if (region->pbo)
  64          intel_region_cow(intel, region);
  65
  66       dri_bo_map(region->buffer, GL_TRUE);
  67       region->map = region->buffer->virtual;
  68    }
  69
  70    return region->map;
  71 }
  72
  73 void
  74 intel_region_unmap(struct intel_context *intel, struct intel_region *region)
  75 {
  76    DBG("%s\n", __FUNCTION__);
  77    if (!--region->map_refcount) {
  78       dri_bo_unmap(region->buffer);
  79       region->map = NULL;
  80    }
  81 }
  82
  83 static int
  84 intel_set_region_tiling_gem(struct intel_context *intel,
  85                             struct intel_region *region,
  86                             uint32_t bo_handle)
  87 {
  88    struct drm_i915_gem_get_tiling get_tiling;
  89    int ret;
  90
  91    memset(&get_tiling, 0, sizeof(get_tiling));
  92
  93    get_tiling.handle = bo_handle;
  94    ret = ioctl(intel->driFd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
  95    if (ret != 0) {
  96       fprintf(stderr, "Failed to get tiling state for region: %s\n",
  97               strerror(errno));
  98       return ret;
  99    }
 100
 101    region->tiling = get_tiling.tiling_mode;
 102    region->bit_6_swizzle = get_tiling.swizzle_mode;
 103
 104    return 0;
 105 }
 106
 107 static struct intel_region *
 108 intel_region_alloc_internal(struct intel_context *intel,
 109                             GLuint cpp, GLuint pitch, GLuint height,
 110                             dri_bo *buffer)
 111 {
 112    struct intel_region *region;
 113
 114    DBG("%s\n", __FUNCTION__);
 115
 116    if (buffer == NULL)
 117       return NULL;
 118
 119    region = calloc(sizeof(*region), 1);
 120    region->cpp = cpp;
 121    region->pitch = pitch;
 122    region->height = height;     /* needed? */
 123    region->refcount = 1;
 124    region->buffer = buffer;
 125
 126    /* Default to no tiling */
 127    region->tiling = I915_TILING_NONE;
 128    region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
 129
 130    return region;
 131 }
 132
 133 struct intel_region *
 134 intel_region_alloc(struct intel_context *intel,
 135                    GLuint cpp, GLuint pitch, GLuint height)
 136 {
 137    dri_bo *buffer;
 138
 139    buffer = dri_bo_alloc(intel->bufmgr, "region",
 140                          pitch * cpp * height, 64);
 141
 142    return intel_region_alloc_internal(intel, cpp, pitch, height, buffer);
 143 }
 144
 145 struct intel_region *
 146 intel_region_alloc_for_handle(struct intel_context *intel,
 147                               GLuint cpp, GLuint pitch, GLuint height,
 148                               GLuint handle, const char *name)
 149 {
 150    struct intel_region *region;
 151    dri_bo *buffer;
 152
 153    buffer = intel_bo_gem_create_from_name(intel->bufmgr, name, handle);
 154
 155    region = intel_region_alloc_internal(intel, cpp, pitch, height, buffer);
 156    if (region == NULL)
 157       return region;
 158
 159    intel_set_region_tiling_gem(intel, region, handle);
 160
 161    return region;
 162 }
 163
 164 void
 165 intel_region_reference(struct intel_region **dst, struct intel_region *src)
 166 {
 167    if (src)
 168       DBG("%s %d\n", __FUNCTION__, src->refcount);
 169
 170    assert(*dst == NULL);
 171    if (src) {
 172       src->refcount++;
 173       *dst = src;
 174    }
 175 }
 176
 177 void
 178 intel_region_release(struct intel_region **region_handle)
 179 {
 180    struct intel_region *region = *region_handle;
 181
 182    if (region == NULL)
 183       return;
 184
 185    DBG("%s %d\n", __FUNCTION__, region->refcount - 1);
 186
 187    ASSERT(region->refcount > 0);
 188    region->refcount--;
 189
 190    if (region->refcount == 0) {
 191       assert(region->map_refcount == 0);
 192
 193       if (region->pbo)
 194          region->pbo->region = NULL;
 195       region->pbo = NULL;
 196       dri_bo_unreference(region->buffer);
 197
 198       if (region->classic_map != NULL) {
 199          drmUnmap(region->classic_map,
 200                         region->pitch * region->cpp * region->height);
 201       }
 202
 203       free(region);
 204    }
 205    *region_handle = NULL;
 206 }
 207
 208 /*
 209  * XXX Move this into core Mesa?
 210  */
 211 void
 212 _mesa_copy_rect(GLubyte * dst,
 213                 GLuint cpp,
 214                 GLuint dst_pitch,
 215                 GLuint dst_x,
 216                 GLuint dst_y,
 217                 GLuint width,
 218                 GLuint height,
 219                 const GLubyte * src,
 220                 GLuint src_pitch, GLuint src_x, GLuint src_y)
 221 {
 222    GLuint i;
 223
 224    dst_pitch *= cpp;
 225    src_pitch *= cpp;
 226    dst += dst_x * cpp;
 227    src += src_x * cpp;
 228    dst += dst_y * dst_pitch;
 229    src += src_y * dst_pitch;
 230    width *= cpp;
 231
 232    if (width == dst_pitch && width == src_pitch)
 233       memcpy(dst, src, height * width);
 234    else {
 235       for (i = 0; i < height; i++) {
 236          memcpy(dst, src, width);
 237          dst += dst_pitch;
 238          src += src_pitch;
 239       }
 240    }
 241 }
 242
 243
 244 /* Upload data to a rectangular sub-region.  Lots of choices how to do this:
 245  *
 246  * - memcpy by span to current destination
 247  * - upload data as new buffer and blit
 248  *
 249  * Currently always memcpy.
 250  */
 251 void
 252 intel_region_data(struct intel_context *intel,
 253                   struct intel_region *dst,
 254                   GLuint dst_offset,
 255                   GLuint dstx, GLuint dsty,
 256                   const void *src, GLuint src_pitch,
 257                   GLuint srcx, GLuint srcy, GLuint width, GLuint height)
 258 {
 259    GLboolean locked = GL_FALSE;
 260
 261    DBG("%s\n", __FUNCTION__);
 262
 263    if (intel == NULL)
 264       return;
 265
 266    if (dst->pbo) {
 267       if (dstx == 0 &&
 268           dsty == 0 && width == dst->pitch && height == dst->height)
 269          intel_region_release_pbo(intel, dst);
 270       else
 271          intel_region_cow(intel, dst);
 272    }
 273
 274    if (!intel->locked) {
 275       LOCK_HARDWARE(intel);
 276       locked = GL_TRUE;
 277    }
 278
 279    _mesa_copy_rect(intel_region_map(intel, dst) + dst_offset,
 280                    dst->cpp,
 281                    dst->pitch,
 282                    dstx, dsty, width, height, src, src_pitch, srcx, srcy);
 283
 284    intel_region_unmap(intel, dst);
 285
 286    if (locked)
 287       UNLOCK_HARDWARE(intel);
 288
 289 }
 290
 291 /* Copy rectangular sub-regions. Need better logic about when to
 292  * push buffers into AGP - will currently do so whenever possible.
 293  */
 294 void
 295 intel_region_copy(struct intel_context *intel,
 296                   struct intel_region *dst,
 297                   GLuint dst_offset,
 298                   GLuint dstx, GLuint dsty,
 299                   struct intel_region *src,
 300                   GLuint src_offset,
 301                   GLuint srcx, GLuint srcy, GLuint width, GLuint height)
 302 {
 303    DBG("%s\n", __FUNCTION__);
 304
 305    if (intel == NULL)
 306       return;
 307
 308    if (dst->pbo) {
 309       if (dstx == 0 &&
 310           dsty == 0 && width == dst->pitch && height == dst->height)
 311          intel_region_release_pbo(intel, dst);
 312       else
 313          intel_region_cow(intel, dst);
 314    }
 315
 316    assert(src->cpp == dst->cpp);
 317
 318    intelEmitCopyBlit(intel,
 319                      dst->cpp,
 320                      src->pitch, src->buffer, src_offset, src->tiling,
 321                      dst->pitch, dst->buffer, dst_offset, dst->tiling,
 322                      srcx, srcy, dstx, dsty, width, height,
 323                      GL_COPY);
 324 }
 325
 326 /* Fill a rectangular sub-region.  Need better logic about when to
 327  * push buffers into AGP - will currently do so whenever possible.
 328  */
 329 void
 330 intel_region_fill(struct intel_context *intel,
 331                   struct intel_region *dst,
 332                   GLuint dst_offset,
 333                   GLuint dstx, GLuint dsty,
 334                   GLuint width, GLuint height, GLuint color)
 335 {
 336    DBG("%s\n", __FUNCTION__);
 337
 338    if (intel == NULL)
 339       return;
 340
 341    if (dst->pbo) {
 342       if (dstx == 0 &&
 343           dsty == 0 && width == dst->pitch && height == dst->height)
 344          intel_region_release_pbo(intel, dst);
 345       else
 346          intel_region_cow(intel, dst);
 347    }
 348
 349    intelEmitFillBlit(intel,
 350                      dst->cpp,
 351                      dst->pitch, dst->buffer, dst_offset, dst->tiling,
 352                      dstx, dsty, width, height, color);
 353 }
 354
 355 /* Attach to a pbo, discarding our data.  Effectively zero-copy upload
 356  * the pbo's data.
 357  */
 358 void
 359 intel_region_attach_pbo(struct intel_context *intel,
 360                         struct intel_region *region,
 361                         struct intel_buffer_object *pbo)
 362 {
 363    if (region->pbo == pbo)
 364       return;
 365
 366    /* If there is already a pbo attached, break the cow tie now.
 367     * Don't call intel_region_release_pbo() as that would
 368     * unnecessarily allocate a new buffer we would have to immediately
 369     * discard.
 370     */
 371    if (region->pbo) {
 372       region->pbo->region = NULL;
 373       region->pbo = NULL;
 374    }
 375
 376    if (region->buffer) {
 377       dri_bo_unreference(region->buffer);
 378       region->buffer = NULL;
 379    }
 380
 381    region->pbo = pbo;
 382    region->pbo->region = region;
 383    dri_bo_reference(pbo->buffer);
 384    region->buffer = pbo->buffer;
 385 }
 386
 387
 388 /* Break the COW tie to the pbo and allocate a new buffer.
 389  * The pbo gets to keep the data.
 390  */
 391 void
 392 intel_region_release_pbo(struct intel_context *intel,
 393                          struct intel_region *region)
 394 {
 395    assert(region->buffer == region->pbo->buffer);
 396    region->pbo->region = NULL;
 397    region->pbo = NULL;
 398    dri_bo_unreference(region->buffer);
 399    region->buffer = NULL;
 400
 401    region->buffer = dri_bo_alloc(intel->bufmgr, "region",
 402                                  region->pitch * region->cpp * region->height,
 403                                  64);
 404 }
 405
 406 /* Break the COW tie to the pbo.  Both the pbo and the region end up
 407  * with a copy of the data.
 408  */
 409 void
 410 intel_region_cow(struct intel_context *intel, struct intel_region *region)
 411 {
 412    struct intel_buffer_object *pbo = region->pbo;
 413    GLboolean was_locked = intel->locked;
 414
 415    if (intel == NULL)
 416       return;
 417
 418    intel_region_release_pbo(intel, region);
 419
 420    assert(region->cpp * region->pitch * region->height == pbo->Base.Size);
 421
 422    DBG("%s (%d bytes)\n", __FUNCTION__, pbo->Base.Size);
 423
 424    /* Now blit from the texture buffer to the new buffer:
 425     */
 426
 427    was_locked = intel->locked;
 428    if (!was_locked)
 429       LOCK_HARDWARE(intel);
 430
 431    intelEmitCopyBlit(intel,
 432                      region->cpp,
 433                      region->pitch, region->buffer, 0, region->tiling,
 434                      region->pitch, pbo->buffer, 0, region->tiling,
 435                      0, 0, 0, 0,
 436                      region->pitch, region->height,
 437                      GL_COPY);
 438
 439    if (!was_locked)
 440       UNLOCK_HARDWARE(intel);
 441 }
 442
 443 dri_bo *
 444 intel_region_buffer(struct intel_context *intel,
 445                     struct intel_region *region, GLuint flag)
 446 {
 447    if (region->pbo) {
 448       if (flag == INTEL_WRITE_PART)
 449          intel_region_cow(intel, region);
 450       else if (flag == INTEL_WRITE_FULL)
 451          intel_region_release_pbo(intel, region);
 452    }
 453
 454    return region->buffer;
 455 }
 456
 457 static struct intel_region *
 458 intel_recreate_static(struct intel_context *intel,
 459                       const char *name,
 460                       struct intel_region *region,
 461                       intelRegion *region_desc)
 462 {
 463    intelScreenPrivate *intelScreen = intel->intelScreen;
 464    int ret;
 465
 466    if (region == NULL) {
 467       region = calloc(sizeof(*region), 1);
 468       region->refcount = 1;
 469    }
 470
 471    if (intel->ctx.Visual.rgbBits == 24)
 472       region->cpp = 4;
 473    else
 474       region->cpp = intel->ctx.Visual.rgbBits / 8;
 475    region->pitch = intelScreen->pitch;
 476    region->height = intelScreen->height;     /* needed? */
 477
 478    if (intel->ttm) {
 479       assert(region_desc->bo_handle != -1);
 480       region->buffer = intel_bo_gem_create_from_name(intel->bufmgr,
 481                                                      name,
 482                                                      region_desc->bo_handle);
 483
 484       intel_set_region_tiling_gem(intel, region, region_desc->bo_handle);
 485    } else {
 486       ret = drmMap(intel->driFd, region_desc->handle,
 487                    region->pitch * region->cpp * region->height,
 488                    &region->classic_map);
 489       if (ret != 0) {
 490          fprintf(stderr, "Failed to drmMap %s buffer\n", name);
 491          free(region);
 492          return NULL;
 493       }
 494
 495       region->buffer = intel_bo_fake_alloc_static(intel->bufmgr,
 496                                                   name,
 497                                                   region_desc->offset,
 498                                                   region->pitch * region->cpp *
 499                                                   region->height,
 500                                                   region->classic_map);
 501
 502       /* The sarea just gives us a boolean for whether it's tiled or not,
 503        * instead of which tiling mode it is.  Guess.
 504        */
 505       if (region_desc->tiled) {
 506          if (IS_965(intel->intelScreen->deviceID) &&
 507              region_desc == &intelScreen->depth)
 508             region->tiling = I915_TILING_Y;
 509          else
 510             region->tiling = I915_TILING_X;
 511       } else {
 512          region->tiling = I915_TILING_NONE;
 513       }
 514
 515       region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
 516    }
 517
 518    assert(region->buffer != NULL);
 519
 520    return region;
 521 }
 522
 523 /**
 524  * Create intel_region structs to describe the static front, back, and depth
 525  * buffers created by the xserver.
 526  *
 527  * Although FBO's mean we now no longer use these as render targets in
 528  * all circumstances, they won't go away until the back and depth
 529  * buffers become private, and the front buffer will remain even then.
 530  *
 531  * Note that these don't allocate video memory, just describe
 532  * allocations alread made by the X server.
 533  */
 534 void
 535 intel_recreate_static_regions(struct intel_context *intel)
 536 {
 537    intelScreenPrivate *intelScreen = intel->intelScreen;
 538
 539    intel->front_region =
 540       intel_recreate_static(intel, "front",
 541                             intel->front_region,
 542                             &intelScreen->front);
 543
 544    intel->back_region =
 545       intel_recreate_static(intel, "back",
 546                             intel->back_region,
 547                             &intelScreen->back);
 548
 549 #ifdef I915
 550    if (intelScreen->third.handle) {
 551       intel->third_region =
 552          intel_recreate_static(intel, "third",
 553                                intel->third_region,
 554                                &intelScreen->third);
 555    }
 556 #endif /* I915 */
 557
 558    /* Still assumes front.cpp == depth.cpp.  We can kill this when we move to
 559     * private buffers.
 560     */
 561    intel->depth_region =
 562       intel_recreate_static(intel, "depth",
 563                             intel->depth_region,
 564                             &intelScreen->depth);
 565 }