Merge branch 'master' into asm-shader-rework-1
[mesa.git] / src / mesa / drivers / dri / intel / intel_regions.c
1 /**************************************************************************
2 *
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /* Provide additional functionality on top of bufmgr buffers:
29 * - 2d semantics and blit operations
30 * - refcounting of buffers for multiple images in a buffer.
31 * - refcounting of buffer mappings.
32 * - some logic for moving the buffers to the best memory pools for
33 * given operations.
34 *
35 * Most of this is to make it easier to implement the fixed-layout
36 * mipmap tree required by intel hardware in the face of GL's
37 * programming interface where each image can be specifed in random
38 * order and it isn't clear what layout the tree should have until the
39 * last moment.
40 */
41
42 #include <sys/ioctl.h>
43 #include <errno.h>
44
45 #include "intel_context.h"
46 #include "intel_regions.h"
47 #include "intel_blit.h"
48 #include "intel_buffer_objects.h"
49 #include "intel_bufmgr.h"
50 #include "intel_batchbuffer.h"
51 #include "intel_chipset.h"
52
53 #define FILE_DEBUG_FLAG DEBUG_REGION
54
55 /* This should be set to the maximum backtrace size desired.
56 * Set it to 0 to disable backtrace debugging.
57 */
58 #define DEBUG_BACKTRACE_SIZE 0
59
60 #if DEBUG_BACKTRACE_SIZE == 0
61 /* Use the standard debug output */
62 #define _DBG(...) DBG(__VA_ARGS__)
63 #else
64 /* Use backtracing debug output */
65 #define _DBG(...) {debug_backtrace(); DBG(__VA_ARGS__);}
66
67 /* Backtracing debug support */
68 #include <execinfo.h>
69
70 static void
71 debug_backtrace(void)
72 {
73 void *trace[DEBUG_BACKTRACE_SIZE];
74 char **strings = NULL;
75 int traceSize;
76 register int i;
77
78 traceSize = backtrace(trace, DEBUG_BACKTRACE_SIZE);
79 strings = backtrace_symbols(trace, traceSize);
80 if (strings == NULL) {
81 DBG("no backtrace:");
82 return;
83 }
84
85 /* Spit out all the strings with a colon separator. Ignore
86 * the first, since we don't really care about the call
87 * to debug_backtrace() itself. Skip until the final "/" in
88 * the trace to avoid really long lines.
89 */
90 for (i = 1; i < traceSize; i++) {
91 char *p = strings[i], *slash = strings[i];
92 while (*p) {
93 if (*p++ == '/') {
94 slash = p;
95 }
96 }
97
98 DBG("%s:", slash);
99 }
100
101 /* Free up the memory, and we're done */
102 free(strings);
103 }
104
105 #endif
106
107
108
109 /* XXX: Thread safety?
110 */
111 GLubyte *
112 intel_region_map(struct intel_context *intel, struct intel_region *region)
113 {
114 intelFlush(&intel->ctx);
115
116 _DBG("%s %p\n", __FUNCTION__, region);
117 if (!region->map_refcount++) {
118 if (region->pbo)
119 intel_region_cow(intel, region);
120
121 if (region->tiling != I915_TILING_NONE &&
122 intel->intelScreen->kernel_exec_fencing)
123 drm_intel_gem_bo_map_gtt(region->buffer);
124 else
125 dri_bo_map(region->buffer, GL_TRUE);
126 region->map = region->buffer->virtual;
127 }
128
129 return region->map;
130 }
131
132 void
133 intel_region_unmap(struct intel_context *intel, struct intel_region *region)
134 {
135 _DBG("%s %p\n", __FUNCTION__, region);
136 if (!--region->map_refcount) {
137 if (region->tiling != I915_TILING_NONE &&
138 intel->intelScreen->kernel_exec_fencing)
139 drm_intel_gem_bo_unmap_gtt(region->buffer);
140 else
141 dri_bo_unmap(region->buffer);
142 region->map = NULL;
143 }
144 }
145
146 static struct intel_region *
147 intel_region_alloc_internal(struct intel_context *intel,
148 GLuint cpp,
149 GLuint width, GLuint height, GLuint pitch,
150 dri_bo *buffer)
151 {
152 struct intel_region *region;
153
154 if (buffer == NULL) {
155 _DBG("%s <-- NULL\n", __FUNCTION__);
156 return NULL;
157 }
158
159 region = calloc(sizeof(*region), 1);
160 region->cpp = cpp;
161 region->width = width;
162 region->height = height;
163 region->pitch = pitch;
164 region->refcount = 1;
165 region->buffer = buffer;
166
167 /* Default to no tiling */
168 region->tiling = I915_TILING_NONE;
169 region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
170
171 _DBG("%s <-- %p\n", __FUNCTION__, region);
172 return region;
173 }
174
175 struct intel_region *
176 intel_region_alloc(struct intel_context *intel,
177 uint32_t tiling,
178 GLuint cpp, GLuint width, GLuint height, GLuint pitch,
179 GLboolean expect_accelerated_upload)
180 {
181 dri_bo *buffer;
182 struct intel_region *region;
183
184 if (tiling == I915_TILING_X)
185 height = ALIGN(height, 8);
186 else if (tiling == I915_TILING_Y)
187 height = ALIGN(height, 32);
188
189 if (expect_accelerated_upload) {
190 buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
191 pitch * cpp * height, 64);
192 } else {
193 buffer = drm_intel_bo_alloc(intel->bufmgr, "region",
194 pitch * cpp * height, 64);
195 }
196
197 region = intel_region_alloc_internal(intel, cpp, width, height,
198 pitch, buffer);
199
200 if (tiling != I915_TILING_NONE) {
201 assert(((pitch * cpp) & 127) == 0);
202 drm_intel_bo_set_tiling(buffer, &tiling, pitch * cpp);
203 drm_intel_bo_get_tiling(buffer, &region->tiling, &region->bit_6_swizzle);
204 }
205
206 return region;
207 }
208
209 struct intel_region *
210 intel_region_alloc_for_handle(struct intel_context *intel,
211 GLuint cpp,
212 GLuint width, GLuint height, GLuint pitch,
213 GLuint handle, const char *name)
214 {
215 struct intel_region *region;
216 dri_bo *buffer;
217 int ret;
218
219 buffer = intel_bo_gem_create_from_name(intel->bufmgr, name, handle);
220
221 region = intel_region_alloc_internal(intel, cpp,
222 width, height, pitch, buffer);
223 if (region == NULL)
224 return region;
225
226 ret = dri_bo_get_tiling(region->buffer, &region->tiling,
227 &region->bit_6_swizzle);
228 if (ret != 0) {
229 fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",
230 handle, name, strerror(-ret));
231 intel_region_release(&region);
232 return NULL;
233 }
234
235 return region;
236 }
237
238 void
239 intel_region_reference(struct intel_region **dst, struct intel_region *src)
240 {
241 if (src)
242 _DBG("%s %p %d\n", __FUNCTION__, src, src->refcount);
243
244 assert(*dst == NULL);
245 if (src) {
246 src->refcount++;
247 *dst = src;
248 }
249 }
250
251 void
252 intel_region_release(struct intel_region **region_handle)
253 {
254 struct intel_region *region = *region_handle;
255
256 if (region == NULL) {
257 _DBG("%s NULL\n", __FUNCTION__);
258 return;
259 }
260
261 _DBG("%s %p %d\n", __FUNCTION__, region, region->refcount - 1);
262
263 ASSERT(region->refcount > 0);
264 region->refcount--;
265
266 if (region->refcount == 0) {
267 assert(region->map_refcount == 0);
268
269 if (region->pbo)
270 region->pbo->region = NULL;
271 region->pbo = NULL;
272 dri_bo_unreference(region->buffer);
273
274 if (region->classic_map != NULL) {
275 drmUnmap(region->classic_map,
276 region->pitch * region->cpp * region->height);
277 }
278
279 free(region);
280 }
281 *region_handle = NULL;
282 }
283
284 /*
285 * XXX Move this into core Mesa?
286 */
287 void
288 _mesa_copy_rect(GLubyte * dst,
289 GLuint cpp,
290 GLuint dst_pitch,
291 GLuint dst_x,
292 GLuint dst_y,
293 GLuint width,
294 GLuint height,
295 const GLubyte * src,
296 GLuint src_pitch, GLuint src_x, GLuint src_y)
297 {
298 GLuint i;
299
300 dst_pitch *= cpp;
301 src_pitch *= cpp;
302 dst += dst_x * cpp;
303 src += src_x * cpp;
304 dst += dst_y * dst_pitch;
305 src += src_y * dst_pitch;
306 width *= cpp;
307
308 if (width == dst_pitch && width == src_pitch)
309 memcpy(dst, src, height * width);
310 else {
311 for (i = 0; i < height; i++) {
312 memcpy(dst, src, width);
313 dst += dst_pitch;
314 src += src_pitch;
315 }
316 }
317 }
318
319
320 /* Upload data to a rectangular sub-region. Lots of choices how to do this:
321 *
322 * - memcpy by span to current destination
323 * - upload data as new buffer and blit
324 *
325 * Currently always memcpy.
326 */
327 void
328 intel_region_data(struct intel_context *intel,
329 struct intel_region *dst,
330 GLuint dst_offset,
331 GLuint dstx, GLuint dsty,
332 const void *src, GLuint src_pitch,
333 GLuint srcx, GLuint srcy, GLuint width, GLuint height)
334 {
335 _DBG("%s\n", __FUNCTION__);
336
337 if (intel == NULL)
338 return;
339
340 if (dst->pbo) {
341 if (dstx == 0 &&
342 dsty == 0 && width == dst->pitch && height == dst->height)
343 intel_region_release_pbo(intel, dst);
344 else
345 intel_region_cow(intel, dst);
346 }
347
348 LOCK_HARDWARE(intel);
349 _mesa_copy_rect(intel_region_map(intel, dst) + dst_offset,
350 dst->cpp,
351 dst->pitch,
352 dstx, dsty, width, height, src, src_pitch, srcx, srcy);
353
354 intel_region_unmap(intel, dst);
355 UNLOCK_HARDWARE(intel);
356 }
357
358 /* Copy rectangular sub-regions. Need better logic about when to
359 * push buffers into AGP - will currently do so whenever possible.
360 */
361 GLboolean
362 intel_region_copy(struct intel_context *intel,
363 struct intel_region *dst,
364 GLuint dst_offset,
365 GLuint dstx, GLuint dsty,
366 struct intel_region *src,
367 GLuint src_offset,
368 GLuint srcx, GLuint srcy, GLuint width, GLuint height,
369 GLenum logicop)
370 {
371 _DBG("%s\n", __FUNCTION__);
372
373 if (intel == NULL)
374 return GL_FALSE;
375
376 if (dst->pbo) {
377 if (dstx == 0 &&
378 dsty == 0 && width == dst->pitch && height == dst->height)
379 intel_region_release_pbo(intel, dst);
380 else
381 intel_region_cow(intel, dst);
382 }
383
384 assert(src->cpp == dst->cpp);
385
386 return intelEmitCopyBlit(intel,
387 dst->cpp,
388 src->pitch, src->buffer, src_offset, src->tiling,
389 dst->pitch, dst->buffer, dst_offset, dst->tiling,
390 srcx, srcy, dstx, dsty, width, height,
391 logicop);
392 }
393
394 /* Attach to a pbo, discarding our data. Effectively zero-copy upload
395 * the pbo's data.
396 */
397 void
398 intel_region_attach_pbo(struct intel_context *intel,
399 struct intel_region *region,
400 struct intel_buffer_object *pbo)
401 {
402 dri_bo *buffer;
403
404 if (region->pbo == pbo)
405 return;
406
407 _DBG("%s %p %p\n", __FUNCTION__, region, pbo);
408
409 /* If there is already a pbo attached, break the cow tie now.
410 * Don't call intel_region_release_pbo() as that would
411 * unnecessarily allocate a new buffer we would have to immediately
412 * discard.
413 */
414 if (region->pbo) {
415 region->pbo->region = NULL;
416 region->pbo = NULL;
417 }
418
419 if (region->buffer) {
420 dri_bo_unreference(region->buffer);
421 region->buffer = NULL;
422 }
423
424 /* make sure pbo has a buffer of its own */
425 buffer = intel_bufferobj_buffer(intel, pbo, INTEL_WRITE_FULL);
426
427 region->pbo = pbo;
428 region->pbo->region = region;
429 dri_bo_reference(buffer);
430 region->buffer = buffer;
431 }
432
433
434 /* Break the COW tie to the pbo and allocate a new buffer.
435 * The pbo gets to keep the data.
436 */
437 void
438 intel_region_release_pbo(struct intel_context *intel,
439 struct intel_region *region)
440 {
441 _DBG("%s %p\n", __FUNCTION__, region);
442 assert(region->buffer == region->pbo->buffer);
443 region->pbo->region = NULL;
444 region->pbo = NULL;
445 dri_bo_unreference(region->buffer);
446 region->buffer = NULL;
447
448 region->buffer = dri_bo_alloc(intel->bufmgr, "region",
449 region->pitch * region->cpp * region->height,
450 64);
451 }
452
453 /* Break the COW tie to the pbo. Both the pbo and the region end up
454 * with a copy of the data.
455 */
456 void
457 intel_region_cow(struct intel_context *intel, struct intel_region *region)
458 {
459 struct intel_buffer_object *pbo = region->pbo;
460 GLboolean ok;
461
462 intel_region_release_pbo(intel, region);
463
464 assert(region->cpp * region->pitch * region->height == pbo->Base.Size);
465
466 _DBG("%s %p (%d bytes)\n", __FUNCTION__, region, pbo->Base.Size);
467
468 /* Now blit from the texture buffer to the new buffer:
469 */
470
471 LOCK_HARDWARE(intel);
472 ok = intelEmitCopyBlit(intel,
473 region->cpp,
474 region->pitch, pbo->buffer, 0, region->tiling,
475 region->pitch, region->buffer, 0, region->tiling,
476 0, 0, 0, 0,
477 region->pitch, region->height,
478 GL_COPY);
479 assert(ok);
480 UNLOCK_HARDWARE(intel);
481 }
482
483 dri_bo *
484 intel_region_buffer(struct intel_context *intel,
485 struct intel_region *region, GLuint flag)
486 {
487 if (region->pbo) {
488 if (flag == INTEL_WRITE_PART)
489 intel_region_cow(intel, region);
490 else if (flag == INTEL_WRITE_FULL)
491 intel_region_release_pbo(intel, region);
492 }
493
494 return region->buffer;
495 }
496
497 static struct intel_region *
498 intel_recreate_static(struct intel_context *intel,
499 const char *name,
500 struct intel_region *region,
501 intelRegion *region_desc)
502 {
503 intelScreenPrivate *intelScreen = intel->intelScreen;
504 int ret;
505
506 if (region == NULL) {
507 region = calloc(sizeof(*region), 1);
508 region->refcount = 1;
509 _DBG("%s creating new region %p\n", __FUNCTION__, region);
510 }
511 else {
512 _DBG("%s %p\n", __FUNCTION__, region);
513 }
514
515 if (intel->ctx.Visual.rgbBits == 24)
516 region->cpp = 4;
517 else
518 region->cpp = intel->ctx.Visual.rgbBits / 8;
519 region->pitch = intelScreen->pitch;
520 region->width = intelScreen->width;
521 region->height = intelScreen->height;
522
523 if (region->buffer != NULL) {
524 dri_bo_unreference(region->buffer);
525 region->buffer = NULL;
526 }
527
528 if (intel->ttm) {
529 assert(region_desc->bo_handle != -1);
530 region->buffer = intel_bo_gem_create_from_name(intel->bufmgr,
531 name,
532 region_desc->bo_handle);
533
534 ret = dri_bo_get_tiling(region->buffer, &region->tiling,
535 &region->bit_6_swizzle);
536 if (ret != 0) {
537 fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",
538 region_desc->bo_handle, name, strerror(-ret));
539 intel_region_release(&region);
540 return NULL;
541 }
542 } else {
543 if (region->classic_map != NULL) {
544 drmUnmap(region->classic_map,
545 region->pitch * region->cpp * region->height);
546 region->classic_map = NULL;
547 }
548 ret = drmMap(intel->driFd, region_desc->handle,
549 region->pitch * region->cpp * region->height,
550 &region->classic_map);
551 if (ret != 0) {
552 fprintf(stderr, "Failed to drmMap %s buffer\n", name);
553 free(region);
554 return NULL;
555 }
556
557 region->buffer = intel_bo_fake_alloc_static(intel->bufmgr,
558 name,
559 region_desc->offset,
560 region->pitch * region->cpp *
561 region->height,
562 region->classic_map);
563
564 /* The sarea just gives us a boolean for whether it's tiled or not,
565 * instead of which tiling mode it is. Guess.
566 */
567 if (region_desc->tiled) {
568 if (IS_965(intel->intelScreen->deviceID) &&
569 region_desc == &intelScreen->depth)
570 region->tiling = I915_TILING_Y;
571 else
572 region->tiling = I915_TILING_X;
573 } else {
574 region->tiling = I915_TILING_NONE;
575 }
576
577 region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
578 }
579
580 assert(region->buffer != NULL);
581
582 return region;
583 }
584
585 /**
586 * Create intel_region structs to describe the static front, back, and depth
587 * buffers created by the xserver.
588 *
589 * Although FBO's mean we now no longer use these as render targets in
590 * all circumstances, they won't go away until the back and depth
591 * buffers become private, and the front buffer will remain even then.
592 *
593 * Note that these don't allocate video memory, just describe
594 * allocations alread made by the X server.
595 */
596 void
597 intel_recreate_static_regions(struct intel_context *intel)
598 {
599 intelScreenPrivate *intelScreen = intel->intelScreen;
600
601 intel->front_region =
602 intel_recreate_static(intel, "front",
603 intel->front_region,
604 &intelScreen->front);
605
606 intel->back_region =
607 intel_recreate_static(intel, "back",
608 intel->back_region,
609 &intelScreen->back);
610
611 /* Still assumes front.cpp == depth.cpp. We can kill this when we move to
612 * private buffers.
613 */
614 intel->depth_region =
615 intel_recreate_static(intel, "depth",
616 intel->depth_region,
617 &intelScreen->depth);
618 }