1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "main/glheader.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "main/colormac.h"
32 #include "main/texformat.h"
34 #include "intel_buffers.h"
35 #include "intel_fbo.h"
36 #include "intel_screen.h"
37 #include "intel_span.h"
38 #include "intel_regions.h"
39 #include "intel_tex.h"
41 #include "swrast/swrast.h"
44 intel_set_span_functions(struct intel_context
*intel
,
45 struct gl_renderbuffer
*rb
);
47 #define SPAN_CACHE_SIZE 4096
50 get_span_cache(struct intel_renderbuffer
*irb
, uint32_t offset
)
52 if (irb
->span_cache
== NULL
) {
53 irb
->span_cache
= _mesa_malloc(SPAN_CACHE_SIZE
);
54 irb
->span_cache_offset
= -1;
57 if ((offset
& ~(SPAN_CACHE_SIZE
- 1)) != irb
->span_cache_offset
) {
58 irb
->span_cache_offset
= offset
& ~(SPAN_CACHE_SIZE
- 1);
59 dri_bo_get_subdata(irb
->region
->buffer
, irb
->span_cache_offset
,
60 SPAN_CACHE_SIZE
, irb
->span_cache
);
65 clear_span_cache(struct intel_renderbuffer
*irb
)
67 irb
->span_cache_offset
= -1;
71 pread_32(struct intel_renderbuffer
*irb
, uint32_t offset
)
73 get_span_cache(irb
, offset
);
75 return *(uint32_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1)));
79 pread_xrgb8888(struct intel_renderbuffer
*irb
, uint32_t offset
)
81 get_span_cache(irb
, offset
);
83 return *(uint32_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1))) |
88 pread_16(struct intel_renderbuffer
*irb
, uint32_t offset
)
90 get_span_cache(irb
, offset
);
92 return *(uint16_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1)));
96 pread_8(struct intel_renderbuffer
*irb
, uint32_t offset
)
98 get_span_cache(irb
, offset
);
100 return *(uint8_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1)));
104 pwrite_32(struct intel_renderbuffer
*irb
, uint32_t offset
, uint32_t val
)
106 clear_span_cache(irb
);
108 dri_bo_subdata(irb
->region
->buffer
, offset
, 4, &val
);
112 pwrite_xrgb8888(struct intel_renderbuffer
*irb
, uint32_t offset
, uint32_t val
)
114 clear_span_cache(irb
);
116 dri_bo_subdata(irb
->region
->buffer
, offset
, 3, &val
);
120 pwrite_16(struct intel_renderbuffer
*irb
, uint32_t offset
, uint16_t val
)
122 clear_span_cache(irb
);
124 dri_bo_subdata(irb
->region
->buffer
, offset
, 2, &val
);
128 pwrite_8(struct intel_renderbuffer
*irb
, uint32_t offset
, uint8_t val
)
130 clear_span_cache(irb
);
132 dri_bo_subdata(irb
->region
->buffer
, offset
, 1, &val
);
136 z24s8_to_s8z24(uint32_t val
)
138 return (val
<< 24) | (val
>> 8);
142 s8z24_to_z24s8(uint32_t val
)
144 return (val
>> 24) | (val
<< 8);
147 static uint32_t no_tile_swizzle(struct intel_renderbuffer
*irb
,
150 return (y
* irb
->region
->pitch
+ x
) * irb
->region
->cpp
;
154 * Deal with tiled surfaces
157 static uint32_t x_tile_swizzle(struct intel_renderbuffer
*irb
,
162 int x_tile_off
, y_tile_off
;
163 int x_tile_number
, y_tile_number
;
164 int tile_off
, tile_base
;
166 tile_stride
= (irb
->region
->pitch
* irb
->region
->cpp
) << 3;
168 xbyte
= x
* irb
->region
->cpp
;
170 x_tile_off
= xbyte
& 0x1ff;
173 x_tile_number
= xbyte
>> 9;
174 y_tile_number
= y
>> 3;
176 tile_off
= (y_tile_off
<< 9) + x_tile_off
;
178 switch (irb
->region
->bit_6_swizzle
) {
179 case I915_BIT_6_SWIZZLE_NONE
:
181 case I915_BIT_6_SWIZZLE_9
:
182 tile_off
^= ((tile_off
>> 3) & 64);
184 case I915_BIT_6_SWIZZLE_9_10
:
185 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64);
187 case I915_BIT_6_SWIZZLE_9_11
:
188 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 5) & 64);
190 case I915_BIT_6_SWIZZLE_9_10_11
:
191 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64) ^
192 ((tile_off
>> 5) & 64);
195 fprintf(stderr
, "Unknown tile swizzling mode %d\n",
196 irb
->region
->bit_6_swizzle
);
200 tile_base
= (x_tile_number
<< 12) + y_tile_number
* tile_stride
;
203 printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
204 x
, y
, tile_off
, tile_base
,
205 tile_off
+ tile_base
,
206 irb
->region
->pitch
, tile_stride
);
209 return tile_base
+ tile_off
;
212 static uint32_t y_tile_swizzle(struct intel_renderbuffer
*irb
,
217 int x_tile_off
, y_tile_off
;
218 int x_tile_number
, y_tile_number
;
219 int tile_off
, tile_base
;
221 tile_stride
= (irb
->region
->pitch
* irb
->region
->cpp
) << 5;
223 xbyte
= x
* irb
->region
->cpp
;
225 x_tile_off
= xbyte
& 0x7f;
226 y_tile_off
= y
& 0x1f;
228 x_tile_number
= xbyte
>> 7;
229 y_tile_number
= y
>> 5;
231 tile_off
= ((x_tile_off
& ~0xf) << 5) + (y_tile_off
<< 4) +
234 switch (irb
->region
->bit_6_swizzle
) {
235 case I915_BIT_6_SWIZZLE_NONE
:
237 case I915_BIT_6_SWIZZLE_9
:
238 tile_off
^= ((tile_off
>> 3) & 64);
240 case I915_BIT_6_SWIZZLE_9_10
:
241 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64);
243 case I915_BIT_6_SWIZZLE_9_11
:
244 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 5) & 64);
246 case I915_BIT_6_SWIZZLE_9_10_11
:
247 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64) ^
248 ((tile_off
>> 5) & 64);
251 fprintf(stderr
, "Unknown tile swizzling mode %d\n",
252 irb
->region
->bit_6_swizzle
);
256 tile_base
= (x_tile_number
<< 12) + y_tile_number
* tile_stride
;
258 return tile_base
+ tile_off
;
262 break intelWriteRGBASpan_ARGB8888
269 struct intel_context *intel = intel_context(ctx); \
270 struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
271 const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \
272 const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
273 unsigned int num_cliprects; \
274 struct drm_clip_rect *cliprects; \
278 intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
280 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
281 * the cliprect info from the context, not the driDrawable.
282 * Move this into spantmp2.h someday.
284 #define HW_CLIPLOOP() \
286 int _nc = num_cliprects; \
288 int minx = cliprects[_nc].x1 - x_off; \
289 int miny = cliprects[_nc].y1 - y_off; \
290 int maxx = cliprects[_nc].x2 - x_off; \
291 int maxy = cliprects[_nc].y2 - y_off;
297 #define Y_FLIP(_y) ((_y) * yScale + yBias)
299 /* XXX with GEM, these need to tell the kernel */
304 /* Convenience macros to avoid typing the swizzle argument over and over */
305 #define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
306 #define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
307 #define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
309 /* r5g6b5 color span and pixel functions */
310 #define INTEL_PIXEL_FMT GL_RGB
311 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
312 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
313 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
314 #define INTEL_TAG(x) x##_RGB565
315 #include "intel_spantmp.h"
317 /* a4r4g4b4 color span and pixel functions */
318 #define INTEL_PIXEL_FMT GL_BGRA
319 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
320 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
321 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
322 #define INTEL_TAG(x) x##_ARGB4444
323 #include "intel_spantmp.h"
325 /* a1r5g5b5 color span and pixel functions */
326 #define INTEL_PIXEL_FMT GL_BGRA
327 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
328 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
329 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
330 #define INTEL_TAG(x) x##_ARGB1555
331 #include "intel_spantmp.h"
333 /* a8r8g8b8 color span and pixel functions */
334 #define INTEL_PIXEL_FMT GL_BGRA
335 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
336 #define INTEL_READ_VALUE(offset) pread_32(irb, offset)
337 #define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v)
338 #define INTEL_TAG(x) x##_ARGB8888
339 #include "intel_spantmp.h"
341 /* x8r8g8b8 color span and pixel functions */
342 #define INTEL_PIXEL_FMT GL_BGRA
343 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
344 #define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
345 #define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
346 #define INTEL_TAG(x) x##_xRGB8888
347 #include "intel_spantmp.h"
349 #define LOCAL_DEPTH_VARS \
350 struct intel_context *intel = intel_context(ctx); \
351 struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
352 const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \
353 const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
354 unsigned int num_cliprects; \
355 struct drm_clip_rect *cliprects; \
357 intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
360 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
362 /* z16 depthbuffer functions. */
363 #define INTEL_VALUE_TYPE GLushort
364 #define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d)
365 #define INTEL_READ_DEPTH(offset) pread_16(irb, offset)
366 #define INTEL_TAG(name) name##_z16
367 #include "intel_depthtmp.h"
369 /* z24 depthbuffer functions. */
370 #define INTEL_VALUE_TYPE GLuint
371 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
372 #define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
373 #define INTEL_TAG(name) name##_z24
374 #include "intel_depthtmp.h"
376 /* z24s8 depthbuffer functions. */
377 #define INTEL_VALUE_TYPE GLuint
378 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, z24s8_to_s8z24(d))
379 #define INTEL_READ_DEPTH(offset) s8z24_to_z24s8(pread_32(irb, offset))
380 #define INTEL_TAG(name) name##_z24_s8
381 #include "intel_depthtmp.h"
385 ** 8-bit stencil function (XXX FBO: This is obsolete)
387 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
388 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
389 #define TAG(x) intel##x##_z24_s8
390 #include "stenciltmp.h"
393 ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
395 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, X_TILE(_x, _y) + 3, d)
396 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, X_TILE(_x, _y) + 3);
397 #define TAG(x) intel_XTile_##x##_z24_s8
398 #include "stenciltmp.h"
401 ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
403 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, Y_TILE(_x, _y) + 3, d)
404 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, Y_TILE(_x, _y) + 3)
405 #define TAG(x) intel_YTile_##x##_z24_s8
406 #include "stenciltmp.h"
409 intel_renderbuffer_map(struct intel_context
*intel
, struct gl_renderbuffer
*rb
)
411 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
413 if (irb
== NULL
|| irb
->region
== NULL
)
416 intel_set_span_functions(intel
, rb
);
420 intel_renderbuffer_unmap(struct intel_context
*intel
,
421 struct gl_renderbuffer
*rb
)
423 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
425 if (irb
== NULL
|| irb
->region
== NULL
)
428 clear_span_cache(irb
);
435 * Map or unmap all the renderbuffers which we may need during
436 * software rendering.
437 * XXX in the future, we could probably convey extra information to
438 * reduce the number of mappings needed. I.e. if doing a glReadPixels
439 * from the depth buffer, we really only need one mapping.
441 * XXX Rewrite this function someday.
442 * We can probably just loop over all the renderbuffer attachments,
443 * map/unmap all of them, and not worry about the _ColorDrawBuffers
444 * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
447 intel_map_unmap_buffers(struct intel_context
*intel
, GLboolean map
)
449 GLcontext
*ctx
= &intel
->ctx
;
452 /* color draw buffers */
453 for (j
= 0; j
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; j
++) {
455 intel_renderbuffer_map(intel
, ctx
->DrawBuffer
->_ColorDrawBuffers
[j
]);
457 intel_renderbuffer_unmap(intel
, ctx
->DrawBuffer
->_ColorDrawBuffers
[j
]);
460 /* check for render to textures */
461 for (i
= 0; i
< BUFFER_COUNT
; i
++) {
462 struct gl_renderbuffer_attachment
*att
=
463 ctx
->DrawBuffer
->Attachment
+ i
;
464 struct gl_texture_object
*tex
= att
->Texture
;
466 /* render to texture */
467 ASSERT(att
->Renderbuffer
);
469 intel_tex_map_images(intel
, intel_texture_object(tex
));
471 intel_tex_unmap_images(intel
, intel_texture_object(tex
));
475 /* color read buffers */
477 intel_renderbuffer_map(intel
, ctx
->ReadBuffer
->_ColorReadBuffer
);
479 intel_renderbuffer_unmap(intel
, ctx
->ReadBuffer
->_ColorReadBuffer
);
481 /* depth buffer (Note wrapper!) */
482 if (ctx
->DrawBuffer
->_DepthBuffer
) {
484 intel_renderbuffer_map(intel
, ctx
->DrawBuffer
->_DepthBuffer
->Wrapped
);
486 intel_renderbuffer_unmap(intel
,
487 ctx
->DrawBuffer
->_DepthBuffer
->Wrapped
);
490 /* stencil buffer (Note wrapper!) */
491 if (ctx
->DrawBuffer
->_StencilBuffer
) {
493 intel_renderbuffer_map(intel
,
494 ctx
->DrawBuffer
->_StencilBuffer
->Wrapped
);
496 intel_renderbuffer_unmap(intel
,
497 ctx
->DrawBuffer
->_StencilBuffer
->Wrapped
);
504 * Prepare for softare rendering. Map current read/draw framebuffers'
505 * renderbuffes and all currently bound texture objects.
507 * Old note: Moved locking out to get reasonable span performance.
510 intelSpanRenderStart(GLcontext
* ctx
)
512 struct intel_context
*intel
= intel_context(ctx
);
515 intelFlush(&intel
->ctx
);
516 LOCK_HARDWARE(intel
);
518 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
519 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
520 struct gl_texture_object
*texObj
= ctx
->Texture
.Unit
[i
]._Current
;
521 intel_tex_map_images(intel
, intel_texture_object(texObj
));
525 intel_map_unmap_buffers(intel
, GL_TRUE
);
529 * Called when done softare rendering. Unmap the buffers we mapped in
530 * the above function.
533 intelSpanRenderFinish(GLcontext
* ctx
)
535 struct intel_context
*intel
= intel_context(ctx
);
540 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
541 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
542 struct gl_texture_object
*texObj
= ctx
->Texture
.Unit
[i
]._Current
;
543 intel_tex_unmap_images(intel
, intel_texture_object(texObj
));
547 intel_map_unmap_buffers(intel
, GL_FALSE
);
549 UNLOCK_HARDWARE(intel
);
554 intelInitSpanFuncs(GLcontext
* ctx
)
556 struct swrast_device_driver
*swdd
= _swrast_GetDeviceDriverReference(ctx
);
557 swdd
->SpanRenderStart
= intelSpanRenderStart
;
558 swdd
->SpanRenderFinish
= intelSpanRenderFinish
;
563 * Plug in appropriate span read/write functions for the given renderbuffer.
564 * These are used for the software fallbacks.
567 intel_set_span_functions(struct intel_context
*intel
,
568 struct gl_renderbuffer
*rb
)
570 struct intel_renderbuffer
*irb
= (struct intel_renderbuffer
*) rb
;
573 /* If in GEM mode, we need to do the tile address swizzling ourselves,
574 * instead of the fence registers handling it.
577 tiling
= irb
->region
->tiling
;
579 tiling
= I915_TILING_NONE
;
581 switch (irb
->texformat
->MesaFormat
) {
582 case MESA_FORMAT_RGB565
:
584 case I915_TILING_NONE
:
586 intelInitPointers_RGB565(rb
);
589 intel_XTile_InitPointers_RGB565(rb
);
592 intel_YTile_InitPointers_RGB565(rb
);
596 case MESA_FORMAT_ARGB4444
:
598 case I915_TILING_NONE
:
600 intelInitPointers_ARGB4444(rb
);
603 intel_XTile_InitPointers_ARGB4444(rb
);
606 intel_YTile_InitPointers_ARGB4444(rb
);
610 case MESA_FORMAT_ARGB1555
:
612 case I915_TILING_NONE
:
614 intelInitPointers_ARGB1555(rb
);
617 intel_XTile_InitPointers_ARGB1555(rb
);
620 intel_YTile_InitPointers_ARGB1555(rb
);
624 case MESA_FORMAT_ARGB8888
:
625 if (rb
->AlphaBits
== 0) { /* XXX: Need xRGB8888 Mesa format */
628 case I915_TILING_NONE
:
630 intelInitPointers_xRGB8888(rb
);
633 intel_XTile_InitPointers_xRGB8888(rb
);
636 intel_YTile_InitPointers_xRGB8888(rb
);
642 case I915_TILING_NONE
:
644 intelInitPointers_ARGB8888(rb
);
647 intel_XTile_InitPointers_ARGB8888(rb
);
650 intel_YTile_InitPointers_ARGB8888(rb
);
655 case MESA_FORMAT_Z16
:
657 case I915_TILING_NONE
:
659 intelInitDepthPointers_z16(rb
);
662 intel_XTile_InitDepthPointers_z16(rb
);
665 intel_YTile_InitDepthPointers_z16(rb
);
669 case MESA_FORMAT_S8_Z24
:
670 /* There are a few different ways SW asks us to access the S8Z24 data:
671 * Z24 depth-only depth reads
673 * S8Z24 stencil reads.
675 if (rb
->_ActualFormat
== GL_DEPTH_COMPONENT24
) {
677 case I915_TILING_NONE
:
679 intelInitDepthPointers_z24(rb
);
682 intel_XTile_InitDepthPointers_z24(rb
);
685 intel_YTile_InitDepthPointers_z24(rb
);
688 } else if (rb
->_ActualFormat
== GL_DEPTH24_STENCIL8_EXT
) {
690 case I915_TILING_NONE
:
692 intelInitDepthPointers_z24_s8(rb
);
695 intel_XTile_InitDepthPointers_z24_s8(rb
);
698 intel_YTile_InitDepthPointers_z24_s8(rb
);
701 } else if (rb
->_ActualFormat
== GL_STENCIL_INDEX8_EXT
) {
703 case I915_TILING_NONE
:
705 intelInitStencilPointers_z24_s8(rb
);
708 intel_XTile_InitStencilPointers_z24_s8(rb
);
711 intel_YTile_InitStencilPointers_z24_s8(rb
);
718 "Unexpected MesaFormat in intelSetSpanFunctions");