src/mesa/drivers/dri/intel/intel_span.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "main/glheader.h"
  29 #include "main/macros.h"
  30 #include "main/mtypes.h"
  31 #include "main/colormac.h"
  32
  33 #include "intel_buffers.h"
  34 #include "intel_fbo.h"
  35 #include "intel_screen.h"
  36 #include "intel_span.h"
  37 #include "intel_regions.h"
  38 #include "intel_tex.h"
  39
  40 #include "swrast/swrast.h"
  41
  42 static void
  43 intel_set_span_functions(struct intel_context *intel,
  44                          struct gl_renderbuffer *rb);
  45
  46 #define SPAN_CACHE_SIZE         4096
  47
  48 static void
  49 get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
  50 {
  51    if (irb->span_cache == NULL) {
  52       irb->span_cache = _mesa_malloc(SPAN_CACHE_SIZE);
  53       irb->span_cache_offset = -1;
  54    }
  55
  56    if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
  57       irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
  58       dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
  59                          SPAN_CACHE_SIZE, irb->span_cache);
  60    }
  61 }
  62
  63 static void
  64 clear_span_cache(struct intel_renderbuffer *irb)
  65 {
  66    irb->span_cache_offset = -1;
  67 }
  68
  69 static uint32_t
  70 pread_32(struct intel_renderbuffer *irb, uint32_t offset)
  71 {
  72    get_span_cache(irb, offset);
  73
  74    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  75 }
  76
  77 static uint32_t
  78 pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
  79 {
  80    get_span_cache(irb, offset);
  81
  82    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
  83       0xff000000;
  84 }
  85
  86 static uint16_t
  87 pread_16(struct intel_renderbuffer *irb, uint32_t offset)
  88 {
  89    get_span_cache(irb, offset);
  90
  91    return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  92 }
  93
  94 static uint8_t
  95 pread_8(struct intel_renderbuffer *irb, uint32_t offset)
  96 {
  97    get_span_cache(irb, offset);
  98
  99    return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
 100 }
 101
 102 static void
 103 pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 104 {
 105    clear_span_cache(irb);
 106
 107    dri_bo_subdata(irb->region->buffer, offset, 4, &val);
 108 }
 109
 110 static void
 111 pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 112 {
 113    clear_span_cache(irb);
 114
 115    dri_bo_subdata(irb->region->buffer, offset, 3, &val);
 116 }
 117
 118 static void
 119 pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
 120 {
 121    clear_span_cache(irb);
 122
 123    dri_bo_subdata(irb->region->buffer, offset, 2, &val);
 124 }
 125
 126 static void
 127 pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
 128 {
 129    clear_span_cache(irb);
 130
 131    dri_bo_subdata(irb->region->buffer, offset, 1, &val);
 132 }
 133
 134 static uint32_t
 135 z24s8_to_s8z24(uint32_t val)
 136 {
 137    return (val << 24) | (val >> 8);
 138 }
 139
 140 static uint32_t
 141 s8z24_to_z24s8(uint32_t val)
 142 {
 143    return (val >> 24) | (val << 8);
 144 }
 145
 146 static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
 147                                 int x, int y)
 148 {
 149         return (y * irb->region->pitch + x) * irb->region->cpp;
 150 }
 151
 152 /*
 153  * Deal with tiled surfaces
 154  */
 155
 156 static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
 157                                int x, int y)
 158 {
 159         int     tile_stride;
 160         int     xbyte;
 161         int     x_tile_off, y_tile_off;
 162         int     x_tile_number, y_tile_number;
 163         int     tile_off, tile_base;
 164
 165         tile_stride = (irb->region->pitch * irb->region->cpp) << 3;
 166
 167         xbyte = x * irb->region->cpp;
 168
 169         x_tile_off = xbyte & 0x1ff;
 170         y_tile_off = y & 7;
 171
 172         x_tile_number = xbyte >> 9;
 173         y_tile_number = y >> 3;
 174
 175         tile_off = (y_tile_off << 9) + x_tile_off;
 176
 177         switch (irb->region->bit_6_swizzle) {
 178         case I915_BIT_6_SWIZZLE_NONE:
 179            break;
 180         case I915_BIT_6_SWIZZLE_9:
 181            tile_off ^= ((tile_off >> 3) & 64);
 182            break;
 183         case I915_BIT_6_SWIZZLE_9_10:
 184            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 185            break;
 186         case I915_BIT_6_SWIZZLE_9_11:
 187            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 188            break;
 189         case I915_BIT_6_SWIZZLE_9_10_11:
 190            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 191               ((tile_off >> 5) & 64);
 192            break;
 193         default:
 194            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 195                    irb->region->bit_6_swizzle);
 196            exit(1);
 197         }
 198
 199         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 200
 201 #if 0
 202         printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
 203                x, y, tile_off, tile_base,
 204                tile_off + tile_base,
 205                irb->region->pitch, tile_stride);
 206 #endif
 207
 208         return tile_base + tile_off;
 209 }
 210
 211 static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 212                                int x, int y)
 213 {
 214         int     tile_stride;
 215         int     xbyte;
 216         int     x_tile_off, y_tile_off;
 217         int     x_tile_number, y_tile_number;
 218         int     tile_off, tile_base;
 219
 220         tile_stride = (irb->region->pitch * irb->region->cpp) << 5;
 221
 222         xbyte = x * irb->region->cpp;
 223
 224         x_tile_off = xbyte & 0x7f;
 225         y_tile_off = y & 0x1f;
 226
 227         x_tile_number = xbyte >> 7;
 228         y_tile_number = y >> 5;
 229
 230         tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
 231            (x_tile_off & 0xf);
 232
 233         switch (irb->region->bit_6_swizzle) {
 234         case I915_BIT_6_SWIZZLE_NONE:
 235            break;
 236         case I915_BIT_6_SWIZZLE_9:
 237            tile_off ^= ((tile_off >> 3) & 64);
 238            break;
 239         case I915_BIT_6_SWIZZLE_9_10:
 240            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 241            break;
 242         case I915_BIT_6_SWIZZLE_9_11:
 243            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 244            break;
 245         case I915_BIT_6_SWIZZLE_9_10_11:
 246            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 247               ((tile_off >> 5) & 64);
 248            break;
 249         default:
 250            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 251                    irb->region->bit_6_swizzle);
 252            exit(1);
 253         }
 254
 255         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 256
 257         return tile_base + tile_off;
 258 }
 259
 260 /*
 261   break intelWriteRGBASpan_ARGB8888
 262 */
 263
 264 #undef DBG
 265 #define DBG 0
 266
 267 #define LOCAL_VARS                                                      \
 268    struct intel_context *intel = intel_context(ctx);                    \
 269    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 270    const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1;                 \
 271    const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
 272    unsigned int num_cliprects;                                          \
 273    struct drm_clip_rect *cliprects;                                     \
 274    int x_off, y_off;                                                    \
 275    GLuint p;                                                            \
 276    (void) p;                                                            \
 277    intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
 278
 279 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
 280  * the cliprect info from the context, not the driDrawable.
 281  * Move this into spantmp2.h someday.
 282  */
 283 #define HW_CLIPLOOP()                                                   \
 284    do {                                                                 \
 285       int _nc = num_cliprects;                                          \
 286       while ( _nc-- ) {                                                 \
 287          int minx = cliprects[_nc].x1 - x_off;                          \
 288          int miny = cliprects[_nc].y1 - y_off;                          \
 289          int maxx = cliprects[_nc].x2 - x_off;                          \
 290          int maxy = cliprects[_nc].y2 - y_off;
 291
 292 #if 0
 293       }}
 294 #endif
 295
 296 #define Y_FLIP(_y) ((_y) * yScale + yBias)
 297
 298 /* XXX with GEM, these need to tell the kernel */
 299 #define HW_LOCK()
 300
 301 #define HW_UNLOCK()
 302
 303 /* Convenience macros to avoid typing the swizzle argument over and over */
 304 #define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 305 #define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 306 #define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 307
 308 /* r5g6b5 color span and pixel functions */
 309 #define INTEL_PIXEL_FMT GL_RGB
 310 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
 311 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 312 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 313 #define INTEL_TAG(x) x##_RGB565
 314 #include "intel_spantmp.h"
 315
 316 /* a4r4g4b4 color span and pixel functions */
 317 #define INTEL_PIXEL_FMT GL_BGRA
 318 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
 319 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 320 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 321 #define INTEL_TAG(x) x##_ARGB4444
 322 #include "intel_spantmp.h"
 323
 324 /* a1r5g5b5 color span and pixel functions */
 325 #define INTEL_PIXEL_FMT GL_BGRA
 326 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
 327 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 328 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 329 #define INTEL_TAG(x) x##_ARGB1555
 330 #include "intel_spantmp.h"
 331
 332 /* a8r8g8b8 color span and pixel functions */
 333 #define INTEL_PIXEL_FMT GL_BGRA
 334 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 335 #define INTEL_READ_VALUE(offset) pread_32(irb, offset)
 336 #define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v)
 337 #define INTEL_TAG(x) x##_ARGB8888
 338 #include "intel_spantmp.h"
 339
 340 /* x8r8g8b8 color span and pixel functions */
 341 #define INTEL_PIXEL_FMT GL_BGRA
 342 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 343 #define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
 344 #define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
 345 #define INTEL_TAG(x) x##_xRGB8888
 346 #include "intel_spantmp.h"
 347
 348 #define LOCAL_DEPTH_VARS                                                \
 349    struct intel_context *intel = intel_context(ctx);                    \
 350    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 351    const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1;                 \
 352    const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
 353    unsigned int num_cliprects;                                          \
 354    struct drm_clip_rect *cliprects;                                     \
 355    int x_off, y_off;                                                    \
 356    intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
 357
 358
 359 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
 360
 361 /* z16 depthbuffer functions. */
 362 #define INTEL_VALUE_TYPE GLushort
 363 #define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d)
 364 #define INTEL_READ_DEPTH(offset) pread_16(irb, offset)
 365 #define INTEL_TAG(name) name##_z16
 366 #include "intel_depthtmp.h"
 367
 368 /* z24 depthbuffer functions. */
 369 #define INTEL_VALUE_TYPE GLuint
 370 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
 371 #define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
 372 #define INTEL_TAG(name) name##_z24
 373 #include "intel_depthtmp.h"
 374
 375 /* z24s8 depthbuffer functions. */
 376 #define INTEL_VALUE_TYPE GLuint
 377 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, z24s8_to_s8z24(d))
 378 #define INTEL_READ_DEPTH(offset) s8z24_to_z24s8(pread_32(irb, offset))
 379 #define INTEL_TAG(name) name##_z24_s8
 380 #include "intel_depthtmp.h"
 381
 382
 383 /**
 384  ** 8-bit stencil function (XXX FBO: This is obsolete)
 385  **/
 386 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
 387 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
 388 #define TAG(x) intel##x##_z24_s8
 389 #include "stenciltmp.h"
 390
 391 /**
 392  ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
 393  **/
 394 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, X_TILE(_x, _y) + 3, d)
 395 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, X_TILE(_x, _y) + 3);
 396 #define TAG(x) intel_XTile_##x##_z24_s8
 397 #include "stenciltmp.h"
 398
 399 /**
 400  ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
 401  **/
 402 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, Y_TILE(_x, _y) + 3, d)
 403 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, Y_TILE(_x, _y) + 3)
 404 #define TAG(x) intel_YTile_##x##_z24_s8
 405 #include "stenciltmp.h"
 406
 407 void
 408 intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
 409 {
 410    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 411
 412    if (irb == NULL || irb->region == NULL)
 413       return;
 414
 415    intel_set_span_functions(intel, rb);
 416 }
 417
 418 void
 419 intel_renderbuffer_unmap(struct intel_context *intel,
 420                          struct gl_renderbuffer *rb)
 421 {
 422    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 423
 424    if (irb == NULL || irb->region == NULL)
 425       return;
 426
 427    clear_span_cache(irb);
 428
 429    rb->GetRow = NULL;
 430    rb->PutRow = NULL;
 431 }
 432
 433 /**
 434  * Map or unmap all the renderbuffers which we may need during
 435  * software rendering.
 436  * XXX in the future, we could probably convey extra information to
 437  * reduce the number of mappings needed.  I.e. if doing a glReadPixels
 438  * from the depth buffer, we really only need one mapping.
 439  *
 440  * XXX Rewrite this function someday.
 441  * We can probably just loop over all the renderbuffer attachments,
 442  * map/unmap all of them, and not worry about the _ColorDrawBuffers
 443  * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
 444  */
 445 static void
 446 intel_map_unmap_framebuffer(struct intel_context *intel,
 447                             struct gl_framebuffer *fb,
 448                             GLboolean map)
 449 {
 450    GLuint i;
 451
 452    /* color draw buffers */
 453    for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
 454       if (map)
 455          intel_renderbuffer_map(intel, fb->_ColorDrawBuffers[i]);
 456       else
 457          intel_renderbuffer_unmap(intel, fb->_ColorDrawBuffers[i]);
 458    }
 459
 460    /* color read buffer */
 461    if (map)
 462       intel_renderbuffer_map(intel, fb->_ColorReadBuffer);
 463    else
 464       intel_renderbuffer_unmap(intel, fb->_ColorReadBuffer);
 465
 466    /* check for render to textures */
 467    for (i = 0; i < BUFFER_COUNT; i++) {
 468       struct gl_renderbuffer_attachment *att =
 469          fb->Attachment + i;
 470       struct gl_texture_object *tex = att->Texture;
 471       if (tex) {
 472          /* render to texture */
 473          ASSERT(att->Renderbuffer);
 474          if (map)
 475             intel_tex_map_images(intel, intel_texture_object(tex));
 476          else
 477             intel_tex_unmap_images(intel, intel_texture_object(tex));
 478       }
 479    }
 480
 481    /* depth buffer (Note wrapper!) */
 482    if (fb->_DepthBuffer) {
 483       if (map)
 484          intel_renderbuffer_map(intel, fb->_DepthBuffer->Wrapped);
 485       else
 486          intel_renderbuffer_unmap(intel, fb->_DepthBuffer->Wrapped);
 487    }
 488
 489    /* stencil buffer (Note wrapper!) */
 490    if (fb->_StencilBuffer) {
 491       if (map)
 492          intel_renderbuffer_map(intel, fb->_StencilBuffer->Wrapped);
 493       else
 494          intel_renderbuffer_unmap(intel, fb->_StencilBuffer->Wrapped);
 495    }
 496 }
 497
 498 /**
 499  * Prepare for software rendering.  Map current read/draw framebuffers'
 500  * renderbuffes and all currently bound texture objects.
 501  *
 502  * Old note: Moved locking out to get reasonable span performance.
 503  */
 504 void
 505 intelSpanRenderStart(GLcontext * ctx)
 506 {
 507    struct intel_context *intel = intel_context(ctx);
 508    GLuint i;
 509
 510    intelFlush(&intel->ctx);
 511    LOCK_HARDWARE(intel);
 512
 513    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 514       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 515          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 516          intel_tex_map_images(intel, intel_texture_object(texObj));
 517       }
 518    }
 519
 520    intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_TRUE);
 521    if (ctx->ReadBuffer != ctx->DrawBuffer)
 522       intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_TRUE);
 523 }
 524
 525 /**
 526  * Called when done software rendering.  Unmap the buffers we mapped in
 527  * the above function.
 528  */
 529 void
 530 intelSpanRenderFinish(GLcontext * ctx)
 531 {
 532    struct intel_context *intel = intel_context(ctx);
 533    GLuint i;
 534
 535    _swrast_flush(ctx);
 536
 537    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 538       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 539          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 540          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 541       }
 542    }
 543
 544    intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_FALSE);
 545    if (ctx->ReadBuffer != ctx->DrawBuffer)
 546       intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_FALSE);
 547
 548    UNLOCK_HARDWARE(intel);
 549 }
 550
 551
 552 void
 553 intelInitSpanFuncs(GLcontext * ctx)
 554 {
 555    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 556    swdd->SpanRenderStart = intelSpanRenderStart;
 557    swdd->SpanRenderFinish = intelSpanRenderFinish;
 558 }
 559
 560
 561 /**
 562  * Plug in appropriate span read/write functions for the given renderbuffer.
 563  * These are used for the software fallbacks.
 564  */
 565 static void
 566 intel_set_span_functions(struct intel_context *intel,
 567                          struct gl_renderbuffer *rb)
 568 {
 569    struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
 570    uint32_t tiling;
 571
 572    /* If in GEM mode, we need to do the tile address swizzling ourselves,
 573     * instead of the fence registers handling it.
 574     */
 575    if (intel->ttm)
 576       tiling = irb->region->tiling;
 577    else
 578       tiling = I915_TILING_NONE;
 579
 580    switch (irb->texformat) {
 581    case MESA_FORMAT_RGB565:
 582       switch (tiling) {
 583       case I915_TILING_NONE:
 584       default:
 585          intelInitPointers_RGB565(rb);
 586          break;
 587       case I915_TILING_X:
 588          intel_XTile_InitPointers_RGB565(rb);
 589          break;
 590       case I915_TILING_Y:
 591          intel_YTile_InitPointers_RGB565(rb);
 592          break;
 593       }
 594       break;
 595    case MESA_FORMAT_ARGB4444:
 596       switch (tiling) {
 597       case I915_TILING_NONE:
 598       default:
 599          intelInitPointers_ARGB4444(rb);
 600          break;
 601       case I915_TILING_X:
 602          intel_XTile_InitPointers_ARGB4444(rb);
 603          break;
 604       case I915_TILING_Y:
 605          intel_YTile_InitPointers_ARGB4444(rb);
 606          break;
 607       }
 608       break;
 609    case MESA_FORMAT_ARGB1555:
 610       switch (tiling) {
 611       case I915_TILING_NONE:
 612       default:
 613          intelInitPointers_ARGB1555(rb);
 614          break;
 615       case I915_TILING_X:
 616          intel_XTile_InitPointers_ARGB1555(rb);
 617          break;
 618       case I915_TILING_Y:
 619          intel_YTile_InitPointers_ARGB1555(rb);
 620          break;
 621       }
 622       break;
 623    case MESA_FORMAT_ARGB8888:
 624       if (rb->AlphaBits == 0) { /* XXX: Need xRGB8888 Mesa format */
 625          /* 8888 RGBx */
 626          switch (tiling) {
 627          case I915_TILING_NONE:
 628          default:
 629             intelInitPointers_xRGB8888(rb);
 630             break;
 631          case I915_TILING_X:
 632             intel_XTile_InitPointers_xRGB8888(rb);
 633             break;
 634          case I915_TILING_Y:
 635             intel_YTile_InitPointers_xRGB8888(rb);
 636             break;
 637          }
 638       } else {
 639          /* 8888 RGBA */
 640          switch (tiling) {
 641          case I915_TILING_NONE:
 642          default:
 643             intelInitPointers_ARGB8888(rb);
 644             break;
 645          case I915_TILING_X:
 646             intel_XTile_InitPointers_ARGB8888(rb);
 647             break;
 648          case I915_TILING_Y:
 649             intel_YTile_InitPointers_ARGB8888(rb);
 650             break;
 651          }
 652       }
 653       break;
 654    case MESA_FORMAT_Z16:
 655       switch (tiling) {
 656       case I915_TILING_NONE:
 657       default:
 658          intelInitDepthPointers_z16(rb);
 659          break;
 660       case I915_TILING_X:
 661          intel_XTile_InitDepthPointers_z16(rb);
 662          break;
 663       case I915_TILING_Y:
 664          intel_YTile_InitDepthPointers_z16(rb);
 665          break;
 666       }
 667       break;
 668    case MESA_FORMAT_S8_Z24:
 669       /* There are a few different ways SW asks us to access the S8Z24 data:
 670        * Z24 depth-only depth reads
 671        * S8Z24 depth reads
 672        * S8Z24 stencil reads.
 673        */
 674       if (rb->_ActualFormat == GL_DEPTH_COMPONENT24) {
 675          switch (tiling) {
 676          case I915_TILING_NONE:
 677          default:
 678             intelInitDepthPointers_z24(rb);
 679             break;
 680          case I915_TILING_X:
 681             intel_XTile_InitDepthPointers_z24(rb);
 682             break;
 683          case I915_TILING_Y:
 684             intel_YTile_InitDepthPointers_z24(rb);
 685             break;
 686          }
 687       } else if (rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
 688          switch (tiling) {
 689          case I915_TILING_NONE:
 690          default:
 691             intelInitDepthPointers_z24_s8(rb);
 692             break;
 693          case I915_TILING_X:
 694             intel_XTile_InitDepthPointers_z24_s8(rb);
 695             break;
 696          case I915_TILING_Y:
 697             intel_YTile_InitDepthPointers_z24_s8(rb);
 698             break;
 699          }
 700       } else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) {
 701          switch (tiling) {
 702          case I915_TILING_NONE:
 703          default:
 704             intelInitStencilPointers_z24_s8(rb);
 705             break;
 706          case I915_TILING_X:
 707             intel_XTile_InitStencilPointers_z24_s8(rb);
 708             break;
 709          case I915_TILING_Y:
 710             intel_YTile_InitStencilPointers_z24_s8(rb);
 711             break;
 712          }
 713       } else {
 714          _mesa_problem(NULL,
 715                        "Unexpected ActualFormat in intelSetSpanFunctions");
 716       }
 717       break;
 718    default:
 719       _mesa_problem(NULL,
 720                     "Unexpected MesaFormat in intelSetSpanFunctions");
 721       break;
 722    }
 723 }