src/mesa/drivers/dri/intel/intel_span.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "main/glheader.h"
  29 #include "main/macros.h"
  30 #include "main/mtypes.h"
  31 #include "main/colormac.h"
  32 #include "main/texformat.h"
  33
  34 #include "intel_buffers.h"
  35 #include "intel_fbo.h"
  36 #include "intel_screen.h"
  37 #include "intel_span.h"
  38 #include "intel_regions.h"
  39 #include "intel_tex.h"
  40
  41 #include "swrast/swrast.h"
  42
  43 static void
  44 intel_set_span_functions(struct intel_context *intel,
  45                          struct gl_renderbuffer *rb);
  46
  47 #define SPAN_CACHE_SIZE         4096
  48
  49 static void
  50 get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
  51 {
  52    if (irb->span_cache == NULL) {
  53       irb->span_cache = _mesa_malloc(SPAN_CACHE_SIZE);
  54       irb->span_cache_offset = -1;
  55    }
  56
  57    if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
  58       irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
  59       dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
  60                          SPAN_CACHE_SIZE, irb->span_cache);
  61    }
  62 }
  63
  64 static void
  65 clear_span_cache(struct intel_renderbuffer *irb)
  66 {
  67    irb->span_cache_offset = -1;
  68 }
  69
  70 static uint32_t
  71 pread_32(struct intel_renderbuffer *irb, uint32_t offset)
  72 {
  73    get_span_cache(irb, offset);
  74
  75    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  76 }
  77
  78 static uint32_t
  79 pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
  80 {
  81    get_span_cache(irb, offset);
  82
  83    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
  84       0xff000000;
  85 }
  86
  87 static uint16_t
  88 pread_16(struct intel_renderbuffer *irb, uint32_t offset)
  89 {
  90    get_span_cache(irb, offset);
  91
  92    return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  93 }
  94
  95 static uint8_t
  96 pread_8(struct intel_renderbuffer *irb, uint32_t offset)
  97 {
  98    get_span_cache(irb, offset);
  99
 100    return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
 101 }
 102
 103 static void
 104 pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 105 {
 106    clear_span_cache(irb);
 107
 108    dri_bo_subdata(irb->region->buffer, offset, 4, &val);
 109 }
 110
 111 static void
 112 pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 113 {
 114    clear_span_cache(irb);
 115
 116    dri_bo_subdata(irb->region->buffer, offset, 3, &val);
 117 }
 118
 119 static void
 120 pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
 121 {
 122    clear_span_cache(irb);
 123
 124    dri_bo_subdata(irb->region->buffer, offset, 2, &val);
 125 }
 126
 127 static void
 128 pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
 129 {
 130    clear_span_cache(irb);
 131
 132    dri_bo_subdata(irb->region->buffer, offset, 1, &val);
 133 }
 134
 135 static uint32_t
 136 z24s8_to_s8z24(uint32_t val)
 137 {
 138    return (val << 24) | (val >> 8);
 139 }
 140
 141 static uint32_t
 142 s8z24_to_z24s8(uint32_t val)
 143 {
 144    return (val >> 24) | (val << 8);
 145 }
 146
 147 static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
 148                                 int x, int y)
 149 {
 150         return (y * irb->region->pitch + x) * irb->region->cpp;
 151 }
 152
 153 /*
 154  * Deal with tiled surfaces
 155  */
 156
 157 static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
 158                                int x, int y)
 159 {
 160         int     tile_stride;
 161         int     xbyte;
 162         int     x_tile_off, y_tile_off;
 163         int     x_tile_number, y_tile_number;
 164         int     tile_off, tile_base;
 165
 166         tile_stride = (irb->region->pitch * irb->region->cpp) << 3;
 167
 168         xbyte = x * irb->region->cpp;
 169
 170         x_tile_off = xbyte & 0x1ff;
 171         y_tile_off = y & 7;
 172
 173         x_tile_number = xbyte >> 9;
 174         y_tile_number = y >> 3;
 175
 176         tile_off = (y_tile_off << 9) + x_tile_off;
 177
 178         switch (irb->region->bit_6_swizzle) {
 179         case I915_BIT_6_SWIZZLE_NONE:
 180            break;
 181         case I915_BIT_6_SWIZZLE_9:
 182            tile_off ^= ((tile_off >> 3) & 64);
 183            break;
 184         case I915_BIT_6_SWIZZLE_9_10:
 185            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 186            break;
 187         case I915_BIT_6_SWIZZLE_9_11:
 188            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 189            break;
 190         case I915_BIT_6_SWIZZLE_9_10_11:
 191            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 192               ((tile_off >> 5) & 64);
 193            break;
 194         default:
 195            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 196                    irb->region->bit_6_swizzle);
 197            exit(1);
 198         }
 199
 200         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 201
 202 #if 0
 203         printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
 204                x, y, tile_off, tile_base,
 205                tile_off + tile_base,
 206                irb->region->pitch, tile_stride);
 207 #endif
 208
 209         return tile_base + tile_off;
 210 }
 211
 212 static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 213                                int x, int y)
 214 {
 215         int     tile_stride;
 216         int     xbyte;
 217         int     x_tile_off, y_tile_off;
 218         int     x_tile_number, y_tile_number;
 219         int     tile_off, tile_base;
 220
 221         tile_stride = (irb->region->pitch * irb->region->cpp) << 5;
 222
 223         xbyte = x * irb->region->cpp;
 224
 225         x_tile_off = xbyte & 0x7f;
 226         y_tile_off = y & 0x1f;
 227
 228         x_tile_number = xbyte >> 7;
 229         y_tile_number = y >> 5;
 230
 231         tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
 232            (x_tile_off & 0xf);
 233
 234         switch (irb->region->bit_6_swizzle) {
 235         case I915_BIT_6_SWIZZLE_NONE:
 236            break;
 237         case I915_BIT_6_SWIZZLE_9:
 238            tile_off ^= ((tile_off >> 3) & 64);
 239            break;
 240         case I915_BIT_6_SWIZZLE_9_10:
 241            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 242            break;
 243         case I915_BIT_6_SWIZZLE_9_11:
 244            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 245            break;
 246         case I915_BIT_6_SWIZZLE_9_10_11:
 247            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 248               ((tile_off >> 5) & 64);
 249            break;
 250         default:
 251            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 252                    irb->region->bit_6_swizzle);
 253            exit(1);
 254         }
 255
 256         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 257
 258         return tile_base + tile_off;
 259 }
 260
 261 /*
 262   break intelWriteRGBASpan_ARGB8888
 263 */
 264
 265 #undef DBG
 266 #define DBG 0
 267
 268 #define LOCAL_VARS                                                      \
 269    struct intel_context *intel = intel_context(ctx);                    \
 270    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 271    const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1;                 \
 272    const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
 273    unsigned int num_cliprects;                                          \
 274    struct drm_clip_rect *cliprects;                                     \
 275    int x_off, y_off;                                                    \
 276    GLuint p;                                                            \
 277    (void) p;                                                            \
 278    intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
 279
 280 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
 281  * the cliprect info from the context, not the driDrawable.
 282  * Move this into spantmp2.h someday.
 283  */
 284 #define HW_CLIPLOOP()                                                   \
 285    do {                                                                 \
 286       int _nc = num_cliprects;                                          \
 287       while ( _nc-- ) {                                                 \
 288          int minx = cliprects[_nc].x1 - x_off;                          \
 289          int miny = cliprects[_nc].y1 - y_off;                          \
 290          int maxx = cliprects[_nc].x2 - x_off;                          \
 291          int maxy = cliprects[_nc].y2 - y_off;
 292
 293 #if 0
 294       }}
 295 #endif
 296
 297 #define Y_FLIP(_y) ((_y) * yScale + yBias)
 298
 299 /* XXX with GEM, these need to tell the kernel */
 300 #define HW_LOCK()
 301
 302 #define HW_UNLOCK()
 303
 304 /* Convenience macros to avoid typing the swizzle argument over and over */
 305 #define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 306 #define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 307 #define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 308
 309 /* r5g6b5 color span and pixel functions */
 310 #define INTEL_PIXEL_FMT GL_RGB
 311 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
 312 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 313 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 314 #define INTEL_TAG(x) x##_RGB565
 315 #include "intel_spantmp.h"
 316
 317 /* a4r4g4b4 color span and pixel functions */
 318 #define INTEL_PIXEL_FMT GL_BGRA
 319 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
 320 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 321 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 322 #define INTEL_TAG(x) x##_ARGB4444
 323 #include "intel_spantmp.h"
 324
 325 /* a1r5g5b5 color span and pixel functions */
 326 #define INTEL_PIXEL_FMT GL_BGRA
 327 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
 328 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 329 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 330 #define INTEL_TAG(x) x##_ARGB1555
 331 #include "intel_spantmp.h"
 332
 333 /* a8r8g8b8 color span and pixel functions */
 334 #define INTEL_PIXEL_FMT GL_BGRA
 335 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 336 #define INTEL_READ_VALUE(offset) pread_32(irb, offset)
 337 #define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v)
 338 #define INTEL_TAG(x) x##_ARGB8888
 339 #include "intel_spantmp.h"
 340
 341 /* x8r8g8b8 color span and pixel functions */
 342 #define INTEL_PIXEL_FMT GL_BGRA
 343 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 344 #define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
 345 #define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
 346 #define INTEL_TAG(x) x##_xRGB8888
 347 #include "intel_spantmp.h"
 348
 349 #define LOCAL_DEPTH_VARS                                                \
 350    struct intel_context *intel = intel_context(ctx);                    \
 351    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 352    const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1;                 \
 353    const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
 354    unsigned int num_cliprects;                                          \
 355    struct drm_clip_rect *cliprects;                                     \
 356    int x_off, y_off;                                                    \
 357    intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
 358
 359
 360 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
 361
 362 /* z16 depthbuffer functions. */
 363 #define INTEL_VALUE_TYPE GLushort
 364 #define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d)
 365 #define INTEL_READ_DEPTH(offset) pread_16(irb, offset)
 366 #define INTEL_TAG(name) name##_z16
 367 #include "intel_depthtmp.h"
 368
 369 /* z24 depthbuffer functions. */
 370 #define INTEL_VALUE_TYPE GLuint
 371 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
 372 #define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
 373 #define INTEL_TAG(name) name##_z24
 374 #include "intel_depthtmp.h"
 375
 376 /* z24s8 depthbuffer functions. */
 377 #define INTEL_VALUE_TYPE GLuint
 378 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, z24s8_to_s8z24(d))
 379 #define INTEL_READ_DEPTH(offset) s8z24_to_z24s8(pread_32(irb, offset))
 380 #define INTEL_TAG(name) name##_z24_s8
 381 #include "intel_depthtmp.h"
 382
 383
 384 /**
 385  ** 8-bit stencil function (XXX FBO: This is obsolete)
 386  **/
 387 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
 388 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
 389 #define TAG(x) intel##x##_z24_s8
 390 #include "stenciltmp.h"
 391
 392 /**
 393  ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
 394  **/
 395 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, X_TILE(_x, _y) + 3, d)
 396 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, X_TILE(_x, _y) + 3);
 397 #define TAG(x) intel_XTile_##x##_z24_s8
 398 #include "stenciltmp.h"
 399
 400 /**
 401  ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
 402  **/
 403 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, Y_TILE(_x, _y) + 3, d)
 404 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, Y_TILE(_x, _y) + 3)
 405 #define TAG(x) intel_YTile_##x##_z24_s8
 406 #include "stenciltmp.h"
 407
 408 void
 409 intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
 410 {
 411    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 412
 413    if (irb == NULL || irb->region == NULL)
 414       return;
 415
 416    intel_set_span_functions(intel, rb);
 417 }
 418
 419 void
 420 intel_renderbuffer_unmap(struct intel_context *intel,
 421                          struct gl_renderbuffer *rb)
 422 {
 423    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 424
 425    if (irb == NULL || irb->region == NULL)
 426       return;
 427
 428    clear_span_cache(irb);
 429
 430    rb->GetRow = NULL;
 431    rb->PutRow = NULL;
 432 }
 433
 434 /**
 435  * Map or unmap all the renderbuffers which we may need during
 436  * software rendering.
 437  * XXX in the future, we could probably convey extra information to
 438  * reduce the number of mappings needed.  I.e. if doing a glReadPixels
 439  * from the depth buffer, we really only need one mapping.
 440  *
 441  * XXX Rewrite this function someday.
 442  * We can probably just loop over all the renderbuffer attachments,
 443  * map/unmap all of them, and not worry about the _ColorDrawBuffers
 444  * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
 445  */
 446 static void
 447 intel_map_unmap_framebuffer(struct intel_context *intel,
 448                             struct gl_framebuffer *fb,
 449                             GLboolean map)
 450 {
 451    GLuint i;
 452
 453    /* color draw buffers */
 454    for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
 455       if (map)
 456          intel_renderbuffer_map(intel, fb->_ColorDrawBuffers[i]);
 457       else
 458          intel_renderbuffer_unmap(intel, fb->_ColorDrawBuffers[i]);
 459    }
 460
 461    /* color read buffer */
 462    if (map)
 463       intel_renderbuffer_map(intel, fb->_ColorReadBuffer);
 464    else
 465       intel_renderbuffer_unmap(intel, fb->_ColorReadBuffer);
 466
 467    /* check for render to textures */
 468    for (i = 0; i < BUFFER_COUNT; i++) {
 469       struct gl_renderbuffer_attachment *att =
 470          fb->Attachment + i;
 471       struct gl_texture_object *tex = att->Texture;
 472       if (tex) {
 473          /* render to texture */
 474          ASSERT(att->Renderbuffer);
 475          if (map)
 476             intel_tex_map_images(intel, intel_texture_object(tex));
 477          else
 478             intel_tex_unmap_images(intel, intel_texture_object(tex));
 479       }
 480    }
 481
 482    /* depth buffer (Note wrapper!) */
 483    if (fb->_DepthBuffer) {
 484       if (map)
 485          intel_renderbuffer_map(intel, fb->_DepthBuffer->Wrapped);
 486       else
 487          intel_renderbuffer_unmap(intel, fb->_DepthBuffer->Wrapped);
 488    }
 489
 490    /* stencil buffer (Note wrapper!) */
 491    if (fb->_StencilBuffer) {
 492       if (map)
 493          intel_renderbuffer_map(intel, fb->_StencilBuffer->Wrapped);
 494       else
 495          intel_renderbuffer_unmap(intel, fb->_StencilBuffer->Wrapped);
 496    }
 497 }
 498
 499 /**
 500  * Prepare for software rendering.  Map current read/draw framebuffers'
 501  * renderbuffes and all currently bound texture objects.
 502  *
 503  * Old note: Moved locking out to get reasonable span performance.
 504  */
 505 void
 506 intelSpanRenderStart(GLcontext * ctx)
 507 {
 508    struct intel_context *intel = intel_context(ctx);
 509    GLuint i;
 510
 511    intelFlush(&intel->ctx);
 512    LOCK_HARDWARE(intel);
 513
 514    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 515       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 516          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 517          intel_tex_map_images(intel, intel_texture_object(texObj));
 518       }
 519    }
 520
 521    intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_TRUE);
 522    if (ctx->ReadBuffer != ctx->DrawBuffer)
 523       intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_TRUE);
 524 }
 525
 526 /**
 527  * Called when done software rendering.  Unmap the buffers we mapped in
 528  * the above function.
 529  */
 530 void
 531 intelSpanRenderFinish(GLcontext * ctx)
 532 {
 533    struct intel_context *intel = intel_context(ctx);
 534    GLuint i;
 535
 536    _swrast_flush(ctx);
 537
 538    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 539       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 540          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 541          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 542       }
 543    }
 544
 545    intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_FALSE);
 546    if (ctx->ReadBuffer != ctx->DrawBuffer)
 547       intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_FALSE);
 548
 549    UNLOCK_HARDWARE(intel);
 550 }
 551
 552
 553 void
 554 intelInitSpanFuncs(GLcontext * ctx)
 555 {
 556    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 557    swdd->SpanRenderStart = intelSpanRenderStart;
 558    swdd->SpanRenderFinish = intelSpanRenderFinish;
 559 }
 560
 561 void
 562 intel_map_vertex_shader_textures(GLcontext *ctx)
 563 {
 564    struct intel_context *intel = intel_context(ctx);
 565    int i;
 566
 567    if (ctx->VertexProgram._Current == NULL)
 568       return;
 569
 570    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 571       if (ctx->Texture.Unit[i]._ReallyEnabled &&
 572           ctx->VertexProgram._Current->Base.TexturesUsed[i] != 0) {
 573          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 574
 575          intel_tex_map_images(intel, intel_texture_object(texObj));
 576       }
 577    }
 578 }
 579
 580 void
 581 intel_unmap_vertex_shader_textures(GLcontext *ctx)
 582 {
 583    struct intel_context *intel = intel_context(ctx);
 584    int i;
 585
 586    if (ctx->VertexProgram._Current == NULL)
 587       return;
 588
 589    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 590       if (ctx->Texture.Unit[i]._ReallyEnabled &&
 591           ctx->VertexProgram._Current->Base.TexturesUsed[i] != 0) {
 592          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 593
 594          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 595       }
 596    }
 597 }
 598
 599 /**
 600  * Plug in appropriate span read/write functions for the given renderbuffer.
 601  * These are used for the software fallbacks.
 602  */
 603 static void
 604 intel_set_span_functions(struct intel_context *intel,
 605                          struct gl_renderbuffer *rb)
 606 {
 607    struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
 608    uint32_t tiling;
 609
 610    /* If in GEM mode, we need to do the tile address swizzling ourselves,
 611     * instead of the fence registers handling it.
 612     */
 613    if (intel->ttm)
 614       tiling = irb->region->tiling;
 615    else
 616       tiling = I915_TILING_NONE;
 617
 618    switch (irb->texformat->MesaFormat) {
 619    case MESA_FORMAT_RGB565:
 620       switch (tiling) {
 621       case I915_TILING_NONE:
 622       default:
 623          intelInitPointers_RGB565(rb);
 624          break;
 625       case I915_TILING_X:
 626          intel_XTile_InitPointers_RGB565(rb);
 627          break;
 628       case I915_TILING_Y:
 629          intel_YTile_InitPointers_RGB565(rb);
 630          break;
 631       }
 632       break;
 633    case MESA_FORMAT_ARGB4444:
 634       switch (tiling) {
 635       case I915_TILING_NONE:
 636       default:
 637          intelInitPointers_ARGB4444(rb);
 638          break;
 639       case I915_TILING_X:
 640          intel_XTile_InitPointers_ARGB4444(rb);
 641          break;
 642       case I915_TILING_Y:
 643          intel_YTile_InitPointers_ARGB4444(rb);
 644          break;
 645       }
 646       break;
 647    case MESA_FORMAT_ARGB1555:
 648       switch (tiling) {
 649       case I915_TILING_NONE:
 650       default:
 651          intelInitPointers_ARGB1555(rb);
 652          break;
 653       case I915_TILING_X:
 654          intel_XTile_InitPointers_ARGB1555(rb);
 655          break;
 656       case I915_TILING_Y:
 657          intel_YTile_InitPointers_ARGB1555(rb);
 658          break;
 659       }
 660       break;
 661    case MESA_FORMAT_ARGB8888:
 662       if (rb->AlphaBits == 0) { /* XXX: Need xRGB8888 Mesa format */
 663          /* 8888 RGBx */
 664          switch (tiling) {
 665          case I915_TILING_NONE:
 666          default:
 667             intelInitPointers_xRGB8888(rb);
 668             break;
 669          case I915_TILING_X:
 670             intel_XTile_InitPointers_xRGB8888(rb);
 671             break;
 672          case I915_TILING_Y:
 673             intel_YTile_InitPointers_xRGB8888(rb);
 674             break;
 675          }
 676       } else {
 677          /* 8888 RGBA */
 678          switch (tiling) {
 679          case I915_TILING_NONE:
 680          default:
 681             intelInitPointers_ARGB8888(rb);
 682             break;
 683          case I915_TILING_X:
 684             intel_XTile_InitPointers_ARGB8888(rb);
 685             break;
 686          case I915_TILING_Y:
 687             intel_YTile_InitPointers_ARGB8888(rb);
 688             break;
 689          }
 690       }
 691       break;
 692    case MESA_FORMAT_Z16:
 693       switch (tiling) {
 694       case I915_TILING_NONE:
 695       default:
 696          intelInitDepthPointers_z16(rb);
 697          break;
 698       case I915_TILING_X:
 699          intel_XTile_InitDepthPointers_z16(rb);
 700          break;
 701       case I915_TILING_Y:
 702          intel_YTile_InitDepthPointers_z16(rb);
 703          break;
 704       }
 705       break;
 706    case MESA_FORMAT_S8_Z24:
 707       /* There are a few different ways SW asks us to access the S8Z24 data:
 708        * Z24 depth-only depth reads
 709        * S8Z24 depth reads
 710        * S8Z24 stencil reads.
 711        */
 712       if (rb->_ActualFormat == GL_DEPTH_COMPONENT24) {
 713          switch (tiling) {
 714          case I915_TILING_NONE:
 715          default:
 716             intelInitDepthPointers_z24(rb);
 717             break;
 718          case I915_TILING_X:
 719             intel_XTile_InitDepthPointers_z24(rb);
 720             break;
 721          case I915_TILING_Y:
 722             intel_YTile_InitDepthPointers_z24(rb);
 723             break;
 724          }
 725       } else if (rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
 726          switch (tiling) {
 727          case I915_TILING_NONE:
 728          default:
 729             intelInitDepthPointers_z24_s8(rb);
 730             break;
 731          case I915_TILING_X:
 732             intel_XTile_InitDepthPointers_z24_s8(rb);
 733             break;
 734          case I915_TILING_Y:
 735             intel_YTile_InitDepthPointers_z24_s8(rb);
 736             break;
 737          }
 738       } else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) {
 739          switch (tiling) {
 740          case I915_TILING_NONE:
 741          default:
 742             intelInitStencilPointers_z24_s8(rb);
 743             break;
 744          case I915_TILING_X:
 745             intel_XTile_InitStencilPointers_z24_s8(rb);
 746             break;
 747          case I915_TILING_Y:
 748             intel_YTile_InitStencilPointers_z24_s8(rb);
 749             break;
 750          }
 751       } else {
 752          _mesa_problem(NULL,
 753                        "Unexpected ActualFormat in intelSetSpanFunctions");
 754       }
 755       break;
 756    default:
 757       _mesa_problem(NULL,
 758                     "Unexpected MesaFormat in intelSetSpanFunctions");
 759       break;
 760    }
 761 }