src/mesa/drivers/dri/intel/intel_span.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "main/glheader.h"
  29 #include "main/macros.h"
  30 #include "main/mtypes.h"
  31 #include "main/colormac.h"
  32 #include "main/texformat.h"
  33
  34 #include "intel_buffers.h"
  35 #include "intel_fbo.h"
  36 #include "intel_screen.h"
  37 #include "intel_span.h"
  38 #include "intel_regions.h"
  39 #include "intel_tex.h"
  40
  41 #include "swrast/swrast.h"
  42
  43 static void
  44 intel_set_span_functions(struct intel_context *intel,
  45                          struct gl_renderbuffer *rb);
  46
  47 #define SPAN_CACHE_SIZE         4096
  48
  49 static void
  50 get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
  51 {
  52    if (irb->span_cache == NULL) {
  53       irb->span_cache = _mesa_malloc(SPAN_CACHE_SIZE);
  54       irb->span_cache_offset = -1;
  55    }
  56
  57    if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
  58       irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
  59       dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
  60                          SPAN_CACHE_SIZE, irb->span_cache);
  61    }
  62 }
  63
  64 static void
  65 clear_span_cache(struct intel_renderbuffer *irb)
  66 {
  67    irb->span_cache_offset = -1;
  68 }
  69
  70 static uint32_t
  71 pread_32(struct intel_renderbuffer *irb, uint32_t offset)
  72 {
  73    get_span_cache(irb, offset);
  74
  75    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  76 }
  77
  78 static uint32_t
  79 pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
  80 {
  81    get_span_cache(irb, offset);
  82
  83    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
  84       0xff000000;
  85 }
  86
  87 static uint16_t
  88 pread_16(struct intel_renderbuffer *irb, uint32_t offset)
  89 {
  90    get_span_cache(irb, offset);
  91
  92    return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  93 }
  94
  95 static uint8_t
  96 pread_8(struct intel_renderbuffer *irb, uint32_t offset)
  97 {
  98    get_span_cache(irb, offset);
  99
 100    return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
 101 }
 102
 103 static void
 104 pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 105 {
 106    clear_span_cache(irb);
 107
 108    dri_bo_subdata(irb->region->buffer, offset, 4, &val);
 109 }
 110
 111 static void
 112 pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 113 {
 114    clear_span_cache(irb);
 115
 116    dri_bo_subdata(irb->region->buffer, offset, 3, &val);
 117 }
 118
 119 static void
 120 pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
 121 {
 122    clear_span_cache(irb);
 123
 124    dri_bo_subdata(irb->region->buffer, offset, 2, &val);
 125 }
 126
 127 static void
 128 pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
 129 {
 130    clear_span_cache(irb);
 131
 132    dri_bo_subdata(irb->region->buffer, offset, 1, &val);
 133 }
 134
 135 static uint32_t
 136 z24s8_to_s8z24(uint32_t val)
 137 {
 138    return (val << 24) | (val >> 8);
 139 }
 140
 141 static uint32_t
 142 s8z24_to_z24s8(uint32_t val)
 143 {
 144    return (val >> 24) | (val << 8);
 145 }
 146
 147 static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
 148                                 int x, int y)
 149 {
 150         return (y * irb->region->pitch + x) * irb->region->cpp;
 151 }
 152
 153 /*
 154  * Deal with tiled surfaces
 155  */
 156
 157 static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
 158                                int x, int y)
 159 {
 160         int     tile_stride;
 161         int     xbyte;
 162         int     x_tile_off, y_tile_off;
 163         int     x_tile_number, y_tile_number;
 164         int     tile_off, tile_base;
 165
 166         x += irb->region->draw_x;
 167         y += irb->region->draw_y;
 168
 169         tile_stride = (irb->region->pitch * irb->region->cpp) << 3;
 170
 171         xbyte = x * irb->region->cpp;
 172
 173         x_tile_off = xbyte & 0x1ff;
 174         y_tile_off = y & 7;
 175
 176         x_tile_number = xbyte >> 9;
 177         y_tile_number = y >> 3;
 178
 179         tile_off = (y_tile_off << 9) + x_tile_off;
 180
 181         switch (irb->region->bit_6_swizzle) {
 182         case I915_BIT_6_SWIZZLE_NONE:
 183            break;
 184         case I915_BIT_6_SWIZZLE_9:
 185            tile_off ^= ((tile_off >> 3) & 64);
 186            break;
 187         case I915_BIT_6_SWIZZLE_9_10:
 188            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 189            break;
 190         case I915_BIT_6_SWIZZLE_9_11:
 191            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 192            break;
 193         case I915_BIT_6_SWIZZLE_9_10_11:
 194            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 195               ((tile_off >> 5) & 64);
 196            break;
 197         default:
 198            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 199                    irb->region->bit_6_swizzle);
 200            exit(1);
 201         }
 202
 203         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 204
 205 #if 0
 206         printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
 207                x, y, tile_off, tile_base,
 208                tile_off + tile_base,
 209                irb->region->pitch, tile_stride);
 210 #endif
 211
 212         return tile_base + tile_off;
 213 }
 214
 215 static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 216                                int x, int y)
 217 {
 218         int     tile_stride;
 219         int     xbyte;
 220         int     x_tile_off, y_tile_off;
 221         int     x_tile_number, y_tile_number;
 222         int     tile_off, tile_base;
 223
 224         x += irb->region->draw_x;
 225         y += irb->region->draw_y;
 226
 227         tile_stride = (irb->region->pitch * irb->region->cpp) << 5;
 228
 229         xbyte = x * irb->region->cpp;
 230
 231         x_tile_off = xbyte & 0x7f;
 232         y_tile_off = y & 0x1f;
 233
 234         x_tile_number = xbyte >> 7;
 235         y_tile_number = y >> 5;
 236
 237         tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
 238            (x_tile_off & 0xf);
 239
 240         switch (irb->region->bit_6_swizzle) {
 241         case I915_BIT_6_SWIZZLE_NONE:
 242            break;
 243         case I915_BIT_6_SWIZZLE_9:
 244            tile_off ^= ((tile_off >> 3) & 64);
 245            break;
 246         case I915_BIT_6_SWIZZLE_9_10:
 247            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 248            break;
 249         case I915_BIT_6_SWIZZLE_9_11:
 250            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 251            break;
 252         case I915_BIT_6_SWIZZLE_9_10_11:
 253            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 254               ((tile_off >> 5) & 64);
 255            break;
 256         default:
 257            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 258                    irb->region->bit_6_swizzle);
 259            exit(1);
 260         }
 261
 262         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 263
 264         return tile_base + tile_off;
 265 }
 266
 267 /*
 268   break intelWriteRGBASpan_ARGB8888
 269 */
 270
 271 #undef DBG
 272 #define DBG 0
 273
 274 #define LOCAL_VARS                                                      \
 275    struct intel_context *intel = intel_context(ctx);                    \
 276    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 277    const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1;                 \
 278    const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
 279    unsigned int num_cliprects;                                          \
 280    struct drm_clip_rect *cliprects;                                     \
 281    int x_off, y_off;                                                    \
 282    GLuint p;                                                            \
 283    (void) p;                                                            \
 284    intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
 285
 286 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
 287  * the cliprect info from the context, not the driDrawable.
 288  * Move this into spantmp2.h someday.
 289  */
 290 #define HW_CLIPLOOP()                                                   \
 291    do {                                                                 \
 292       int _nc = num_cliprects;                                          \
 293       while ( _nc-- ) {                                                 \
 294          int minx = cliprects[_nc].x1 - x_off;                          \
 295          int miny = cliprects[_nc].y1 - y_off;                          \
 296          int maxx = cliprects[_nc].x2 - x_off;                          \
 297          int maxy = cliprects[_nc].y2 - y_off;
 298
 299 #if 0
 300       }}
 301 #endif
 302
 303 #define Y_FLIP(_y) ((_y) * yScale + yBias)
 304
 305 /* XXX with GEM, these need to tell the kernel */
 306 #define HW_LOCK()
 307
 308 #define HW_UNLOCK()
 309
 310 /* Convenience macros to avoid typing the swizzle argument over and over */
 311 #define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 312 #define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 313 #define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 314
 315 /* r5g6b5 color span and pixel functions */
 316 #define INTEL_PIXEL_FMT GL_RGB
 317 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
 318 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 319 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 320 #define INTEL_TAG(x) x##_RGB565
 321 #include "intel_spantmp.h"
 322
 323 /* a4r4g4b4 color span and pixel functions */
 324 #define INTEL_PIXEL_FMT GL_BGRA
 325 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
 326 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 327 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 328 #define INTEL_TAG(x) x##_ARGB4444
 329 #include "intel_spantmp.h"
 330
 331 /* a1r5g5b5 color span and pixel functions */
 332 #define INTEL_PIXEL_FMT GL_BGRA
 333 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
 334 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 335 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 336 #define INTEL_TAG(x) x##_ARGB1555
 337 #include "intel_spantmp.h"
 338
 339 /* a8r8g8b8 color span and pixel functions */
 340 #define INTEL_PIXEL_FMT GL_BGRA
 341 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 342 #define INTEL_READ_VALUE(offset) pread_32(irb, offset)
 343 #define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v)
 344 #define INTEL_TAG(x) x##_ARGB8888
 345 #include "intel_spantmp.h"
 346
 347 /* x8r8g8b8 color span and pixel functions */
 348 #define INTEL_PIXEL_FMT GL_BGRA
 349 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 350 #define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
 351 #define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
 352 #define INTEL_TAG(x) x##_xRGB8888
 353 #include "intel_spantmp.h"
 354
 355 #define LOCAL_DEPTH_VARS                                                \
 356    struct intel_context *intel = intel_context(ctx);                    \
 357    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 358    const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1;                 \
 359    const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
 360    unsigned int num_cliprects;                                          \
 361    struct drm_clip_rect *cliprects;                                     \
 362    int x_off, y_off;                                                    \
 363    intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
 364
 365
 366 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
 367
 368 /* z16 depthbuffer functions. */
 369 #define INTEL_VALUE_TYPE GLushort
 370 #define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d)
 371 #define INTEL_READ_DEPTH(offset) pread_16(irb, offset)
 372 #define INTEL_TAG(name) name##_z16
 373 #include "intel_depthtmp.h"
 374
 375 /* z24 depthbuffer functions. */
 376 #define INTEL_VALUE_TYPE GLuint
 377 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
 378 #define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
 379 #define INTEL_TAG(name) name##_z24
 380 #include "intel_depthtmp.h"
 381
 382 /* z24s8 depthbuffer functions. */
 383 #define INTEL_VALUE_TYPE GLuint
 384 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, z24s8_to_s8z24(d))
 385 #define INTEL_READ_DEPTH(offset) s8z24_to_z24s8(pread_32(irb, offset))
 386 #define INTEL_TAG(name) name##_z24_s8
 387 #include "intel_depthtmp.h"
 388
 389
 390 /**
 391  ** 8-bit stencil function (XXX FBO: This is obsolete)
 392  **/
 393 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
 394 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
 395 #define TAG(x) intel##x##_z24_s8
 396 #include "stenciltmp.h"
 397
 398 /**
 399  ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
 400  **/
 401 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, X_TILE(_x, _y) + 3, d)
 402 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, X_TILE(_x, _y) + 3);
 403 #define TAG(x) intel_XTile_##x##_z24_s8
 404 #include "stenciltmp.h"
 405
 406 /**
 407  ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
 408  **/
 409 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, Y_TILE(_x, _y) + 3, d)
 410 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, Y_TILE(_x, _y) + 3)
 411 #define TAG(x) intel_YTile_##x##_z24_s8
 412 #include "stenciltmp.h"
 413
 414 void
 415 intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
 416 {
 417    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 418
 419    if (irb == NULL || irb->region == NULL)
 420       return;
 421
 422    intel_set_span_functions(intel, rb);
 423 }
 424
 425 void
 426 intel_renderbuffer_unmap(struct intel_context *intel,
 427                          struct gl_renderbuffer *rb)
 428 {
 429    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 430
 431    if (irb == NULL || irb->region == NULL)
 432       return;
 433
 434    clear_span_cache(irb);
 435
 436    rb->GetRow = NULL;
 437    rb->PutRow = NULL;
 438 }
 439
 440 /**
 441  * Map or unmap all the renderbuffers which we may need during
 442  * software rendering.
 443  * XXX in the future, we could probably convey extra information to
 444  * reduce the number of mappings needed.  I.e. if doing a glReadPixels
 445  * from the depth buffer, we really only need one mapping.
 446  *
 447  * XXX Rewrite this function someday.
 448  * We can probably just loop over all the renderbuffer attachments,
 449  * map/unmap all of them, and not worry about the _ColorDrawBuffers
 450  * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
 451  */
 452 static void
 453 intel_map_unmap_framebuffer(struct intel_context *intel,
 454                             struct gl_framebuffer *fb,
 455                             GLboolean map)
 456 {
 457    GLuint i;
 458
 459    /* color draw buffers */
 460    for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
 461       if (map)
 462          intel_renderbuffer_map(intel, fb->_ColorDrawBuffers[i]);
 463       else
 464          intel_renderbuffer_unmap(intel, fb->_ColorDrawBuffers[i]);
 465    }
 466
 467    /* color read buffer */
 468    if (map)
 469       intel_renderbuffer_map(intel, fb->_ColorReadBuffer);
 470    else
 471       intel_renderbuffer_unmap(intel, fb->_ColorReadBuffer);
 472
 473    /* check for render to textures */
 474    for (i = 0; i < BUFFER_COUNT; i++) {
 475       struct gl_renderbuffer_attachment *att =
 476          fb->Attachment + i;
 477       struct gl_texture_object *tex = att->Texture;
 478       if (tex) {
 479          /* render to texture */
 480          ASSERT(att->Renderbuffer);
 481          if (map)
 482             intel_tex_map_images(intel, intel_texture_object(tex));
 483          else
 484             intel_tex_unmap_images(intel, intel_texture_object(tex));
 485       }
 486    }
 487
 488    /* depth buffer (Note wrapper!) */
 489    if (fb->_DepthBuffer) {
 490       if (map)
 491          intel_renderbuffer_map(intel, fb->_DepthBuffer->Wrapped);
 492       else
 493          intel_renderbuffer_unmap(intel, fb->_DepthBuffer->Wrapped);
 494    }
 495
 496    /* stencil buffer (Note wrapper!) */
 497    if (fb->_StencilBuffer) {
 498       if (map)
 499          intel_renderbuffer_map(intel, fb->_StencilBuffer->Wrapped);
 500       else
 501          intel_renderbuffer_unmap(intel, fb->_StencilBuffer->Wrapped);
 502    }
 503 }
 504
 505 /**
 506  * Prepare for software rendering.  Map current read/draw framebuffers'
 507  * renderbuffes and all currently bound texture objects.
 508  *
 509  * Old note: Moved locking out to get reasonable span performance.
 510  */
 511 void
 512 intelSpanRenderStart(GLcontext * ctx)
 513 {
 514    struct intel_context *intel = intel_context(ctx);
 515    GLuint i;
 516
 517    intelFlush(&intel->ctx);
 518    LOCK_HARDWARE(intel);
 519
 520    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 521       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 522          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 523          intel_tex_map_images(intel, intel_texture_object(texObj));
 524       }
 525    }
 526
 527    intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_TRUE);
 528    if (ctx->ReadBuffer != ctx->DrawBuffer)
 529       intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_TRUE);
 530 }
 531
 532 /**
 533  * Called when done software rendering.  Unmap the buffers we mapped in
 534  * the above function.
 535  */
 536 void
 537 intelSpanRenderFinish(GLcontext * ctx)
 538 {
 539    struct intel_context *intel = intel_context(ctx);
 540    GLuint i;
 541
 542    _swrast_flush(ctx);
 543
 544    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 545       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 546          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 547          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 548       }
 549    }
 550
 551    intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_FALSE);
 552    if (ctx->ReadBuffer != ctx->DrawBuffer)
 553       intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_FALSE);
 554
 555    UNLOCK_HARDWARE(intel);
 556 }
 557
 558
 559 void
 560 intelInitSpanFuncs(GLcontext * ctx)
 561 {
 562    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 563    swdd->SpanRenderStart = intelSpanRenderStart;
 564    swdd->SpanRenderFinish = intelSpanRenderFinish;
 565 }
 566
 567 void
 568 intel_map_vertex_shader_textures(GLcontext *ctx)
 569 {
 570    struct intel_context *intel = intel_context(ctx);
 571    int i;
 572
 573    if (ctx->VertexProgram._Current == NULL)
 574       return;
 575
 576    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 577       if (ctx->Texture.Unit[i]._ReallyEnabled &&
 578           ctx->VertexProgram._Current->Base.TexturesUsed[i] != 0) {
 579          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 580
 581          intel_tex_map_images(intel, intel_texture_object(texObj));
 582       }
 583    }
 584 }
 585
 586 void
 587 intel_unmap_vertex_shader_textures(GLcontext *ctx)
 588 {
 589    struct intel_context *intel = intel_context(ctx);
 590    int i;
 591
 592    if (ctx->VertexProgram._Current == NULL)
 593       return;
 594
 595    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 596       if (ctx->Texture.Unit[i]._ReallyEnabled &&
 597           ctx->VertexProgram._Current->Base.TexturesUsed[i] != 0) {
 598          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 599
 600          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 601       }
 602    }
 603 }
 604
 605 /**
 606  * Plug in appropriate span read/write functions for the given renderbuffer.
 607  * These are used for the software fallbacks.
 608  */
 609 static void
 610 intel_set_span_functions(struct intel_context *intel,
 611                          struct gl_renderbuffer *rb)
 612 {
 613    struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
 614    uint32_t tiling;
 615
 616    /* If in GEM mode, we need to do the tile address swizzling ourselves,
 617     * instead of the fence registers handling it.
 618     */
 619    if (intel->ttm)
 620       tiling = irb->region->tiling;
 621    else
 622       tiling = I915_TILING_NONE;
 623
 624    switch (irb->texformat->MesaFormat) {
 625    case MESA_FORMAT_RGB565:
 626       switch (tiling) {
 627       case I915_TILING_NONE:
 628       default:
 629          intelInitPointers_RGB565(rb);
 630          break;
 631       case I915_TILING_X:
 632          intel_XTile_InitPointers_RGB565(rb);
 633          break;
 634       case I915_TILING_Y:
 635          intel_YTile_InitPointers_RGB565(rb);
 636          break;
 637       }
 638       break;
 639    case MESA_FORMAT_ARGB4444:
 640       switch (tiling) {
 641       case I915_TILING_NONE:
 642       default:
 643          intelInitPointers_ARGB4444(rb);
 644          break;
 645       case I915_TILING_X:
 646          intel_XTile_InitPointers_ARGB4444(rb);
 647          break;
 648       case I915_TILING_Y:
 649          intel_YTile_InitPointers_ARGB4444(rb);
 650          break;
 651       }
 652       break;
 653    case MESA_FORMAT_ARGB1555:
 654       switch (tiling) {
 655       case I915_TILING_NONE:
 656       default:
 657          intelInitPointers_ARGB1555(rb);
 658          break;
 659       case I915_TILING_X:
 660          intel_XTile_InitPointers_ARGB1555(rb);
 661          break;
 662       case I915_TILING_Y:
 663          intel_YTile_InitPointers_ARGB1555(rb);
 664          break;
 665       }
 666       break;
 667    case MESA_FORMAT_ARGB8888:
 668       if (rb->AlphaBits == 0) { /* XXX: Need xRGB8888 Mesa format */
 669          /* 8888 RGBx */
 670          switch (tiling) {
 671          case I915_TILING_NONE:
 672          default:
 673             intelInitPointers_xRGB8888(rb);
 674             break;
 675          case I915_TILING_X:
 676             intel_XTile_InitPointers_xRGB8888(rb);
 677             break;
 678          case I915_TILING_Y:
 679             intel_YTile_InitPointers_xRGB8888(rb);
 680             break;
 681          }
 682       } else {
 683          /* 8888 RGBA */
 684          switch (tiling) {
 685          case I915_TILING_NONE:
 686          default:
 687             intelInitPointers_ARGB8888(rb);
 688             break;
 689          case I915_TILING_X:
 690             intel_XTile_InitPointers_ARGB8888(rb);
 691             break;
 692          case I915_TILING_Y:
 693             intel_YTile_InitPointers_ARGB8888(rb);
 694             break;
 695          }
 696       }
 697       break;
 698    case MESA_FORMAT_Z16:
 699       switch (tiling) {
 700       case I915_TILING_NONE:
 701       default:
 702          intelInitDepthPointers_z16(rb);
 703          break;
 704       case I915_TILING_X:
 705          intel_XTile_InitDepthPointers_z16(rb);
 706          break;
 707       case I915_TILING_Y:
 708          intel_YTile_InitDepthPointers_z16(rb);
 709          break;
 710       }
 711       break;
 712    case MESA_FORMAT_S8_Z24:
 713       /* There are a few different ways SW asks us to access the S8Z24 data:
 714        * Z24 depth-only depth reads
 715        * S8Z24 depth reads
 716        * S8Z24 stencil reads.
 717        */
 718       if (rb->_ActualFormat == GL_DEPTH_COMPONENT24) {
 719          switch (tiling) {
 720          case I915_TILING_NONE:
 721          default:
 722             intelInitDepthPointers_z24(rb);
 723             break;
 724          case I915_TILING_X:
 725             intel_XTile_InitDepthPointers_z24(rb);
 726             break;
 727          case I915_TILING_Y:
 728             intel_YTile_InitDepthPointers_z24(rb);
 729             break;
 730          }
 731       } else if (rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
 732          switch (tiling) {
 733          case I915_TILING_NONE:
 734          default:
 735             intelInitDepthPointers_z24_s8(rb);
 736             break;
 737          case I915_TILING_X:
 738             intel_XTile_InitDepthPointers_z24_s8(rb);
 739             break;
 740          case I915_TILING_Y:
 741             intel_YTile_InitDepthPointers_z24_s8(rb);
 742             break;
 743          }
 744       } else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) {
 745          switch (tiling) {
 746          case I915_TILING_NONE:
 747          default:
 748             intelInitStencilPointers_z24_s8(rb);
 749             break;
 750          case I915_TILING_X:
 751             intel_XTile_InitStencilPointers_z24_s8(rb);
 752             break;
 753          case I915_TILING_Y:
 754             intel_YTile_InitStencilPointers_z24_s8(rb);
 755             break;
 756          }
 757       } else {
 758          _mesa_problem(NULL,
 759                        "Unexpected ActualFormat in intelSetSpanFunctions");
 760       }
 761       break;
 762    default:
 763       _mesa_problem(NULL,
 764                     "Unexpected MesaFormat in intelSetSpanFunctions");
 765       break;
 766    }
 767 }