src/mesa/drivers/dri/intel/intel_span.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "glheader.h"
  29 #include "macros.h"
  30 #include "mtypes.h"
  31 #include "colormac.h"
  32
  33 #include "intel_fbo.h"
  34 #include "intel_screen.h"
  35 #include "intel_span.h"
  36 #include "intel_regions.h"
  37 #include "intel_ioctl.h"
  38 #include "intel_tex.h"
  39
  40 #include "swrast/swrast.h"
  41
  42 static void
  43 intel_set_span_functions(struct intel_context *intel,
  44                          struct gl_renderbuffer *rb);
  45
  46 #define SPAN_CACHE_SIZE         4096
  47
  48 static void
  49 get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
  50 {
  51    if (irb->span_cache == NULL) {
  52       irb->span_cache = _mesa_malloc(SPAN_CACHE_SIZE);
  53       irb->span_cache_offset = -1;
  54    }
  55
  56    if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
  57       irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
  58       dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
  59                          SPAN_CACHE_SIZE, irb->span_cache);
  60    }
  61 }
  62
  63 static void
  64 clear_span_cache(struct intel_renderbuffer *irb)
  65 {
  66    irb->span_cache_offset = -1;
  67 }
  68
  69 static uint32_t
  70 pread_32(struct intel_renderbuffer *irb, uint32_t offset)
  71 {
  72    get_span_cache(irb, offset);
  73
  74    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  75 }
  76
  77 static uint32_t
  78 pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
  79 {
  80    get_span_cache(irb, offset);
  81
  82    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
  83       0xff000000;
  84 }
  85
  86 static uint16_t
  87 pread_16(struct intel_renderbuffer *irb, uint32_t offset)
  88 {
  89    get_span_cache(irb, offset);
  90
  91    return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  92 }
  93
  94 static uint8_t
  95 pread_8(struct intel_renderbuffer *irb, uint32_t offset)
  96 {
  97    get_span_cache(irb, offset);
  98
  99    return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
 100 }
 101
 102 static void
 103 pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 104 {
 105    clear_span_cache(irb);
 106
 107    dri_bo_subdata(irb->region->buffer, offset, 4, &val);
 108 }
 109
 110 static void
 111 pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 112 {
 113    clear_span_cache(irb);
 114
 115    dri_bo_subdata(irb->region->buffer, offset, 3, &val);
 116 }
 117
 118 static void
 119 pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
 120 {
 121    clear_span_cache(irb);
 122
 123    dri_bo_subdata(irb->region->buffer, offset, 2, &val);
 124 }
 125
 126 static void
 127 pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
 128 {
 129    clear_span_cache(irb);
 130
 131    dri_bo_subdata(irb->region->buffer, offset, 1, &val);
 132 }
 133
 134 static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
 135                                 struct intel_context *intel,
 136                                 int x, int y)
 137 {
 138         x += intel->drawX;
 139         y += intel->drawY;
 140
 141         return (y * irb->region->pitch + x) * irb->region->cpp;
 142 }
 143
 144 /*
 145  * Deal with tiled surfaces
 146  */
 147
 148 static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
 149                                struct intel_context *intel,
 150                                int x, int y)
 151 {
 152         int     tile_stride;
 153         int     xbyte;
 154         int     x_tile_off, y_tile_off;
 155         int     x_tile_number, y_tile_number;
 156         int     tile_off, tile_base;
 157
 158         tile_stride = (irb->pfPitch * irb->region->cpp) << 3;
 159
 160         x += intel->drawX;
 161         y += intel->drawY;
 162
 163         xbyte = x * irb->region->cpp;
 164
 165         x_tile_off = xbyte & 0x1ff;
 166         y_tile_off = y & 7;
 167
 168         x_tile_number = xbyte >> 9;
 169         y_tile_number = y >> 3;
 170
 171         tile_off = (y_tile_off << 9) + x_tile_off;
 172
 173         switch (irb->region->bit_6_swizzle) {
 174         case I915_BIT_6_SWIZZLE_NONE:
 175            break;
 176         case I915_BIT_6_SWIZZLE_9:
 177            tile_off ^= ((tile_off >> 3) & 64);
 178            break;
 179         case I915_BIT_6_SWIZZLE_9_10:
 180            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 181            break;
 182         case I915_BIT_6_SWIZZLE_9_11:
 183            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 184            break;
 185         case I915_BIT_6_SWIZZLE_9_10_11:
 186            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 187               ((tile_off >> 5) & 64);
 188            break;
 189         default:
 190            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 191                    irb->region->bit_6_swizzle);
 192            exit(1);
 193         }
 194
 195         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 196
 197 #if 0
 198         printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
 199                x, y, tile_off, tile_base,
 200                tile_off + tile_base,
 201                irb->pfPitch, tile_stride);
 202 #endif
 203
 204         return tile_base + tile_off;
 205 }
 206
 207 static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 208                                struct intel_context *intel,
 209                                int x, int y)
 210 {
 211         int     tile_stride;
 212         int     xbyte;
 213         int     x_tile_off, y_tile_off;
 214         int     x_tile_number, y_tile_number;
 215         int     tile_off, tile_base;
 216
 217         tile_stride = (irb->pfPitch * irb->region->cpp) << 5;
 218
 219         x += intel->drawX;
 220         y += intel->drawY;
 221
 222         xbyte = x * irb->region->cpp;
 223
 224         x_tile_off = xbyte & 0x7f;
 225         y_tile_off = y & 0x1f;
 226
 227         x_tile_number = xbyte >> 7;
 228         y_tile_number = y >> 5;
 229
 230         tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
 231            (x_tile_off & 0xf);
 232
 233         switch (irb->region->bit_6_swizzle) {
 234         case I915_BIT_6_SWIZZLE_NONE:
 235            break;
 236         case I915_BIT_6_SWIZZLE_9:
 237            tile_off ^= ((tile_off >> 3) & 64);
 238            break;
 239         case I915_BIT_6_SWIZZLE_9_10:
 240            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 241            break;
 242         case I915_BIT_6_SWIZZLE_9_11:
 243            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 244            break;
 245         case I915_BIT_6_SWIZZLE_9_10_11:
 246            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 247               ((tile_off >> 5) & 64);
 248            break;
 249         default:
 250            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 251                    irb->region->bit_6_swizzle);
 252            exit(1);
 253         }
 254
 255         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 256
 257         return tile_base + tile_off;
 258 }
 259
 260 /*
 261   break intelWriteRGBASpan_ARGB8888
 262 */
 263
 264 #undef DBG
 265 #define DBG 0
 266
 267 #define LOCAL_VARS                                                      \
 268    struct intel_context *intel = intel_context(ctx);                    \
 269    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 270    const GLint yScale = irb->RenderToTexture ? 1 : -1;                  \
 271    const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1; \
 272    GLuint p;                                                            \
 273    (void) p;
 274
 275 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
 276  * the cliprect info from the context, not the driDrawable.
 277  * Move this into spantmp2.h someday.
 278  */
 279 #define HW_CLIPLOOP()                                                   \
 280    do {                                                                 \
 281       int _nc = intel->numClipRects;                                    \
 282       while ( _nc-- ) {                                                 \
 283          int minx = intel->pClipRects[_nc].x1 - intel->drawX;           \
 284          int miny = intel->pClipRects[_nc].y1 - intel->drawY;           \
 285          int maxx = intel->pClipRects[_nc].x2 - intel->drawX;           \
 286          int maxy = intel->pClipRects[_nc].y2 - intel->drawY;
 287
 288 #if 0
 289       }}
 290 #endif
 291
 292 #define Y_FLIP(_y) ((_y) * yScale + yBias)
 293
 294 /* XXX with GEM, these need to tell the kernel */
 295 #define HW_LOCK()
 296
 297 #define HW_UNLOCK()
 298
 299 /* 16 bit, RGB565 color spanline and pixel functions
 300  */
 301 #define SPANTMP_PIXEL_FMT GL_RGB
 302 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
 303
 304 #define TAG(x)    intel##x##_RGB565
 305 #define TAG2(x,y) intel##x##_RGB565##y
 306 #define GET_VALUE(X, Y) pread_16(irb, no_tile_swizzle(irb, intel, X, Y))
 307 #define PUT_VALUE(X, Y, V) pwrite_16(irb, no_tile_swizzle(irb, intel, X, Y), V)
 308 #include "spantmp2.h"
 309
 310 /* 32 bit, ARGB8888 color spanline and pixel functions
 311  */
 312 #define SPANTMP_PIXEL_FMT GL_BGRA
 313 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 314
 315 #define TAG(x)    intel##x##_ARGB8888
 316 #define TAG2(x,y) intel##x##_ARGB8888##y
 317 #define GET_VALUE(X, Y) pread_32(irb, no_tile_swizzle(irb, intel, X, Y))
 318 #define PUT_VALUE(X, Y, V) pwrite_32(irb, no_tile_swizzle(irb, intel, X, Y), V)
 319 #include "spantmp2.h"
 320
 321 /* 32 bit, xRGB8888 color spanline and pixel functions
 322  */
 323 #define SPANTMP_PIXEL_FMT GL_BGRA
 324 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 325
 326 #define TAG(x)    intel##x##_xRGB8888
 327 #define TAG2(x,y) intel##x##_xRGB8888##y
 328 #define GET_VALUE(X, Y) pread_xrgb8888(irb, no_tile_swizzle(irb, intel, X, Y))
 329 #define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, no_tile_swizzle(irb, intel, X, Y), V)
 330 #include "spantmp2.h"
 331
 332 /* 16 bit RGB565 color tile spanline and pixel functions
 333  */
 334
 335 #define SPANTMP_PIXEL_FMT GL_RGB
 336 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
 337
 338 #define TAG(x)    intel_XTile_##x##_RGB565
 339 #define TAG2(x,y) intel_XTile_##x##_RGB565##y
 340 #define GET_VALUE(X, Y) pread_16(irb, x_tile_swizzle(irb, intel, X, Y))
 341 #define PUT_VALUE(X, Y, V) pwrite_16(irb, x_tile_swizzle(irb, intel, X, Y), V)
 342 #include "spantmp2.h"
 343
 344 #define SPANTMP_PIXEL_FMT GL_RGB
 345 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
 346
 347 #define TAG(x)    intel_YTile_##x##_RGB565
 348 #define TAG2(x,y) intel_YTile_##x##_RGB565##y
 349 #define GET_VALUE(X, Y) pread_16(irb, y_tile_swizzle(irb, intel, X, Y))
 350 #define PUT_VALUE(X, Y, V) pwrite_16(irb, y_tile_swizzle(irb, intel, X, Y), V)
 351 #include "spantmp2.h"
 352
 353 /* 32 bit ARGB888 color tile spanline and pixel functions
 354  */
 355
 356 #define SPANTMP_PIXEL_FMT GL_BGRA
 357 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 358
 359 #define TAG(x)    intel_XTile_##x##_ARGB8888
 360 #define TAG2(x,y) intel_XTile_##x##_ARGB8888##y
 361 #define GET_VALUE(X, Y) pread_32(irb, x_tile_swizzle(irb, intel, X, Y))
 362 #define PUT_VALUE(X, Y, V) pwrite_32(irb, x_tile_swizzle(irb, intel, X, Y), V)
 363 #include "spantmp2.h"
 364
 365 #define SPANTMP_PIXEL_FMT GL_BGRA
 366 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 367
 368 #define TAG(x)    intel_YTile_##x##_ARGB8888
 369 #define TAG2(x,y) intel_YTile_##x##_ARGB8888##y
 370 #define GET_VALUE(X, Y) pread_32(irb, y_tile_swizzle(irb, intel, X, Y))
 371 #define PUT_VALUE(X, Y, V) pwrite_32(irb, y_tile_swizzle(irb, intel, X, Y), V)
 372 #include "spantmp2.h"
 373
 374 /* 32 bit xRGB888 color tile spanline and pixel functions
 375  */
 376
 377 #define SPANTMP_PIXEL_FMT GL_BGRA
 378 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 379
 380 #define TAG(x)    intel_XTile_##x##_xRGB8888
 381 #define TAG2(x,y) intel_XTile_##x##_xRGB8888##y
 382 #define GET_VALUE(X, Y) pread_xrgb8888(irb, x_tile_swizzle(irb, intel, X, Y))
 383 #define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, x_tile_swizzle(irb, intel, X, Y), V)
 384 #include "spantmp2.h"
 385
 386 #define SPANTMP_PIXEL_FMT GL_BGRA
 387 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 388
 389 #define TAG(x)    intel_YTile_##x##_xRGB8888
 390 #define TAG2(x,y) intel_YTile_##x##_xRGB8888##y
 391 #define GET_VALUE(X, Y) pread_xrgb8888(irb, y_tile_swizzle(irb, intel, X, Y))
 392 #define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, y_tile_swizzle(irb, intel, X, Y), V)
 393 #include "spantmp2.h"
 394
 395 #define LOCAL_DEPTH_VARS                                                \
 396    struct intel_context *intel = intel_context(ctx);                    \
 397    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 398    const GLint yScale = irb->RenderToTexture ? 1 : -1;                  \
 399    const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1;
 400
 401
 402 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
 403
 404 /**
 405  ** 16-bit depthbuffer functions.
 406  **/
 407 #define VALUE_TYPE GLushort
 408 #define WRITE_DEPTH(_x, _y, d) \
 409    pwrite_16(irb, no_tile_swizzle(irb, intel, _x, _y), d)
 410 #define READ_DEPTH(d, _x, _y) \
 411    d = pread_16(irb, no_tile_swizzle(irb, intel, _x, _y))
 412 #define TAG(x) intel##x##_z16
 413 #include "depthtmp.h"
 414
 415
 416 /**
 417  ** 16-bit x tile depthbuffer functions.
 418  **/
 419 #define VALUE_TYPE GLushort
 420 #define WRITE_DEPTH(_x, _y, d) \
 421    pwrite_16(irb, x_tile_swizzle(irb, intel, _x, _y), d)
 422 #define READ_DEPTH(d, _x, _y) \
 423    d = pread_16(irb, x_tile_swizzle(irb, intel, _x, _y))
 424 #define TAG(x) intel_XTile_##x##_z16
 425 #include "depthtmp.h"
 426
 427 /**
 428  ** 16-bit y tile depthbuffer functions.
 429  **/
 430 #define VALUE_TYPE GLushort
 431 #define WRITE_DEPTH(_x, _y, d) \
 432    pwrite_16(irb, y_tile_swizzle(irb, intel, _x, _y), d)
 433 #define READ_DEPTH(d, _x, _y) \
 434    d = pread_16(irb, y_tile_swizzle(irb, intel, _x, _y))
 435 #define TAG(x) intel_YTile_##x##_z16
 436 #include "depthtmp.h"
 437
 438
 439 /**
 440  ** 24/8-bit interleaved depth/stencil functions
 441  ** Note: we're actually reading back combined depth+stencil values.
 442  ** The wrappers in main/depthstencil.c are used to extract the depth
 443  ** and stencil values.
 444  **/
 445 #define VALUE_TYPE GLuint
 446
 447 /* Change ZZZS -> SZZZ */
 448 #define WRITE_DEPTH(_x, _y, d)                                  \
 449    pwrite_32(irb, no_tile_swizzle(irb, intel, _x, _y),          \
 450              ((d) >> 8) | ((d) << 24))
 451
 452 /* Change SZZZ -> ZZZS */
 453 #define READ_DEPTH( d, _x, _y ) {                               \
 454    GLuint tmp = pread_32(irb, no_tile_swizzle(irb, intel, _x, _y));     \
 455    d = (tmp << 8) | (tmp >> 24);                                \
 456 }
 457
 458 #define TAG(x) intel##x##_z24_s8
 459 #include "depthtmp.h"
 460
 461
 462 /**
 463  ** 24/8-bit x-tile interleaved depth/stencil functions
 464  ** Note: we're actually reading back combined depth+stencil values.
 465  ** The wrappers in main/depthstencil.c are used to extract the depth
 466  ** and stencil values.
 467  **/
 468 #define VALUE_TYPE GLuint
 469
 470 /* Change ZZZS -> SZZZ */
 471 #define WRITE_DEPTH(_x, _y, d)                                  \
 472    pwrite_32(irb, x_tile_swizzle(irb, intel, _x, _y),           \
 473              ((d) >> 8) | ((d) << 24))                          \
 474
 475 /* Change SZZZ -> ZZZS */
 476 #define READ_DEPTH( d, _x, _y ) {                               \
 477    GLuint tmp = pread_32(irb, x_tile_swizzle(irb, intel, _x, _y));      \
 478    d = (tmp << 8) | (tmp >> 24);                                \
 479 }
 480
 481 #define TAG(x) intel_XTile_##x##_z24_s8
 482 #include "depthtmp.h"
 483
 484 /**
 485  ** 24/8-bit y-tile interleaved depth/stencil functions
 486  ** Note: we're actually reading back combined depth+stencil values.
 487  ** The wrappers in main/depthstencil.c are used to extract the depth
 488  ** and stencil values.
 489  **/
 490 #define VALUE_TYPE GLuint
 491
 492 /* Change ZZZS -> SZZZ */
 493 #define WRITE_DEPTH(_x, _y, d)                                  \
 494    pwrite_32(irb, y_tile_swizzle(irb, intel, _x, _y),           \
 495              ((d) >> 8) | ((d) << 24))
 496
 497 /* Change SZZZ -> ZZZS */
 498 #define READ_DEPTH( d, _x, _y ) {                               \
 499    GLuint tmp = pread_32(irb, y_tile_swizzle(irb, intel, _x, _y));      \
 500    d = (tmp << 8) | (tmp >> 24);                                \
 501 }
 502
 503 #define TAG(x) intel_YTile_##x##_z24_s8
 504 #include "depthtmp.h"
 505
 506
 507 /**
 508  ** 8-bit stencil function (XXX FBO: This is obsolete)
 509  **/
 510 #define WRITE_STENCIL(_x, _y, d)                                \
 511    pwrite_8(irb, no_tile_swizzle(irb, intel, _x, _y) + 3, d)
 512
 513 #define READ_STENCIL(d, _x, _y)                                 \
 514    d = pread_8(irb, no_tile_swizzle(irb, intel, _x, _y) + 3);
 515
 516 #define TAG(x) intel##x##_z24_s8
 517 #include "stenciltmp.h"
 518
 519 /**
 520  ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
 521  **/
 522 #define WRITE_STENCIL(_x, _y, d)                                \
 523    pwrite_8(irb, x_tile_swizzle(irb, intel, _x, _y) + 3, d)
 524
 525 #define READ_STENCIL(d, _x, _y)                                 \
 526    d = pread_8(irb, x_tile_swizzle(irb, intel, _x, _y) + 3);
 527
 528 #define TAG(x) intel_XTile_##x##_z24_s8
 529 #include "stenciltmp.h"
 530
 531 /**
 532  ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
 533  **/
 534 #define WRITE_STENCIL(_x, _y, d)                                \
 535    pwrite_8(irb, y_tile_swizzle(irb, intel, _x, _y) + 3, d)
 536
 537 #define READ_STENCIL(d, _x, _y)                                 \
 538    d = pread_8(irb, y_tile_swizzle(irb, intel, _x, _y) + 3)
 539
 540 #define TAG(x) intel_YTile_##x##_z24_s8
 541 #include "stenciltmp.h"
 542
 543 void
 544 intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
 545 {
 546    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 547
 548    if (irb == NULL || irb->region == NULL)
 549       return;
 550
 551    irb->pfPitch = irb->region->pitch;
 552
 553    intel_set_span_functions(intel, rb);
 554 }
 555
 556 void
 557 intel_renderbuffer_unmap(struct intel_context *intel,
 558                          struct gl_renderbuffer *rb)
 559 {
 560    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 561
 562    if (irb == NULL || irb->region == NULL)
 563       return;
 564
 565    clear_span_cache(irb);
 566    irb->pfPitch = 0;
 567
 568    rb->GetRow = NULL;
 569    rb->PutRow = NULL;
 570 }
 571
 572 /**
 573  * Map or unmap all the renderbuffers which we may need during
 574  * software rendering.
 575  * XXX in the future, we could probably convey extra information to
 576  * reduce the number of mappings needed.  I.e. if doing a glReadPixels
 577  * from the depth buffer, we really only need one mapping.
 578  *
 579  * XXX Rewrite this function someday.
 580  * We can probably just loop over all the renderbuffer attachments,
 581  * map/unmap all of them, and not worry about the _ColorDrawBuffers
 582  * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
 583  */
 584 static void
 585 intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
 586 {
 587    GLcontext *ctx = &intel->ctx;
 588    GLuint i, j;
 589
 590    /* color draw buffers */
 591    for (j = 0; j < ctx->DrawBuffer->_NumColorDrawBuffers; j++) {
 592       if (map)
 593          intel_renderbuffer_map(intel, ctx->DrawBuffer->_ColorDrawBuffers[j]);
 594       else
 595          intel_renderbuffer_unmap(intel, ctx->DrawBuffer->_ColorDrawBuffers[j]);
 596    }
 597
 598    /* check for render to textures */
 599    for (i = 0; i < BUFFER_COUNT; i++) {
 600       struct gl_renderbuffer_attachment *att =
 601          ctx->DrawBuffer->Attachment + i;
 602       struct gl_texture_object *tex = att->Texture;
 603       if (tex) {
 604          /* render to texture */
 605          ASSERT(att->Renderbuffer);
 606          if (map) {
 607             struct gl_texture_image *texImg;
 608             texImg = tex->Image[att->CubeMapFace][att->TextureLevel];
 609             intel_tex_map_images(intel, intel_texture_object(tex));
 610          }
 611          else {
 612             intel_tex_unmap_images(intel, intel_texture_object(tex));
 613          }
 614       }
 615    }
 616
 617    /* color read buffers */
 618    if (map)
 619       intel_renderbuffer_map(intel, ctx->ReadBuffer->_ColorReadBuffer);
 620    else
 621       intel_renderbuffer_unmap(intel, ctx->ReadBuffer->_ColorReadBuffer);
 622
 623    /* depth buffer (Note wrapper!) */
 624    if (ctx->DrawBuffer->_DepthBuffer) {
 625       if (map)
 626          intel_renderbuffer_map(intel, ctx->DrawBuffer->_DepthBuffer->Wrapped);
 627       else
 628          intel_renderbuffer_unmap(intel,
 629                                   ctx->DrawBuffer->_DepthBuffer->Wrapped);
 630    }
 631
 632    /* stencil buffer (Note wrapper!) */
 633    if (ctx->DrawBuffer->_StencilBuffer) {
 634       if (map)
 635          intel_renderbuffer_map(intel,
 636                                 ctx->DrawBuffer->_StencilBuffer->Wrapped);
 637       else
 638          intel_renderbuffer_unmap(intel,
 639                                   ctx->DrawBuffer->_StencilBuffer->Wrapped);
 640    }
 641 }
 642
 643
 644
 645 /**
 646  * Prepare for softare rendering.  Map current read/draw framebuffers'
 647  * renderbuffes and all currently bound texture objects.
 648  *
 649  * Old note: Moved locking out to get reasonable span performance.
 650  */
 651 void
 652 intelSpanRenderStart(GLcontext * ctx)
 653 {
 654    struct intel_context *intel = intel_context(ctx);
 655    GLuint i;
 656
 657    intelFlush(&intel->ctx);
 658    LOCK_HARDWARE(intel);
 659
 660    for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
 661       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 662          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 663          intel_tex_map_images(intel, intel_texture_object(texObj));
 664       }
 665    }
 666
 667    intel_map_unmap_buffers(intel, GL_TRUE);
 668 }
 669
 670 /**
 671  * Called when done softare rendering.  Unmap the buffers we mapped in
 672  * the above function.
 673  */
 674 void
 675 intelSpanRenderFinish(GLcontext * ctx)
 676 {
 677    struct intel_context *intel = intel_context(ctx);
 678    GLuint i;
 679
 680    _swrast_flush(ctx);
 681
 682    for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
 683       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 684          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 685          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 686       }
 687    }
 688
 689    intel_map_unmap_buffers(intel, GL_FALSE);
 690
 691    UNLOCK_HARDWARE(intel);
 692 }
 693
 694
 695 void
 696 intelInitSpanFuncs(GLcontext * ctx)
 697 {
 698    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 699    swdd->SpanRenderStart = intelSpanRenderStart;
 700    swdd->SpanRenderFinish = intelSpanRenderFinish;
 701 }
 702
 703
 704 /**
 705  * Plug in appropriate span read/write functions for the given renderbuffer.
 706  * These are used for the software fallbacks.
 707  */
 708 static void
 709 intel_set_span_functions(struct intel_context *intel,
 710                          struct gl_renderbuffer *rb)
 711 {
 712    struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
 713    uint32_t tiling;
 714
 715    /* If in GEM mode, we need to do the tile address swizzling ourselves,
 716     * instead of the fence registers handling it.
 717     */
 718    if (intel->ttm)
 719       tiling = irb->region->tiling;
 720    else
 721       tiling = I915_TILING_NONE;
 722
 723    if (rb->_ActualFormat == GL_RGB5) {
 724       /* 565 RGB */
 725       switch (tiling) {
 726       case I915_TILING_NONE:
 727       default:
 728          intelInitPointers_RGB565(rb);
 729          break;
 730       case I915_TILING_X:
 731          intel_XTile_InitPointers_RGB565(rb);
 732          break;
 733       case I915_TILING_Y:
 734          intel_YTile_InitPointers_RGB565(rb);
 735          break;
 736       }
 737    }
 738    else if (rb->_ActualFormat == GL_RGB8) {
 739       /* 8888 RGBx */
 740       switch (tiling) {
 741       case I915_TILING_NONE:
 742       default:
 743          intelInitPointers_xRGB8888(rb);
 744          break;
 745       case I915_TILING_X:
 746          intel_XTile_InitPointers_xRGB8888(rb);
 747          break;
 748       case I915_TILING_Y:
 749          intel_YTile_InitPointers_xRGB8888(rb);
 750          break;
 751       }
 752    }
 753    else if (rb->_ActualFormat == GL_RGBA8) {
 754       /* 8888 RGBA */
 755       switch (tiling) {
 756       case I915_TILING_NONE:
 757       default:
 758          intelInitPointers_ARGB8888(rb);
 759          break;
 760       case I915_TILING_X:
 761          intel_XTile_InitPointers_ARGB8888(rb);
 762          break;
 763       case I915_TILING_Y:
 764          intel_YTile_InitPointers_ARGB8888(rb);
 765          break;
 766       }
 767    }
 768    else if (rb->_ActualFormat == GL_DEPTH_COMPONENT16) {
 769       switch (tiling) {
 770       case I915_TILING_NONE:
 771       default:
 772          intelInitDepthPointers_z16(rb);
 773          break;
 774       case I915_TILING_X:
 775          intel_XTile_InitDepthPointers_z16(rb);
 776          break;
 777       case I915_TILING_Y:
 778          intel_YTile_InitDepthPointers_z16(rb);
 779          break;
 780       }
 781    }
 782    else if (rb->_ActualFormat == GL_DEPTH_COMPONENT24 ||        /* XXX FBO remove */
 783             rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
 784       switch (tiling) {
 785       case I915_TILING_NONE:
 786       default:
 787          intelInitDepthPointers_z24_s8(rb);
 788          break;
 789       case I915_TILING_X:
 790          intel_XTile_InitDepthPointers_z24_s8(rb);
 791          break;
 792       case I915_TILING_Y:
 793          intel_YTile_InitDepthPointers_z24_s8(rb);
 794          break;
 795       }
 796    }
 797    else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) {
 798       switch (tiling) {
 799       case I915_TILING_NONE:
 800       default:
 801          intelInitStencilPointers_z24_s8(rb);
 802          break;
 803       case I915_TILING_X:
 804          intel_XTile_InitStencilPointers_z24_s8(rb);
 805          break;
 806       case I915_TILING_Y:
 807          intel_YTile_InitStencilPointers_z24_s8(rb);
 808          break;
 809       }
 810    }
 811    else {
 812       _mesa_problem(NULL,
 813                     "Unexpected _ActualFormat in intelSetSpanFunctions");
 814    }
 815 }