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intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.
[mesa.git] / src / mesa / drivers / dri / intel / intel_span.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "glheader.h"
29 #include "macros.h"
30 #include "mtypes.h"
31 #include "colormac.h"
32
33 #include "intel_fbo.h"
34 #include "intel_screen.h"
35 #include "intel_span.h"
36 #include "intel_regions.h"
37 #include "intel_ioctl.h"
38 #include "intel_tex.h"
39
40 #include "swrast/swrast.h"
41
42 /*
43 * Deal with tiled surfaces
44 */
45
46 #if 0
47 /* These are pre-965 tile swizzling functions -- power of two widths */
48 static uintptr_t x_tile_swizzle_pow2 (uintptr_t addr, int n)
49 {
50 uintptr_t a = addr;
51 uintptr_t base_mask = (((~0) << (n + 4)) | 0xff);
52 uintptr_t x_mask = ((~0) << 12) & ~base_mask;
53
54 a = ((a & base_mask) |
55 ((a >> (n-8)) & 0x7) |
56 ((a << 3) & x_mask));
57 _mesa_printf ("x_swizzle %08x (base %x yrow %x tile#x %x xsword %x byte %x) %08x\n",
58 addr,
59 addr >> (n + 4),
60 (addr >> (n + 1)) & 0x7,
61 (addr >> 9) & ((1 << (n-8)) - 1),
62 (addr >> 5) & 0xf,
63 (addr & 0x1f),
64 a);
65 return a;
66 }
67
68 static uintptr_t y_tile_swizzle_pow2 (uintptr_t addr, int n)
69 {
70 uintptr_t a = (uintptr_t) addr;
71 uintptr_t base_mask = (((~0) << (n + 6)) | 0xf);
72 uintptr_t x_mask = ((~0) << 9) & ~base_mask;
73
74 a = ((a & base_mask) |
75 ((a >> (n-3)) & 0x1f) |
76 ((a << 5) & x_mask));
77 _mesa_printf ("y_swizzle %08x (base %x yrow %x tile#x %x xoword %x byte %x) %08x\n",
78 addr,
79 addr >> (n + 6),
80 (addr >> (n + 1)) & 0x01f,
81 (addr >> 7) & ((1 << (n-6)) - 1),
82 (addr >> 4) & 0x7,
83 (addr & 0xf),
84 a);
85 return a;
86 }
87 #endif
88
89 static GLubyte *x_tile_swizzle(struct intel_renderbuffer *irb, struct intel_context *intel,
90 int x, int y)
91 {
92 GLubyte *buf = (GLubyte *) irb->pfMap;
93 int tile_stride;
94 int xbyte;
95 int x_tile_off, y_tile_off;
96 int x_tile_number, y_tile_number;
97 int tile_off, tile_base;
98
99 tile_stride = (irb->pfPitch * irb->region->cpp) << 3;
100
101 x += intel->drawX;
102 y += intel->drawY;
103
104 xbyte = x * irb->region->cpp;
105
106 x_tile_off = xbyte & 0x1ff;
107 y_tile_off = y & 7;
108
109 x_tile_number = xbyte >> 9;
110 y_tile_number = y >> 3;
111
112 tile_off = (y_tile_off << 9) + x_tile_off;
113
114 /* bit swizzling tricks your parents never told you about:
115 *
116 * The specs say that the X tiling layout is just 8 512-byte rows
117 * packed into a page. It turns out that there's some additional
118 * swizzling of bit 6 to reduce cache aliasing issues. Experimental
119 * results below:
120 *
121 * line bit GM965 945G/Q965
122 * 9 10 11
123 * 0 0 0 0 0 0
124 * 1 0 1 0 1 1
125 * 2 1 0 0 1 1
126 * 3 1 1 0 0 0
127 * 4 0 0 1 1 0
128 * 5 0 1 1 0 1
129 * 6 1 0 1 0 1
130 * 7 1 1 1 1 0
131 *
132 * So we see that the GM965 is bit 6 ^ 9 ^ 10 ^ 11, while other
133 * parts were just 6 ^ 9 ^ 10. However, some systems, including a
134 * GM965 we've seen, don't perform the swizzling at all. Information
135 * on how to detect it through register reads is expected soon.
136 */
137 switch (intel->tiling_swizzle_mode) {
138 case 0:
139 break;
140 case 1:
141 tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
142 break;
143 case 2:
144 tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
145 ((tile_off >> 5) & 64);
146 break;
147 }
148
149 tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
150
151 #if 0
152 printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
153 x, y, tile_off, tile_base,
154 tile_off + tile_base,
155 irb->pfPitch, tile_stride);
156 #endif
157
158 return buf + tile_base + tile_off;
159 }
160
161 static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_context *intel,
162 int x, int y)
163 {
164 GLubyte *buf = (GLubyte *) irb->pfMap;
165 int tile_stride;
166 int xbyte;
167 int x_tile_off, y_tile_off;
168 int x_tile_number, y_tile_number;
169 int tile_off, tile_base;
170
171 tile_stride = (irb->pfPitch * irb->region->cpp) << 5;
172
173 x += intel->drawX;
174 y += intel->drawY;
175
176 xbyte = x * irb->region->cpp;
177
178 x_tile_off = xbyte & 0x7f;
179 y_tile_off = y & 0x1f;
180
181 x_tile_number = xbyte >> 7;
182 y_tile_number = y >> 5;
183
184 tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
185 (x_tile_off & 0xf);
186
187 switch (intel->tiling_swizzle_mode) {
188 case 0:
189 break;
190 case 1:
191 tile_off ^= (tile_off >> 3) & 64;
192 break;
193 case 2:
194 break;
195 }
196 tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
197
198 return buf + tile_base + tile_off;
199 }
200
201 /*
202 break intelWriteRGBASpan_ARGB8888
203 */
204
205 #undef DBG
206 #define DBG 0
207
208 #define LOCAL_VARS \
209 struct intel_context *intel = intel_context(ctx); \
210 struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
211 const GLint yScale = irb->RenderToTexture ? 1 : -1; \
212 const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1; \
213 GLubyte *buf = (GLubyte *) irb->pfMap \
214 + (intel->drawY * irb->pfPitch + intel->drawX) * irb->region->cpp;\
215 GLuint p; \
216 assert(irb->pfMap);\
217 (void) p; (void) buf;
218
219 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
220 * the cliprect info from the context, not the driDrawable.
221 * Move this into spantmp2.h someday.
222 */
223 #define HW_CLIPLOOP() \
224 do { \
225 int _nc = intel->numClipRects; \
226 while ( _nc-- ) { \
227 int minx = intel->pClipRects[_nc].x1 - intel->drawX; \
228 int miny = intel->pClipRects[_nc].y1 - intel->drawY; \
229 int maxx = intel->pClipRects[_nc].x2 - intel->drawX; \
230 int maxy = intel->pClipRects[_nc].y2 - intel->drawY;
231
232 #if 0
233 }}
234 #endif
235
236 #define Y_FLIP(_y) ((_y) * yScale + yBias)
237
238 /* XXX with GEM, these need to tell the kernel */
239 #define HW_LOCK()
240
241 #define HW_UNLOCK()
242
243 /* 16 bit, RGB565 color spanline and pixel functions
244 */
245 #define SPANTMP_PIXEL_FMT GL_RGB
246 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
247
248 #define TAG(x) intel##x##_RGB565
249 #define TAG2(x,y) intel##x##_RGB565##y
250 #define GET_PTR(X,Y) (buf + ((Y) * irb->pfPitch + (X)) * 2)
251 #include "spantmp2.h"
252
253 /* 32 bit, ARGB8888 color spanline and pixel functions
254 */
255 #define SPANTMP_PIXEL_FMT GL_BGRA
256 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
257
258 #define TAG(x) intel##x##_ARGB8888
259 #define TAG2(x,y) intel##x##_ARGB8888##y
260 #define GET_PTR(X,Y) (buf + ((Y) * irb->pfPitch + (X)) * 4)
261 #include "spantmp2.h"
262
263 /* 16 bit RGB565 color tile spanline and pixel functions
264 */
265
266 #define SPANTMP_PIXEL_FMT GL_RGB
267 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
268
269 #define TAG(x) intel_XTile_##x##_RGB565
270 #define TAG2(x,y) intel_XTile_##x##_RGB565##y
271 #define GET_PTR(X,Y) x_tile_swizzle(irb, intel, X, Y)
272 #include "spantmp2.h"
273
274 #define SPANTMP_PIXEL_FMT GL_RGB
275 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
276
277 #define TAG(x) intel_YTile_##x##_RGB565
278 #define TAG2(x,y) intel_YTile_##x##_RGB565##y
279 #define GET_PTR(X,Y) y_tile_swizzle(irb, intel, X, Y)
280 #include "spantmp2.h"
281
282 /* 32 bit ARGB888 color tile spanline and pixel functions
283 */
284
285 #define SPANTMP_PIXEL_FMT GL_BGRA
286 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
287
288 #define TAG(x) intel_XTile_##x##_ARGB8888
289 #define TAG2(x,y) intel_XTile_##x##_ARGB8888##y
290 #define GET_PTR(X,Y) x_tile_swizzle(irb, intel, X, Y)
291 #include "spantmp2.h"
292
293 #define SPANTMP_PIXEL_FMT GL_BGRA
294 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
295
296 #define TAG(x) intel_YTile_##x##_ARGB8888
297 #define TAG2(x,y) intel_YTile_##x##_ARGB8888##y
298 #define GET_PTR(X,Y) y_tile_swizzle(irb, intel, X, Y)
299 #include "spantmp2.h"
300
301 #define LOCAL_DEPTH_VARS \
302 struct intel_context *intel = intel_context(ctx); \
303 struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
304 const GLuint pitch = irb->pfPitch/***XXX region->pitch*/; /* in pixels */ \
305 const GLint yScale = irb->RenderToTexture ? 1 : -1; \
306 const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1; \
307 char *buf = (char *) irb->pfMap/*XXX use region->map*/ + \
308 (intel->drawY * pitch + intel->drawX) * irb->region->cpp; (void) buf;
309
310
311 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
312
313 /**
314 ** 16-bit depthbuffer functions.
315 **/
316 #define WRITE_DEPTH( _x, _y, d ) \
317 ((GLushort *)buf)[(_x) + (_y) * pitch] = d;
318
319 #define READ_DEPTH( d, _x, _y ) \
320 d = ((GLushort *)buf)[(_x) + (_y) * pitch];
321
322
323 #define TAG(x) intel##x##_z16
324 #include "depthtmp.h"
325
326
327 /**
328 ** 16-bit x tile depthbuffer functions.
329 **/
330 #define WRITE_DEPTH( _x, _y, d ) \
331 (*((GLushort *)x_tile_swizzle (irb, intel, _x, _y)) = d)
332
333 #define READ_DEPTH( d, _x, _y ) \
334 d = *((GLushort *)x_tile_swizzle (irb, intel, _x, _y))
335
336
337 #define TAG(x) intel_XTile_##x##_z16
338 #include "depthtmp.h"
339
340 /**
341 ** 16-bit y tile depthbuffer functions.
342 **/
343 #define WRITE_DEPTH( _x, _y, d ) \
344 (*((GLushort *)y_tile_swizzle (irb, intel, _x, _y)) = d)
345
346 #define READ_DEPTH( d, _x, _y ) \
347 (d = *((GLushort *)y_tile_swizzle (irb, intel, _x, _y)))
348
349
350 #define TAG(x) intel_YTile_##x##_z16
351 #include "depthtmp.h"
352
353
354 /**
355 ** 24/8-bit interleaved depth/stencil functions
356 ** Note: we're actually reading back combined depth+stencil values.
357 ** The wrappers in main/depthstencil.c are used to extract the depth
358 ** and stencil values.
359 **/
360 /* Change ZZZS -> SZZZ */
361 #define WRITE_DEPTH( _x, _y, d ) { \
362 GLuint tmp = ((d) >> 8) | ((d) << 24); \
363 ((GLuint *)buf)[(_x) + (_y) * pitch] = tmp; \
364 }
365
366 /* Change SZZZ -> ZZZS */
367 #define READ_DEPTH( d, _x, _y ) { \
368 GLuint tmp = ((GLuint *)buf)[(_x) + (_y) * pitch]; \
369 d = (tmp << 8) | (tmp >> 24); \
370 }
371
372 #define TAG(x) intel##x##_z24_s8
373 #include "depthtmp.h"
374
375
376 /**
377 ** 24/8-bit x-tile interleaved depth/stencil functions
378 ** Note: we're actually reading back combined depth+stencil values.
379 ** The wrappers in main/depthstencil.c are used to extract the depth
380 ** and stencil values.
381 **/
382 /* Change ZZZS -> SZZZ */
383 #define WRITE_DEPTH( _x, _y, d ) { \
384 GLuint tmp = ((d) >> 8) | ((d) << 24); \
385 *((GLuint *)x_tile_swizzle (irb, intel, _x, _y)) = tmp; \
386 }
387
388 /* Change SZZZ -> ZZZS */
389 #define READ_DEPTH( d, _x, _y ) { \
390 GLuint tmp = *((GLuint *)x_tile_swizzle (irb, intel, _x, _y)); \
391 d = (tmp << 8) | (tmp >> 24); \
392 }
393
394 #define TAG(x) intel_XTile_##x##_z24_s8
395 #include "depthtmp.h"
396
397 /**
398 ** 24/8-bit y-tile interleaved depth/stencil functions
399 ** Note: we're actually reading back combined depth+stencil values.
400 ** The wrappers in main/depthstencil.c are used to extract the depth
401 ** and stencil values.
402 **/
403 /* Change ZZZS -> SZZZ */
404 #define WRITE_DEPTH( _x, _y, d ) { \
405 GLuint tmp = ((d) >> 8) | ((d) << 24); \
406 *((GLuint *)y_tile_swizzle (irb, intel, _x, _y)) = tmp; \
407 }
408
409 /* Change SZZZ -> ZZZS */
410 #define READ_DEPTH( d, _x, _y ) { \
411 GLuint tmp = *((GLuint *)y_tile_swizzle (irb, intel, _x, _y)); \
412 d = (tmp << 8) | (tmp >> 24); \
413 }
414
415 #define TAG(x) intel_YTile_##x##_z24_s8
416 #include "depthtmp.h"
417
418
419 /**
420 ** 8-bit stencil function (XXX FBO: This is obsolete)
421 **/
422 #define WRITE_STENCIL( _x, _y, d ) { \
423 GLuint tmp = ((GLuint *)buf)[(_x) + (_y) * pitch]; \
424 tmp &= 0xffffff; \
425 tmp |= ((d) << 24); \
426 ((GLuint *) buf)[(_x) + (_y) * pitch] = tmp; \
427 }
428
429 #define READ_STENCIL( d, _x, _y ) \
430 d = ((GLuint *)buf)[(_x) + (_y) * pitch] >> 24;
431
432 #define TAG(x) intel##x##_z24_s8
433 #include "stenciltmp.h"
434
435 /**
436 ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
437 **/
438 #define WRITE_STENCIL( _x, _y, d ) { \
439 GLuint *a = (GLuint *) x_tile_swizzle (irb, intel, _x, _y); \
440 GLuint tmp = *a; \
441 tmp &= 0xffffff; \
442 tmp |= ((d) << 24); \
443 *a = tmp; \
444 }
445
446 #define READ_STENCIL( d, _x, _y ) \
447 (d = *((GLuint*) x_tile_swizzle (irb, intel, _x, _y)) >> 24)
448
449 #define TAG(x) intel_XTile_##x##_z24_s8
450 #include "stenciltmp.h"
451
452 /**
453 ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
454 **/
455 #define WRITE_STENCIL( _x, _y, d ) { \
456 GLuint *a = (GLuint *) y_tile_swizzle (irb, intel, _x, _y); \
457 GLuint tmp = *a; \
458 tmp &= 0xffffff; \
459 tmp |= ((d) << 24); \
460 *a = tmp; \
461 }
462
463 #define READ_STENCIL( d, _x, _y ) \
464 (d = *((GLuint*) y_tile_swizzle (irb, intel, _x, _y)) >> 24)
465
466 #define TAG(x) intel_YTile_##x##_z24_s8
467 #include "stenciltmp.h"
468
469
470
471 /**
472 * Map or unmap all the renderbuffers which we may need during
473 * software rendering.
474 * XXX in the future, we could probably convey extra information to
475 * reduce the number of mappings needed. I.e. if doing a glReadPixels
476 * from the depth buffer, we really only need one mapping.
477 *
478 * XXX Rewrite this function someday.
479 * We can probably just loop over all the renderbuffer attachments,
480 * map/unmap all of them, and not worry about the _ColorDrawBuffers
481 * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
482 */
483 static void
484 intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
485 {
486 GLcontext *ctx = &intel->ctx;
487 GLuint i, j;
488 struct intel_renderbuffer *irb;
489
490 /* color draw buffers */
491 for (j = 0; j < ctx->DrawBuffer->_NumColorDrawBuffers; j++) {
492 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[j];
493 irb = intel_renderbuffer(rb);
494 if (irb) {
495 /* this is a user-created intel_renderbuffer */
496 if (irb->region) {
497 if (map)
498 intel_region_map(intel, irb->region);
499 else
500 intel_region_unmap(intel, irb->region);
501 irb->pfMap = irb->region->map;
502 irb->pfPitch = irb->region->pitch;
503 }
504 }
505 }
506
507 /* check for render to textures */
508 for (i = 0; i < BUFFER_COUNT; i++) {
509 struct gl_renderbuffer_attachment *att =
510 ctx->DrawBuffer->Attachment + i;
511 struct gl_texture_object *tex = att->Texture;
512 if (tex) {
513 /* render to texture */
514 ASSERT(att->Renderbuffer);
515 if (map) {
516 struct gl_texture_image *texImg;
517 texImg = tex->Image[att->CubeMapFace][att->TextureLevel];
518 intel_tex_map_images(intel, intel_texture_object(tex));
519 }
520 else {
521 intel_tex_unmap_images(intel, intel_texture_object(tex));
522 }
523 }
524 }
525
526 /* color read buffers */
527 irb = intel_renderbuffer(ctx->ReadBuffer->_ColorReadBuffer);
528 if (irb && irb->region) {
529 if (map)
530 intel_region_map(intel, irb->region);
531 else
532 intel_region_unmap(intel, irb->region);
533 irb->pfMap = irb->region->map;
534 irb->pfPitch = irb->region->pitch;
535 }
536
537 /* Account for front/back color page flipping.
538 * The span routines use the pfMap and pfPitch fields which will
539 * swap the front/back region map/pitch if we're page flipped.
540 * Do this after mapping, above, so the map field is valid.
541 */
542 #if 0
543 if (map && ctx->DrawBuffer->Name == 0) {
544 struct intel_renderbuffer *irbFront
545 = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_FRONT_LEFT);
546 struct intel_renderbuffer *irbBack
547 = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_BACK_LEFT);
548 if (irbBack) {
549 /* double buffered */
550 if (intel->sarea->pf_current_page == 0) {
551 irbFront->pfMap = irbFront->region->map;
552 irbFront->pfPitch = irbFront->region->pitch;
553 irbBack->pfMap = irbBack->region->map;
554 irbBack->pfPitch = irbBack->region->pitch;
555 }
556 else {
557 irbFront->pfMap = irbBack->region->map;
558 irbFront->pfPitch = irbBack->region->pitch;
559 irbBack->pfMap = irbFront->region->map;
560 irbBack->pfPitch = irbFront->region->pitch;
561 }
562 }
563 }
564 #endif
565
566 /* depth buffer (Note wrapper!) */
567 if (ctx->DrawBuffer->_DepthBuffer) {
568 irb = intel_renderbuffer(ctx->DrawBuffer->_DepthBuffer->Wrapped);
569 if (irb && irb->region) {
570 if (map) {
571 intel_region_map(intel, irb->region);
572 irb->pfMap = irb->region->map;
573 irb->pfPitch = irb->region->pitch;
574 }
575 else {
576 intel_region_unmap(intel, irb->region);
577 irb->pfMap = irb->region->map;
578 irb->pfPitch = irb->region->pitch;
579 }
580 }
581 }
582
583 /* stencil buffer (Note wrapper!) */
584 if (ctx->DrawBuffer->_StencilBuffer) {
585 irb = intel_renderbuffer(ctx->DrawBuffer->_StencilBuffer->Wrapped);
586 if (irb && irb->region) {
587 if (map) {
588 intel_region_map(intel, irb->region);
589 irb->pfMap = irb->region->map;
590 irb->pfPitch = irb->region->pitch;
591 }
592 else {
593 intel_region_unmap(intel, irb->region);
594 irb->pfMap = irb->region->map;
595 irb->pfPitch = irb->region->pitch;
596 }
597 }
598 }
599 }
600
601
602
603 /**
604 * Prepare for softare rendering. Map current read/draw framebuffers'
605 * renderbuffes and all currently bound texture objects.
606 *
607 * Old note: Moved locking out to get reasonable span performance.
608 */
609 void
610 intelSpanRenderStart(GLcontext * ctx)
611 {
612 struct intel_context *intel = intel_context(ctx);
613 GLuint i;
614
615 intelFinish(&intel->ctx);
616 LOCK_HARDWARE(intel);
617
618 #if 0
619 /* Just map the framebuffer and all textures. Bufmgr code will
620 * take care of waiting on the necessary fences:
621 */
622 intel_region_map(intel, intel->front_region);
623 intel_region_map(intel, intel->back_region);
624 intel_region_map(intel, intel->depth_region);
625 #endif
626
627 for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
628 if (ctx->Texture.Unit[i]._ReallyEnabled) {
629 struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
630 intel_tex_map_images(intel, intel_texture_object(texObj));
631 }
632 }
633
634 intel_map_unmap_buffers(intel, GL_TRUE);
635 }
636
637 /**
638 * Called when done softare rendering. Unmap the buffers we mapped in
639 * the above function.
640 */
641 void
642 intelSpanRenderFinish(GLcontext * ctx)
643 {
644 struct intel_context *intel = intel_context(ctx);
645 GLuint i;
646
647 _swrast_flush(ctx);
648
649 /* Now unmap the framebuffer:
650 */
651 #if 0
652 intel_region_unmap(intel, intel->front_region);
653 intel_region_unmap(intel, intel->back_region);
654 intel_region_unmap(intel, intel->depth_region);
655 #endif
656
657 for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
658 if (ctx->Texture.Unit[i]._ReallyEnabled) {
659 struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
660 intel_tex_unmap_images(intel, intel_texture_object(texObj));
661 }
662 }
663
664 intel_map_unmap_buffers(intel, GL_FALSE);
665
666 UNLOCK_HARDWARE(intel);
667 }
668
669
670 void
671 intelInitSpanFuncs(GLcontext * ctx)
672 {
673 struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
674 swdd->SpanRenderStart = intelSpanRenderStart;
675 swdd->SpanRenderFinish = intelSpanRenderFinish;
676 }
677
678
679 /**
680 * Plug in appropriate span read/write functions for the given renderbuffer.
681 * These are used for the software fallbacks.
682 */
683 void
684 intel_set_span_functions(struct gl_renderbuffer *rb, enum tiling_mode tiling)
685 {
686 if (rb->_ActualFormat == GL_RGB5) {
687 /* 565 RGB */
688 switch (tiling) {
689 case INTEL_TILE_NONE:
690 default:
691 intelInitPointers_RGB565(rb);
692 break;
693 case INTEL_TILE_X:
694 intel_XTile_InitPointers_RGB565(rb);
695 break;
696 case INTEL_TILE_Y:
697 intel_YTile_InitPointers_RGB565(rb);
698 break;
699 }
700 }
701 else if (rb->_ActualFormat == GL_RGBA8) {
702 /* 8888 RGBA */
703 switch (tiling) {
704 case INTEL_TILE_NONE:
705 default:
706 intelInitPointers_ARGB8888(rb);
707 break;
708 case INTEL_TILE_X:
709 intel_XTile_InitPointers_ARGB8888(rb);
710 break;
711 case INTEL_TILE_Y:
712 intel_YTile_InitPointers_ARGB8888(rb);
713 break;
714 }
715 }
716 else if (rb->_ActualFormat == GL_DEPTH_COMPONENT16) {
717 switch (tiling) {
718 case INTEL_TILE_NONE:
719 default:
720 intelInitDepthPointers_z16(rb);
721 break;
722 case INTEL_TILE_X:
723 intel_XTile_InitDepthPointers_z16(rb);
724 break;
725 case INTEL_TILE_Y:
726 intel_YTile_InitDepthPointers_z16(rb);
727 break;
728 }
729 }
730 else if (rb->_ActualFormat == GL_DEPTH_COMPONENT24 || /* XXX FBO remove */
731 rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
732 switch (tiling) {
733 case INTEL_TILE_NONE:
734 default:
735 intelInitDepthPointers_z24_s8(rb);
736 break;
737 case INTEL_TILE_X:
738 intel_XTile_InitDepthPointers_z24_s8(rb);
739 break;
740 case INTEL_TILE_Y:
741 intel_YTile_InitDepthPointers_z24_s8(rb);
742 break;
743 }
744 }
745 else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) {
746 switch (tiling) {
747 case INTEL_TILE_NONE:
748 default:
749 intelInitStencilPointers_z24_s8(rb);
750 break;
751 case INTEL_TILE_X:
752 intel_XTile_InitStencilPointers_z24_s8(rb);
753 break;
754 case INTEL_TILE_Y:
755 intel_YTile_InitStencilPointers_z24_s8(rb);
756 break;
757 }
758 }
759 else {
760 _mesa_problem(NULL,
761 "Unexpected _ActualFormat in intelSetSpanFunctions");
762 }
763 }