src/mesa/drivers/dri/intel/intel_span.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "main/glheader.h"
  29 #include "main/macros.h"
  30 #include "main/mtypes.h"
  31 #include "main/colormac.h"
  32
  33 #include "intel_buffers.h"
  34 #include "intel_fbo.h"
  35 #include "intel_screen.h"
  36 #include "intel_span.h"
  37 #include "intel_regions.h"
  38 #include "intel_tex.h"
  39
  40 #include "swrast/swrast.h"
  41
  42 static void
  43 intel_set_span_functions(struct intel_context *intel,
  44                          struct gl_renderbuffer *rb);
  45
  46 #define SPAN_CACHE_SIZE         4096
  47
  48 static void
  49 get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
  50 {
  51    if (irb->span_cache == NULL) {
  52       irb->span_cache = _mesa_malloc(SPAN_CACHE_SIZE);
  53       irb->span_cache_offset = -1;
  54    }
  55
  56    if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
  57       irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
  58       dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
  59                          SPAN_CACHE_SIZE, irb->span_cache);
  60    }
  61 }
  62
  63 static void
  64 clear_span_cache(struct intel_renderbuffer *irb)
  65 {
  66    irb->span_cache_offset = -1;
  67 }
  68
  69 static uint32_t
  70 pread_32(struct intel_renderbuffer *irb, uint32_t offset)
  71 {
  72    get_span_cache(irb, offset);
  73
  74    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  75 }
  76
  77 static uint32_t
  78 pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
  79 {
  80    get_span_cache(irb, offset);
  81
  82    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
  83       0xff000000;
  84 }
  85
  86 static uint16_t
  87 pread_16(struct intel_renderbuffer *irb, uint32_t offset)
  88 {
  89    get_span_cache(irb, offset);
  90
  91    return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  92 }
  93
  94 static uint8_t
  95 pread_8(struct intel_renderbuffer *irb, uint32_t offset)
  96 {
  97    get_span_cache(irb, offset);
  98
  99    return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
 100 }
 101
 102 static void
 103 pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 104 {
 105    clear_span_cache(irb);
 106
 107    dri_bo_subdata(irb->region->buffer, offset, 4, &val);
 108 }
 109
 110 static void
 111 pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 112 {
 113    clear_span_cache(irb);
 114
 115    dri_bo_subdata(irb->region->buffer, offset, 3, &val);
 116 }
 117
 118 static void
 119 pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
 120 {
 121    clear_span_cache(irb);
 122
 123    dri_bo_subdata(irb->region->buffer, offset, 2, &val);
 124 }
 125
 126 static void
 127 pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
 128 {
 129    clear_span_cache(irb);
 130
 131    dri_bo_subdata(irb->region->buffer, offset, 1, &val);
 132 }
 133
 134 static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
 135                                 int x, int y)
 136 {
 137         return (y * irb->region->pitch + x) * irb->region->cpp;
 138 }
 139
 140 /*
 141  * Deal with tiled surfaces
 142  */
 143
 144 static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
 145                                int x, int y)
 146 {
 147         int     tile_stride;
 148         int     xbyte;
 149         int     x_tile_off, y_tile_off;
 150         int     x_tile_number, y_tile_number;
 151         int     tile_off, tile_base;
 152
 153         x += irb->region->draw_x;
 154         y += irb->region->draw_y;
 155
 156         tile_stride = (irb->region->pitch * irb->region->cpp) << 3;
 157
 158         xbyte = x * irb->region->cpp;
 159
 160         x_tile_off = xbyte & 0x1ff;
 161         y_tile_off = y & 7;
 162
 163         x_tile_number = xbyte >> 9;
 164         y_tile_number = y >> 3;
 165
 166         tile_off = (y_tile_off << 9) + x_tile_off;
 167
 168         switch (irb->region->bit_6_swizzle) {
 169         case I915_BIT_6_SWIZZLE_NONE:
 170            break;
 171         case I915_BIT_6_SWIZZLE_9:
 172            tile_off ^= ((tile_off >> 3) & 64);
 173            break;
 174         case I915_BIT_6_SWIZZLE_9_10:
 175            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 176            break;
 177         case I915_BIT_6_SWIZZLE_9_11:
 178            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 179            break;
 180         case I915_BIT_6_SWIZZLE_9_10_11:
 181            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 182               ((tile_off >> 5) & 64);
 183            break;
 184         default:
 185            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 186                    irb->region->bit_6_swizzle);
 187            exit(1);
 188         }
 189
 190         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 191
 192 #if 0
 193         printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
 194                x, y, tile_off, tile_base,
 195                tile_off + tile_base,
 196                irb->region->pitch, tile_stride);
 197 #endif
 198
 199         return tile_base + tile_off;
 200 }
 201
 202 static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 203                                int x, int y)
 204 {
 205         int     tile_stride;
 206         int     xbyte;
 207         int     x_tile_off, y_tile_off;
 208         int     x_tile_number, y_tile_number;
 209         int     tile_off, tile_base;
 210
 211         x += irb->region->draw_x;
 212         y += irb->region->draw_y;
 213
 214         tile_stride = (irb->region->pitch * irb->region->cpp) << 5;
 215
 216         xbyte = x * irb->region->cpp;
 217
 218         x_tile_off = xbyte & 0x7f;
 219         y_tile_off = y & 0x1f;
 220
 221         x_tile_number = xbyte >> 7;
 222         y_tile_number = y >> 5;
 223
 224         tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
 225            (x_tile_off & 0xf);
 226
 227         switch (irb->region->bit_6_swizzle) {
 228         case I915_BIT_6_SWIZZLE_NONE:
 229            break;
 230         case I915_BIT_6_SWIZZLE_9:
 231            tile_off ^= ((tile_off >> 3) & 64);
 232            break;
 233         case I915_BIT_6_SWIZZLE_9_10:
 234            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 235            break;
 236         case I915_BIT_6_SWIZZLE_9_11:
 237            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 238            break;
 239         case I915_BIT_6_SWIZZLE_9_10_11:
 240            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 241               ((tile_off >> 5) & 64);
 242            break;
 243         default:
 244            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 245                    irb->region->bit_6_swizzle);
 246            exit(1);
 247         }
 248
 249         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 250
 251         return tile_base + tile_off;
 252 }
 253
 254 /*
 255   break intelWriteRGBASpan_ARGB8888
 256 */
 257
 258 #undef DBG
 259 #define DBG 0
 260
 261 #define LOCAL_VARS                                                      \
 262    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 263    const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1;                 \
 264    const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
 265    int minx = 0, miny = 0;                                              \
 266    int maxx = ctx->DrawBuffer->Width;                                   \
 267    int maxy = ctx->DrawBuffer->Height;                                  \
 268    int pitch = irb->region->pitch * irb->region->cpp;                   \
 269    void *buf = irb->region->buffer->virtual;                            \
 270    GLuint p;                                                            \
 271    (void) p;                                                            \
 272    (void)buf; (void)pitch; /* unused for non-gttmap. */                 \
 273
 274 #define HW_CLIPLOOP()
 275 #define HW_ENDCLIPLOOP()
 276
 277 #define Y_FLIP(_y) ((_y) * yScale + yBias)
 278
 279 #define HW_LOCK()
 280
 281 #define HW_UNLOCK()
 282
 283 /* Convenience macros to avoid typing the swizzle argument over and over */
 284 #define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X), (_Y))
 285 #define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X), (_Y))
 286 #define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X), (_Y))
 287
 288 /* r5g6b5 color span and pixel functions */
 289 #define INTEL_PIXEL_FMT GL_RGB
 290 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
 291 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 292 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 293 #define INTEL_TAG(x) x##_RGB565
 294 #include "intel_spantmp.h"
 295
 296 /* a4r4g4b4 color span and pixel functions */
 297 #define INTEL_PIXEL_FMT GL_BGRA
 298 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
 299 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 300 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 301 #define INTEL_TAG(x) x##_ARGB4444
 302 #include "intel_spantmp.h"
 303
 304 /* a1r5g5b5 color span and pixel functions */
 305 #define INTEL_PIXEL_FMT GL_BGRA
 306 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
 307 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 308 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 309 #define INTEL_TAG(x) x##_ARGB1555
 310 #include "intel_spantmp.h"
 311
 312 /* a8r8g8b8 color span and pixel functions */
 313 #define INTEL_PIXEL_FMT GL_BGRA
 314 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 315 #define INTEL_READ_VALUE(offset) pread_32(irb, offset)
 316 #define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v)
 317 #define INTEL_TAG(x) x##_ARGB8888
 318 #include "intel_spantmp.h"
 319
 320 /* x8r8g8b8 color span and pixel functions */
 321 #define INTEL_PIXEL_FMT GL_BGR
 322 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 323 #define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
 324 #define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
 325 #define INTEL_TAG(x) x##_xRGB8888
 326 #include "intel_spantmp.h"
 327
 328 #define LOCAL_DEPTH_VARS                                                \
 329    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 330    const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1;                 \
 331    const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
 332    int minx = 0, miny = 0;                                              \
 333    int maxx = ctx->DrawBuffer->Width;                                   \
 334    int maxy = ctx->DrawBuffer->Height;                                  \
 335    int pitch = irb->region->pitch * irb->region->cpp;                   \
 336    void *buf = irb->region->buffer->virtual;                            \
 337    (void)buf; (void)pitch; /* unused for non-gttmap. */                 \
 338
 339 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
 340
 341 /* z16 depthbuffer functions. */
 342 #define INTEL_VALUE_TYPE GLushort
 343 #define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d)
 344 #define INTEL_READ_DEPTH(offset) pread_16(irb, offset)
 345 #define INTEL_TAG(name) name##_z16
 346 #include "intel_depthtmp.h"
 347
 348 /* z24x8 depthbuffer functions. */
 349 #define INTEL_VALUE_TYPE GLuint
 350 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
 351 #define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
 352 #define INTEL_TAG(name) name##_z24_x8
 353 #include "intel_depthtmp.h"
 354
 355
 356 /**
 357  ** 8-bit stencil function (XXX FBO: This is obsolete)
 358  **/
 359 /* XXX */
 360 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
 361 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
 362 #define TAG(x) intel_gttmap_##x##_z24_s8
 363 #include "stenciltmp.h"
 364
 365 /**
 366  ** 8-bit stencil function (XXX FBO: This is obsolete)
 367  **/
 368 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
 369 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
 370 #define TAG(x) intel##x##_z24_s8
 371 #include "stenciltmp.h"
 372
 373 /**
 374  ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
 375  **/
 376 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, X_TILE(_x, _y) + 3, d)
 377 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, X_TILE(_x, _y) + 3);
 378 #define TAG(x) intel_XTile_##x##_z24_s8
 379 #include "stenciltmp.h"
 380
 381 /**
 382  ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
 383  **/
 384 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, Y_TILE(_x, _y) + 3, d)
 385 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, Y_TILE(_x, _y) + 3)
 386 #define TAG(x) intel_YTile_##x##_z24_s8
 387 #include "stenciltmp.h"
 388
 389 void
 390 intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
 391 {
 392    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 393
 394    if (irb == NULL || irb->region == NULL)
 395       return;
 396
 397    if (intel->intelScreen->kernel_exec_fencing)
 398       drm_intel_gem_bo_map_gtt(irb->region->buffer);
 399
 400    intel_set_span_functions(intel, rb);
 401 }
 402
 403 void
 404 intel_renderbuffer_unmap(struct intel_context *intel,
 405                          struct gl_renderbuffer *rb)
 406 {
 407    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 408
 409    if (irb == NULL || irb->region == NULL)
 410       return;
 411
 412    if (intel->intelScreen->kernel_exec_fencing)
 413       drm_intel_gem_bo_unmap_gtt(irb->region->buffer);
 414    else
 415       clear_span_cache(irb);
 416
 417    rb->GetRow = NULL;
 418    rb->PutRow = NULL;
 419 }
 420
 421 /**
 422  * Map or unmap all the renderbuffers which we may need during
 423  * software rendering.
 424  * XXX in the future, we could probably convey extra information to
 425  * reduce the number of mappings needed.  I.e. if doing a glReadPixels
 426  * from the depth buffer, we really only need one mapping.
 427  *
 428  * XXX Rewrite this function someday.
 429  * We can probably just loop over all the renderbuffer attachments,
 430  * map/unmap all of them, and not worry about the _ColorDrawBuffers
 431  * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
 432  */
 433 static void
 434 intel_map_unmap_framebuffer(struct intel_context *intel,
 435                             struct gl_framebuffer *fb,
 436                             GLboolean map)
 437 {
 438    GLuint i;
 439
 440    /* color draw buffers */
 441    for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
 442       if (map)
 443          intel_renderbuffer_map(intel, fb->_ColorDrawBuffers[i]);
 444       else
 445          intel_renderbuffer_unmap(intel, fb->_ColorDrawBuffers[i]);
 446    }
 447
 448    /* color read buffer */
 449    if (map)
 450       intel_renderbuffer_map(intel, fb->_ColorReadBuffer);
 451    else
 452       intel_renderbuffer_unmap(intel, fb->_ColorReadBuffer);
 453
 454    /* check for render to textures */
 455    for (i = 0; i < BUFFER_COUNT; i++) {
 456       struct gl_renderbuffer_attachment *att =
 457          fb->Attachment + i;
 458       struct gl_texture_object *tex = att->Texture;
 459       if (tex) {
 460          /* render to texture */
 461          ASSERT(att->Renderbuffer);
 462          if (map)
 463             intel_tex_map_images(intel, intel_texture_object(tex));
 464          else
 465             intel_tex_unmap_images(intel, intel_texture_object(tex));
 466       }
 467    }
 468
 469    /* depth buffer (Note wrapper!) */
 470    if (fb->_DepthBuffer) {
 471       if (map)
 472          intel_renderbuffer_map(intel, fb->_DepthBuffer->Wrapped);
 473       else
 474          intel_renderbuffer_unmap(intel, fb->_DepthBuffer->Wrapped);
 475    }
 476
 477    /* stencil buffer (Note wrapper!) */
 478    if (fb->_StencilBuffer) {
 479       if (map)
 480          intel_renderbuffer_map(intel, fb->_StencilBuffer->Wrapped);
 481       else
 482          intel_renderbuffer_unmap(intel, fb->_StencilBuffer->Wrapped);
 483    }
 484
 485    intel_check_front_buffer_rendering(intel);
 486 }
 487
 488 /**
 489  * Prepare for software rendering.  Map current read/draw framebuffers'
 490  * renderbuffes and all currently bound texture objects.
 491  *
 492  * Old note: Moved locking out to get reasonable span performance.
 493  */
 494 void
 495 intelSpanRenderStart(GLcontext * ctx)
 496 {
 497    struct intel_context *intel = intel_context(ctx);
 498    GLuint i;
 499
 500    intelFlush(&intel->ctx);
 501
 502    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 503       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 504          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 505          intel_tex_map_images(intel, intel_texture_object(texObj));
 506       }
 507    }
 508
 509    intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_TRUE);
 510    if (ctx->ReadBuffer != ctx->DrawBuffer)
 511       intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_TRUE);
 512 }
 513
 514 /**
 515  * Called when done software rendering.  Unmap the buffers we mapped in
 516  * the above function.
 517  */
 518 void
 519 intelSpanRenderFinish(GLcontext * ctx)
 520 {
 521    struct intel_context *intel = intel_context(ctx);
 522    GLuint i;
 523
 524    _swrast_flush(ctx);
 525
 526    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 527       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 528          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 529          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 530       }
 531    }
 532
 533    intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_FALSE);
 534    if (ctx->ReadBuffer != ctx->DrawBuffer)
 535       intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_FALSE);
 536 }
 537
 538
 539 void
 540 intelInitSpanFuncs(GLcontext * ctx)
 541 {
 542    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 543    swdd->SpanRenderStart = intelSpanRenderStart;
 544    swdd->SpanRenderFinish = intelSpanRenderFinish;
 545 }
 546
 547 void
 548 intel_map_vertex_shader_textures(GLcontext *ctx)
 549 {
 550    struct intel_context *intel = intel_context(ctx);
 551    int i;
 552
 553    if (ctx->VertexProgram._Current == NULL)
 554       return;
 555
 556    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 557       if (ctx->Texture.Unit[i]._ReallyEnabled &&
 558           ctx->VertexProgram._Current->Base.TexturesUsed[i] != 0) {
 559          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 560
 561          intel_tex_map_images(intel, intel_texture_object(texObj));
 562       }
 563    }
 564 }
 565
 566 void
 567 intel_unmap_vertex_shader_textures(GLcontext *ctx)
 568 {
 569    struct intel_context *intel = intel_context(ctx);
 570    int i;
 571
 572    if (ctx->VertexProgram._Current == NULL)
 573       return;
 574
 575    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 576       if (ctx->Texture.Unit[i]._ReallyEnabled &&
 577           ctx->VertexProgram._Current->Base.TexturesUsed[i] != 0) {
 578          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 579
 580          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 581       }
 582    }
 583 }
 584
 585 /**
 586  * Plug in appropriate span read/write functions for the given renderbuffer.
 587  * These are used for the software fallbacks.
 588  */
 589 static void
 590 intel_set_span_functions(struct intel_context *intel,
 591                          struct gl_renderbuffer *rb)
 592 {
 593    struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
 594    uint32_t tiling = irb->region->tiling;
 595
 596    if (intel->intelScreen->kernel_exec_fencing) {
 597       switch (irb->Base.Format) {
 598       case MESA_FORMAT_RGB565:
 599          intel_gttmap_InitPointers_RGB565(rb);
 600          break;
 601       case MESA_FORMAT_ARGB4444:
 602          intel_gttmap_InitPointers_ARGB4444(rb);
 603          break;
 604       case MESA_FORMAT_ARGB1555:
 605          intel_gttmap_InitPointers_ARGB1555(rb);
 606          break;
 607       case MESA_FORMAT_XRGB8888:
 608          intel_gttmap_InitPointers_xRGB8888(rb);
 609          break;
 610       case MESA_FORMAT_ARGB8888:
 611          intel_gttmap_InitPointers_ARGB8888(rb);
 612          break;
 613       case MESA_FORMAT_Z16:
 614          intel_gttmap_InitDepthPointers_z16(rb);
 615          break;
 616       case MESA_FORMAT_X8_Z24:
 617          intel_gttmap_InitDepthPointers_z24_x8(rb);
 618          break;
 619       case MESA_FORMAT_S8_Z24:
 620          /* There are a few different ways SW asks us to access the S8Z24 data:
 621           * Z24 depth-only depth reads
 622           * S8Z24 depth reads
 623           * S8Z24 stencil reads.
 624           */
 625          if (rb->Format == MESA_FORMAT_S8_Z24) {
 626             intel_gttmap_InitDepthPointers_z24_x8(rb);
 627          } else if (rb->Format == MESA_FORMAT_S8) {
 628             intel_gttmap_InitStencilPointers_z24_s8(rb);
 629          }
 630          break;
 631       default:
 632          _mesa_problem(NULL,
 633                        "Unexpected MesaFormat %d in intelSetSpanFunctions",
 634                        irb->Base.Format);
 635          break;
 636       }
 637       return;
 638    }
 639
 640    /* If in GEM mode, we need to do the tile address swizzling ourselves,
 641     * instead of the fence registers handling it.
 642     */
 643    switch (irb->Base.Format) {
 644    case MESA_FORMAT_RGB565:
 645       switch (tiling) {
 646       case I915_TILING_NONE:
 647       default:
 648          intelInitPointers_RGB565(rb);
 649          break;
 650       case I915_TILING_X:
 651          intel_XTile_InitPointers_RGB565(rb);
 652          break;
 653       case I915_TILING_Y:
 654          intel_YTile_InitPointers_RGB565(rb);
 655          break;
 656       }
 657       break;
 658    case MESA_FORMAT_ARGB4444:
 659       switch (tiling) {
 660       case I915_TILING_NONE:
 661       default:
 662          intelInitPointers_ARGB4444(rb);
 663          break;
 664       case I915_TILING_X:
 665          intel_XTile_InitPointers_ARGB4444(rb);
 666          break;
 667       case I915_TILING_Y:
 668          intel_YTile_InitPointers_ARGB4444(rb);
 669          break;
 670       }
 671       break;
 672    case MESA_FORMAT_ARGB1555:
 673       switch (tiling) {
 674       case I915_TILING_NONE:
 675       default:
 676          intelInitPointers_ARGB1555(rb);
 677          break;
 678       case I915_TILING_X:
 679          intel_XTile_InitPointers_ARGB1555(rb);
 680          break;
 681       case I915_TILING_Y:
 682          intel_YTile_InitPointers_ARGB1555(rb);
 683          break;
 684       }
 685       break;
 686    case MESA_FORMAT_XRGB8888:
 687       switch (tiling) {
 688       case I915_TILING_NONE:
 689       default:
 690          intelInitPointers_xRGB8888(rb);
 691          break;
 692       case I915_TILING_X:
 693          intel_XTile_InitPointers_xRGB8888(rb);
 694          break;
 695       case I915_TILING_Y:
 696          intel_YTile_InitPointers_xRGB8888(rb);
 697          break;
 698       }
 699       break;
 700    case MESA_FORMAT_ARGB8888:
 701       /* 8888 RGBA */
 702       switch (tiling) {
 703       case I915_TILING_NONE:
 704       default:
 705          intelInitPointers_ARGB8888(rb);
 706          break;
 707       case I915_TILING_X:
 708          intel_XTile_InitPointers_ARGB8888(rb);
 709          break;
 710       case I915_TILING_Y:
 711          intel_YTile_InitPointers_ARGB8888(rb);
 712          break;
 713       }
 714       break;
 715    case MESA_FORMAT_Z16:
 716       switch (tiling) {
 717       case I915_TILING_NONE:
 718       default:
 719          intelInitDepthPointers_z16(rb);
 720          break;
 721       case I915_TILING_X:
 722          intel_XTile_InitDepthPointers_z16(rb);
 723          break;
 724       case I915_TILING_Y:
 725          intel_YTile_InitDepthPointers_z16(rb);
 726          break;
 727       }
 728       break;
 729    case MESA_FORMAT_X8_Z24:
 730    case MESA_FORMAT_S8_Z24:
 731       /* There are a few different ways SW asks us to access the S8Z24 data:
 732        * Z24 depth-only depth reads
 733        * S8Z24 depth reads
 734        * S8Z24 stencil reads.
 735        */
 736       if (rb->Format == MESA_FORMAT_S8_Z24) {
 737          switch (tiling) {
 738          case I915_TILING_NONE:
 739          default:
 740             intelInitDepthPointers_z24_x8(rb);
 741             break;
 742          case I915_TILING_X:
 743             intel_XTile_InitDepthPointers_z24_x8(rb);
 744             break;
 745          case I915_TILING_Y:
 746             intel_YTile_InitDepthPointers_z24_x8(rb);
 747             break;
 748          }
 749       } else if (rb->Format == MESA_FORMAT_S8) {
 750          switch (tiling) {
 751          case I915_TILING_NONE:
 752          default:
 753             intelInitStencilPointers_z24_s8(rb);
 754             break;
 755          case I915_TILING_X:
 756             intel_XTile_InitStencilPointers_z24_s8(rb);
 757             break;
 758          case I915_TILING_Y:
 759             intel_YTile_InitStencilPointers_z24_s8(rb);
 760             break;
 761          }
 762       } else {
 763          _mesa_problem(NULL,
 764                        "Unexpected ActualFormat in intelSetSpanFunctions");
 765       }
 766       break;
 767    default:
 768       _mesa_problem(NULL,
 769                     "Unexpected MesaFormat in intelSetSpanFunctions");
 770       break;
 771    }
 772 }