src/mesa/drivers/dri/intel/intel_span.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "main/glheader.h"
  29 #include "main/macros.h"
  30 #include "main/mtypes.h"
  31 #include "main/colormac.h"
  32
  33 #include "intel_buffers.h"
  34 #include "intel_fbo.h"
  35 #include "intel_screen.h"
  36 #include "intel_span.h"
  37 #include "intel_regions.h"
  38 #include "intel_tex.h"
  39
  40 #include "swrast/swrast.h"
  41
  42 static void
  43 intel_set_span_functions(struct intel_context *intel,
  44                          struct gl_renderbuffer *rb);
  45
  46 #define SPAN_CACHE_SIZE         4096
  47
  48 static void
  49 get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
  50 {
  51    if (irb->span_cache == NULL) {
  52       irb->span_cache = _mesa_malloc(SPAN_CACHE_SIZE);
  53       irb->span_cache_offset = -1;
  54    }
  55
  56    if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
  57       irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
  58       dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
  59                          SPAN_CACHE_SIZE, irb->span_cache);
  60    }
  61 }
  62
  63 static void
  64 clear_span_cache(struct intel_renderbuffer *irb)
  65 {
  66    irb->span_cache_offset = -1;
  67 }
  68
  69 static uint32_t
  70 pread_32(struct intel_renderbuffer *irb, uint32_t offset)
  71 {
  72    get_span_cache(irb, offset);
  73
  74    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  75 }
  76
  77 static uint32_t
  78 pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
  79 {
  80    get_span_cache(irb, offset);
  81
  82    return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
  83       0xff000000;
  84 }
  85
  86 static uint16_t
  87 pread_16(struct intel_renderbuffer *irb, uint32_t offset)
  88 {
  89    get_span_cache(irb, offset);
  90
  91    return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
  92 }
  93
  94 static uint8_t
  95 pread_8(struct intel_renderbuffer *irb, uint32_t offset)
  96 {
  97    get_span_cache(irb, offset);
  98
  99    return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
 100 }
 101
 102 static void
 103 pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 104 {
 105    clear_span_cache(irb);
 106
 107    dri_bo_subdata(irb->region->buffer, offset, 4, &val);
 108 }
 109
 110 static void
 111 pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
 112 {
 113    clear_span_cache(irb);
 114
 115    dri_bo_subdata(irb->region->buffer, offset, 3, &val);
 116 }
 117
 118 static void
 119 pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
 120 {
 121    clear_span_cache(irb);
 122
 123    dri_bo_subdata(irb->region->buffer, offset, 2, &val);
 124 }
 125
 126 static void
 127 pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
 128 {
 129    clear_span_cache(irb);
 130
 131    dri_bo_subdata(irb->region->buffer, offset, 1, &val);
 132 }
 133
 134 static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
 135                                 int x, int y)
 136 {
 137         return (y * irb->region->pitch + x) * irb->region->cpp;
 138 }
 139
 140 /*
 141  * Deal with tiled surfaces
 142  */
 143
 144 static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
 145                                int x, int y)
 146 {
 147         int     tile_stride;
 148         int     xbyte;
 149         int     x_tile_off, y_tile_off;
 150         int     x_tile_number, y_tile_number;
 151         int     tile_off, tile_base;
 152
 153         x += irb->region->draw_x;
 154         y += irb->region->draw_y;
 155
 156         tile_stride = (irb->region->pitch * irb->region->cpp) << 3;
 157
 158         xbyte = x * irb->region->cpp;
 159
 160         x_tile_off = xbyte & 0x1ff;
 161         y_tile_off = y & 7;
 162
 163         x_tile_number = xbyte >> 9;
 164         y_tile_number = y >> 3;
 165
 166         tile_off = (y_tile_off << 9) + x_tile_off;
 167
 168         switch (irb->region->bit_6_swizzle) {
 169         case I915_BIT_6_SWIZZLE_NONE:
 170            break;
 171         case I915_BIT_6_SWIZZLE_9:
 172            tile_off ^= ((tile_off >> 3) & 64);
 173            break;
 174         case I915_BIT_6_SWIZZLE_9_10:
 175            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 176            break;
 177         case I915_BIT_6_SWIZZLE_9_11:
 178            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 179            break;
 180         case I915_BIT_6_SWIZZLE_9_10_11:
 181            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 182               ((tile_off >> 5) & 64);
 183            break;
 184         default:
 185            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 186                    irb->region->bit_6_swizzle);
 187            exit(1);
 188         }
 189
 190         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 191
 192 #if 0
 193         printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
 194                x, y, tile_off, tile_base,
 195                tile_off + tile_base,
 196                irb->region->pitch, tile_stride);
 197 #endif
 198
 199         return tile_base + tile_off;
 200 }
 201
 202 static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 203                                int x, int y)
 204 {
 205         int     tile_stride;
 206         int     xbyte;
 207         int     x_tile_off, y_tile_off;
 208         int     x_tile_number, y_tile_number;
 209         int     tile_off, tile_base;
 210
 211         x += irb->region->draw_x;
 212         y += irb->region->draw_y;
 213
 214         tile_stride = (irb->region->pitch * irb->region->cpp) << 5;
 215
 216         xbyte = x * irb->region->cpp;
 217
 218         x_tile_off = xbyte & 0x7f;
 219         y_tile_off = y & 0x1f;
 220
 221         x_tile_number = xbyte >> 7;
 222         y_tile_number = y >> 5;
 223
 224         tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
 225            (x_tile_off & 0xf);
 226
 227         switch (irb->region->bit_6_swizzle) {
 228         case I915_BIT_6_SWIZZLE_NONE:
 229            break;
 230         case I915_BIT_6_SWIZZLE_9:
 231            tile_off ^= ((tile_off >> 3) & 64);
 232            break;
 233         case I915_BIT_6_SWIZZLE_9_10:
 234            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
 235            break;
 236         case I915_BIT_6_SWIZZLE_9_11:
 237            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
 238            break;
 239         case I915_BIT_6_SWIZZLE_9_10_11:
 240            tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
 241               ((tile_off >> 5) & 64);
 242            break;
 243         default:
 244            fprintf(stderr, "Unknown tile swizzling mode %d\n",
 245                    irb->region->bit_6_swizzle);
 246            exit(1);
 247         }
 248
 249         tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 250
 251         return tile_base + tile_off;
 252 }
 253
 254 /*
 255   break intelWriteRGBASpan_ARGB8888
 256 */
 257
 258 #undef DBG
 259 #define DBG 0
 260
 261 #define LOCAL_VARS                                                      \
 262    struct intel_context *intel = intel_context(ctx);                    \
 263    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 264    const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1;                 \
 265    const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
 266    unsigned int num_cliprects;                                          \
 267    struct drm_clip_rect *cliprects;                                     \
 268    int x_off, y_off;                                                    \
 269    int pitch = irb->region->pitch * irb->region->cpp;                   \
 270    void *buf = irb->region->buffer->virtual;                            \
 271    GLuint p;                                                            \
 272    (void) p;                                                            \
 273    (void)buf; (void)pitch; /* unused for non-gttmap. */                 \
 274    intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
 275
 276 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
 277  * the cliprect info from the context, not the driDrawable.
 278  * Move this into spantmp2.h someday.
 279  */
 280 #define HW_CLIPLOOP()                                                   \
 281    do {                                                                 \
 282       int _nc = num_cliprects;                                          \
 283       while ( _nc-- ) {                                                 \
 284          int minx = cliprects[_nc].x1 - x_off;                          \
 285          int miny = cliprects[_nc].y1 - y_off;                          \
 286          int maxx = cliprects[_nc].x2 - x_off;                          \
 287          int maxy = cliprects[_nc].y2 - y_off;
 288
 289 #if 0
 290       }}
 291 #endif
 292
 293 #define Y_FLIP(_y) ((_y) * yScale + yBias)
 294
 295 /* XXX with GEM, these need to tell the kernel */
 296 #define HW_LOCK()
 297
 298 #define HW_UNLOCK()
 299
 300 /* Convenience macros to avoid typing the swizzle argument over and over */
 301 #define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 302 #define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 303 #define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
 304
 305 /* r5g6b5 color span and pixel functions */
 306 #define INTEL_PIXEL_FMT GL_RGB
 307 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
 308 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 309 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 310 #define INTEL_TAG(x) x##_RGB565
 311 #include "intel_spantmp.h"
 312
 313 /* a4r4g4b4 color span and pixel functions */
 314 #define INTEL_PIXEL_FMT GL_BGRA
 315 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
 316 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 317 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 318 #define INTEL_TAG(x) x##_ARGB4444
 319 #include "intel_spantmp.h"
 320
 321 /* a1r5g5b5 color span and pixel functions */
 322 #define INTEL_PIXEL_FMT GL_BGRA
 323 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
 324 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
 325 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
 326 #define INTEL_TAG(x) x##_ARGB1555
 327 #include "intel_spantmp.h"
 328
 329 /* a8r8g8b8 color span and pixel functions */
 330 #define INTEL_PIXEL_FMT GL_BGRA
 331 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 332 #define INTEL_READ_VALUE(offset) pread_32(irb, offset)
 333 #define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v)
 334 #define INTEL_TAG(x) x##_ARGB8888
 335 #include "intel_spantmp.h"
 336
 337 /* x8r8g8b8 color span and pixel functions */
 338 #define INTEL_PIXEL_FMT GL_BGRA
 339 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 340 #define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
 341 #define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
 342 #define INTEL_TAG(x) x##_xRGB8888
 343 #include "intel_spantmp.h"
 344
 345 #define LOCAL_DEPTH_VARS                                                \
 346    struct intel_context *intel = intel_context(ctx);                    \
 347    struct intel_renderbuffer *irb = intel_renderbuffer(rb);             \
 348    const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1;                 \
 349    const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
 350    unsigned int num_cliprects;                                          \
 351    struct drm_clip_rect *cliprects;                                     \
 352    int x_off, y_off;                                                    \
 353    int pitch = irb->region->pitch * irb->region->cpp;                   \
 354    void *buf = irb->region->buffer->virtual;                            \
 355    (void)buf; (void)pitch; /* unused for non-gttmap. */                 \
 356    intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
 357
 358
 359 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
 360
 361 /* z16 depthbuffer functions. */
 362 #define INTEL_VALUE_TYPE GLushort
 363 #define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d)
 364 #define INTEL_READ_DEPTH(offset) pread_16(irb, offset)
 365 #define INTEL_TAG(name) name##_z16
 366 #include "intel_depthtmp.h"
 367
 368 /* z24x8 depthbuffer functions. */
 369 #define INTEL_VALUE_TYPE GLuint
 370 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
 371 #define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
 372 #define INTEL_TAG(name) name##_z24_x8
 373 #include "intel_depthtmp.h"
 374
 375
 376 /**
 377  ** 8-bit stencil function (XXX FBO: This is obsolete)
 378  **/
 379 /* XXX */
 380 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
 381 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
 382 #define TAG(x) intel_gttmap_##x##_z24_s8
 383 #include "stenciltmp.h"
 384
 385 /**
 386  ** 8-bit stencil function (XXX FBO: This is obsolete)
 387  **/
 388 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
 389 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
 390 #define TAG(x) intel##x##_z24_s8
 391 #include "stenciltmp.h"
 392
 393 /**
 394  ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
 395  **/
 396 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, X_TILE(_x, _y) + 3, d)
 397 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, X_TILE(_x, _y) + 3);
 398 #define TAG(x) intel_XTile_##x##_z24_s8
 399 #include "stenciltmp.h"
 400
 401 /**
 402  ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
 403  **/
 404 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, Y_TILE(_x, _y) + 3, d)
 405 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, Y_TILE(_x, _y) + 3)
 406 #define TAG(x) intel_YTile_##x##_z24_s8
 407 #include "stenciltmp.h"
 408
 409 void
 410 intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
 411 {
 412    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 413
 414    if (irb == NULL || irb->region == NULL)
 415       return;
 416
 417    if (intel->intelScreen->kernel_exec_fencing)
 418       drm_intel_gem_bo_map_gtt(irb->region->buffer);
 419
 420    intel_set_span_functions(intel, rb);
 421 }
 422
 423 void
 424 intel_renderbuffer_unmap(struct intel_context *intel,
 425                          struct gl_renderbuffer *rb)
 426 {
 427    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 428
 429    if (irb == NULL || irb->region == NULL)
 430       return;
 431
 432    if (intel->intelScreen->kernel_exec_fencing)
 433       drm_intel_gem_bo_unmap_gtt(irb->region->buffer);
 434    else
 435       clear_span_cache(irb);
 436
 437    rb->GetRow = NULL;
 438    rb->PutRow = NULL;
 439 }
 440
 441 /**
 442  * Map or unmap all the renderbuffers which we may need during
 443  * software rendering.
 444  * XXX in the future, we could probably convey extra information to
 445  * reduce the number of mappings needed.  I.e. if doing a glReadPixels
 446  * from the depth buffer, we really only need one mapping.
 447  *
 448  * XXX Rewrite this function someday.
 449  * We can probably just loop over all the renderbuffer attachments,
 450  * map/unmap all of them, and not worry about the _ColorDrawBuffers
 451  * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
 452  */
 453 static void
 454 intel_map_unmap_framebuffer(struct intel_context *intel,
 455                             struct gl_framebuffer *fb,
 456                             GLboolean map)
 457 {
 458    GLuint i;
 459
 460    /* color draw buffers */
 461    for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
 462       if (map)
 463          intel_renderbuffer_map(intel, fb->_ColorDrawBuffers[i]);
 464       else
 465          intel_renderbuffer_unmap(intel, fb->_ColorDrawBuffers[i]);
 466    }
 467
 468    /* color read buffer */
 469    if (map)
 470       intel_renderbuffer_map(intel, fb->_ColorReadBuffer);
 471    else
 472       intel_renderbuffer_unmap(intel, fb->_ColorReadBuffer);
 473
 474    /* check for render to textures */
 475    for (i = 0; i < BUFFER_COUNT; i++) {
 476       struct gl_renderbuffer_attachment *att =
 477          fb->Attachment + i;
 478       struct gl_texture_object *tex = att->Texture;
 479       if (tex) {
 480          /* render to texture */
 481          ASSERT(att->Renderbuffer);
 482          if (map)
 483             intel_tex_map_images(intel, intel_texture_object(tex));
 484          else
 485             intel_tex_unmap_images(intel, intel_texture_object(tex));
 486       }
 487    }
 488
 489    /* depth buffer (Note wrapper!) */
 490    if (fb->_DepthBuffer) {
 491       if (map)
 492          intel_renderbuffer_map(intel, fb->_DepthBuffer->Wrapped);
 493       else
 494          intel_renderbuffer_unmap(intel, fb->_DepthBuffer->Wrapped);
 495    }
 496
 497    /* stencil buffer (Note wrapper!) */
 498    if (fb->_StencilBuffer) {
 499       if (map)
 500          intel_renderbuffer_map(intel, fb->_StencilBuffer->Wrapped);
 501       else
 502          intel_renderbuffer_unmap(intel, fb->_StencilBuffer->Wrapped);
 503    }
 504
 505    intel_check_front_buffer_rendering(intel);
 506 }
 507
 508 /**
 509  * Prepare for software rendering.  Map current read/draw framebuffers'
 510  * renderbuffes and all currently bound texture objects.
 511  *
 512  * Old note: Moved locking out to get reasonable span performance.
 513  */
 514 void
 515 intelSpanRenderStart(GLcontext * ctx)
 516 {
 517    struct intel_context *intel = intel_context(ctx);
 518    GLuint i;
 519
 520    intelFlush(&intel->ctx);
 521    LOCK_HARDWARE(intel);
 522
 523    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 524       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 525          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 526          intel_tex_map_images(intel, intel_texture_object(texObj));
 527       }
 528    }
 529
 530    intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_TRUE);
 531    if (ctx->ReadBuffer != ctx->DrawBuffer)
 532       intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_TRUE);
 533 }
 534
 535 /**
 536  * Called when done software rendering.  Unmap the buffers we mapped in
 537  * the above function.
 538  */
 539 void
 540 intelSpanRenderFinish(GLcontext * ctx)
 541 {
 542    struct intel_context *intel = intel_context(ctx);
 543    GLuint i;
 544
 545    _swrast_flush(ctx);
 546
 547    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 548       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 549          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 550          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 551       }
 552    }
 553
 554    intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_FALSE);
 555    if (ctx->ReadBuffer != ctx->DrawBuffer)
 556       intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_FALSE);
 557
 558    UNLOCK_HARDWARE(intel);
 559 }
 560
 561
 562 void
 563 intelInitSpanFuncs(GLcontext * ctx)
 564 {
 565    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 566    swdd->SpanRenderStart = intelSpanRenderStart;
 567    swdd->SpanRenderFinish = intelSpanRenderFinish;
 568 }
 569
 570 void
 571 intel_map_vertex_shader_textures(GLcontext *ctx)
 572 {
 573    struct intel_context *intel = intel_context(ctx);
 574    int i;
 575
 576    if (ctx->VertexProgram._Current == NULL)
 577       return;
 578
 579    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 580       if (ctx->Texture.Unit[i]._ReallyEnabled &&
 581           ctx->VertexProgram._Current->Base.TexturesUsed[i] != 0) {
 582          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 583
 584          intel_tex_map_images(intel, intel_texture_object(texObj));
 585       }
 586    }
 587 }
 588
 589 void
 590 intel_unmap_vertex_shader_textures(GLcontext *ctx)
 591 {
 592    struct intel_context *intel = intel_context(ctx);
 593    int i;
 594
 595    if (ctx->VertexProgram._Current == NULL)
 596       return;
 597
 598    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
 599       if (ctx->Texture.Unit[i]._ReallyEnabled &&
 600           ctx->VertexProgram._Current->Base.TexturesUsed[i] != 0) {
 601          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
 602
 603          intel_tex_unmap_images(intel, intel_texture_object(texObj));
 604       }
 605    }
 606 }
 607
 608 /**
 609  * Plug in appropriate span read/write functions for the given renderbuffer.
 610  * These are used for the software fallbacks.
 611  */
 612 static void
 613 intel_set_span_functions(struct intel_context *intel,
 614                          struct gl_renderbuffer *rb)
 615 {
 616    struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
 617    uint32_t tiling;
 618
 619    /* If in GEM mode, we need to do the tile address swizzling ourselves,
 620     * instead of the fence registers handling it.
 621     */
 622    if (intel->ttm)
 623       tiling = irb->region->tiling;
 624    else
 625       tiling = I915_TILING_NONE;
 626
 627    if (intel->intelScreen->kernel_exec_fencing) {
 628       switch (irb->texformat) {
 629       case MESA_FORMAT_RGB565:
 630          intel_gttmap_InitPointers_RGB565(rb);
 631          break;
 632       case MESA_FORMAT_ARGB4444:
 633          intel_gttmap_InitPointers_ARGB4444(rb);
 634          break;
 635       case MESA_FORMAT_ARGB1555:
 636          intel_gttmap_InitPointers_ARGB1555(rb);
 637          break;
 638       case MESA_FORMAT_XRGB8888:
 639          intel_gttmap_InitPointers_xRGB8888(rb);
 640          break;
 641       case MESA_FORMAT_ARGB8888:
 642          if (rb->_BaseFormat == GL_RGB) {
 643             /* XXX remove this code someday when we enable XRGB surfaces */
 644             /* 8888 RGBx */
 645             intel_gttmap_InitPointers_xRGB8888(rb);
 646          } else {
 647             intel_gttmap_InitPointers_ARGB8888(rb);
 648          }
 649          break;
 650       case MESA_FORMAT_Z16:
 651          intel_gttmap_InitDepthPointers_z16(rb);
 652          break;
 653       case MESA_FORMAT_X8_Z24:
 654          intel_gttmap_InitDepthPointers_z24_x8(rb);
 655          break;
 656       case MESA_FORMAT_S8_Z24:
 657          /* There are a few different ways SW asks us to access the S8Z24 data:
 658           * Z24 depth-only depth reads
 659           * S8Z24 depth reads
 660           * S8Z24 stencil reads.
 661           */
 662          if (rb->Format == MESA_FORMAT_S8_Z24) {
 663             intel_gttmap_InitDepthPointers_z24_x8(rb);
 664          } else if (rb->Format == MESA_FORMAT_S8) {
 665             intel_gttmap_InitStencilPointers_z24_s8(rb);
 666          }
 667          break;
 668       default:
 669          _mesa_problem(NULL,
 670                        "Unexpected MesaFormat %d in intelSetSpanFunctions",
 671                        irb->texformat);
 672          break;
 673       }
 674       return;
 675    }
 676
 677    switch (irb->texformat) {
 678    case MESA_FORMAT_RGB565:
 679       switch (tiling) {
 680       case I915_TILING_NONE:
 681       default:
 682          intelInitPointers_RGB565(rb);
 683          break;
 684       case I915_TILING_X:
 685          intel_XTile_InitPointers_RGB565(rb);
 686          break;
 687       case I915_TILING_Y:
 688          intel_YTile_InitPointers_RGB565(rb);
 689          break;
 690       }
 691       break;
 692    case MESA_FORMAT_ARGB4444:
 693       switch (tiling) {
 694       case I915_TILING_NONE:
 695       default:
 696          intelInitPointers_ARGB4444(rb);
 697          break;
 698       case I915_TILING_X:
 699          intel_XTile_InitPointers_ARGB4444(rb);
 700          break;
 701       case I915_TILING_Y:
 702          intel_YTile_InitPointers_ARGB4444(rb);
 703          break;
 704       }
 705       break;
 706    case MESA_FORMAT_ARGB1555:
 707       switch (tiling) {
 708       case I915_TILING_NONE:
 709       default:
 710          intelInitPointers_ARGB1555(rb);
 711          break;
 712       case I915_TILING_X:
 713          intel_XTile_InitPointers_ARGB1555(rb);
 714          break;
 715       case I915_TILING_Y:
 716          intel_YTile_InitPointers_ARGB1555(rb);
 717          break;
 718       }
 719       break;
 720    case MESA_FORMAT_XRGB8888:
 721       switch (tiling) {
 722       case I915_TILING_NONE:
 723       default:
 724          intelInitPointers_xRGB8888(rb);
 725          break;
 726       case I915_TILING_X:
 727          intel_XTile_InitPointers_xRGB8888(rb);
 728          break;
 729       case I915_TILING_Y:
 730          intel_YTile_InitPointers_xRGB8888(rb);
 731          break;
 732       }
 733       break;
 734    case MESA_FORMAT_ARGB8888:
 735       if (rb->_BaseFormat == GL_RGB) {
 736          /* XXX remove this code someday when we enable XRGB surfaces */
 737          /* 8888 RGBx */
 738          switch (tiling) {
 739          case I915_TILING_NONE:
 740          default:
 741             intelInitPointers_xRGB8888(rb);
 742             break;
 743          case I915_TILING_X:
 744             intel_XTile_InitPointers_xRGB8888(rb);
 745             break;
 746          case I915_TILING_Y:
 747             intel_YTile_InitPointers_xRGB8888(rb);
 748             break;
 749          }
 750       } else {
 751          /* 8888 RGBA */
 752          switch (tiling) {
 753          case I915_TILING_NONE:
 754          default:
 755             intelInitPointers_ARGB8888(rb);
 756             break;
 757          case I915_TILING_X:
 758             intel_XTile_InitPointers_ARGB8888(rb);
 759             break;
 760          case I915_TILING_Y:
 761             intel_YTile_InitPointers_ARGB8888(rb);
 762             break;
 763          }
 764       }
 765       break;
 766    case MESA_FORMAT_Z16:
 767       switch (tiling) {
 768       case I915_TILING_NONE:
 769       default:
 770          intelInitDepthPointers_z16(rb);
 771          break;
 772       case I915_TILING_X:
 773          intel_XTile_InitDepthPointers_z16(rb);
 774          break;
 775       case I915_TILING_Y:
 776          intel_YTile_InitDepthPointers_z16(rb);
 777          break;
 778       }
 779       break;
 780    case MESA_FORMAT_X8_Z24:
 781    case MESA_FORMAT_S8_Z24:
 782       /* There are a few different ways SW asks us to access the S8Z24 data:
 783        * Z24 depth-only depth reads
 784        * S8Z24 depth reads
 785        * S8Z24 stencil reads.
 786        */
 787       if (rb->Format == MESA_FORMAT_S8_Z24) {
 788          switch (tiling) {
 789          case I915_TILING_NONE:
 790          default:
 791             intelInitDepthPointers_z24_x8(rb);
 792             break;
 793          case I915_TILING_X:
 794             intel_XTile_InitDepthPointers_z24_x8(rb);
 795             break;
 796          case I915_TILING_Y:
 797             intel_YTile_InitDepthPointers_z24_x8(rb);
 798             break;
 799          }
 800       } else if (rb->Format == MESA_FORMAT_S8) {
 801          switch (tiling) {
 802          case I915_TILING_NONE:
 803          default:
 804             intelInitStencilPointers_z24_s8(rb);
 805             break;
 806          case I915_TILING_X:
 807             intel_XTile_InitStencilPointers_z24_s8(rb);
 808             break;
 809          case I915_TILING_Y:
 810             intel_YTile_InitStencilPointers_z24_s8(rb);
 811             break;
 812          }
 813       } else {
 814          _mesa_problem(NULL,
 815                        "Unexpected ActualFormat in intelSetSpanFunctions");
 816       }
 817       break;
 818    default:
 819       _mesa_problem(NULL,
 820                     "Unexpected MesaFormat in intelSetSpanFunctions");
 821       break;
 822    }
 823 }