1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "main/glheader.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "main/colormac.h"
33 #include "intel_buffers.h"
34 #include "intel_fbo.h"
35 #include "intel_screen.h"
36 #include "intel_span.h"
37 #include "intel_regions.h"
38 #include "intel_tex.h"
40 #include "swrast/swrast.h"
43 intel_set_span_functions(struct intel_context
*intel
,
44 struct gl_renderbuffer
*rb
);
46 #define SPAN_CACHE_SIZE 4096
49 get_span_cache(struct intel_renderbuffer
*irb
, uint32_t offset
)
51 if (irb
->span_cache
== NULL
) {
52 irb
->span_cache
= _mesa_malloc(SPAN_CACHE_SIZE
);
53 irb
->span_cache_offset
= -1;
56 if ((offset
& ~(SPAN_CACHE_SIZE
- 1)) != irb
->span_cache_offset
) {
57 irb
->span_cache_offset
= offset
& ~(SPAN_CACHE_SIZE
- 1);
58 dri_bo_get_subdata(irb
->region
->buffer
, irb
->span_cache_offset
,
59 SPAN_CACHE_SIZE
, irb
->span_cache
);
64 clear_span_cache(struct intel_renderbuffer
*irb
)
66 irb
->span_cache_offset
= -1;
70 pread_32(struct intel_renderbuffer
*irb
, uint32_t offset
)
72 get_span_cache(irb
, offset
);
74 return *(uint32_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1)));
78 pread_xrgb8888(struct intel_renderbuffer
*irb
, uint32_t offset
)
80 get_span_cache(irb
, offset
);
82 return *(uint32_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1))) |
87 pread_16(struct intel_renderbuffer
*irb
, uint32_t offset
)
89 get_span_cache(irb
, offset
);
91 return *(uint16_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1)));
95 pread_8(struct intel_renderbuffer
*irb
, uint32_t offset
)
97 get_span_cache(irb
, offset
);
99 return *(uint8_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1)));
103 pwrite_32(struct intel_renderbuffer
*irb
, uint32_t offset
, uint32_t val
)
105 clear_span_cache(irb
);
107 dri_bo_subdata(irb
->region
->buffer
, offset
, 4, &val
);
111 pwrite_xrgb8888(struct intel_renderbuffer
*irb
, uint32_t offset
, uint32_t val
)
113 clear_span_cache(irb
);
115 dri_bo_subdata(irb
->region
->buffer
, offset
, 3, &val
);
119 pwrite_16(struct intel_renderbuffer
*irb
, uint32_t offset
, uint16_t val
)
121 clear_span_cache(irb
);
123 dri_bo_subdata(irb
->region
->buffer
, offset
, 2, &val
);
127 pwrite_8(struct intel_renderbuffer
*irb
, uint32_t offset
, uint8_t val
)
129 clear_span_cache(irb
);
131 dri_bo_subdata(irb
->region
->buffer
, offset
, 1, &val
);
134 static uint32_t no_tile_swizzle(struct intel_renderbuffer
*irb
,
137 return (y
* irb
->region
->pitch
+ x
) * irb
->region
->cpp
;
141 * Deal with tiled surfaces
144 static uint32_t x_tile_swizzle(struct intel_renderbuffer
*irb
,
149 int x_tile_off
, y_tile_off
;
150 int x_tile_number
, y_tile_number
;
151 int tile_off
, tile_base
;
153 x
+= irb
->region
->draw_x
;
154 y
+= irb
->region
->draw_y
;
156 tile_stride
= (irb
->region
->pitch
* irb
->region
->cpp
) << 3;
158 xbyte
= x
* irb
->region
->cpp
;
160 x_tile_off
= xbyte
& 0x1ff;
163 x_tile_number
= xbyte
>> 9;
164 y_tile_number
= y
>> 3;
166 tile_off
= (y_tile_off
<< 9) + x_tile_off
;
168 switch (irb
->region
->bit_6_swizzle
) {
169 case I915_BIT_6_SWIZZLE_NONE
:
171 case I915_BIT_6_SWIZZLE_9
:
172 tile_off
^= ((tile_off
>> 3) & 64);
174 case I915_BIT_6_SWIZZLE_9_10
:
175 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64);
177 case I915_BIT_6_SWIZZLE_9_11
:
178 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 5) & 64);
180 case I915_BIT_6_SWIZZLE_9_10_11
:
181 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64) ^
182 ((tile_off
>> 5) & 64);
185 fprintf(stderr
, "Unknown tile swizzling mode %d\n",
186 irb
->region
->bit_6_swizzle
);
190 tile_base
= (x_tile_number
<< 12) + y_tile_number
* tile_stride
;
193 printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
194 x
, y
, tile_off
, tile_base
,
195 tile_off
+ tile_base
,
196 irb
->region
->pitch
, tile_stride
);
199 return tile_base
+ tile_off
;
202 static uint32_t y_tile_swizzle(struct intel_renderbuffer
*irb
,
207 int x_tile_off
, y_tile_off
;
208 int x_tile_number
, y_tile_number
;
209 int tile_off
, tile_base
;
211 x
+= irb
->region
->draw_x
;
212 y
+= irb
->region
->draw_y
;
214 tile_stride
= (irb
->region
->pitch
* irb
->region
->cpp
) << 5;
216 xbyte
= x
* irb
->region
->cpp
;
218 x_tile_off
= xbyte
& 0x7f;
219 y_tile_off
= y
& 0x1f;
221 x_tile_number
= xbyte
>> 7;
222 y_tile_number
= y
>> 5;
224 tile_off
= ((x_tile_off
& ~0xf) << 5) + (y_tile_off
<< 4) +
227 switch (irb
->region
->bit_6_swizzle
) {
228 case I915_BIT_6_SWIZZLE_NONE
:
230 case I915_BIT_6_SWIZZLE_9
:
231 tile_off
^= ((tile_off
>> 3) & 64);
233 case I915_BIT_6_SWIZZLE_9_10
:
234 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64);
236 case I915_BIT_6_SWIZZLE_9_11
:
237 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 5) & 64);
239 case I915_BIT_6_SWIZZLE_9_10_11
:
240 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64) ^
241 ((tile_off
>> 5) & 64);
244 fprintf(stderr
, "Unknown tile swizzling mode %d\n",
245 irb
->region
->bit_6_swizzle
);
249 tile_base
= (x_tile_number
<< 12) + y_tile_number
* tile_stride
;
251 return tile_base
+ tile_off
;
255 break intelWriteRGBASpan_ARGB8888
262 struct intel_context *intel = intel_context(ctx); \
263 struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
264 const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \
265 const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
266 unsigned int num_cliprects; \
267 struct drm_clip_rect *cliprects; \
269 int pitch = irb->region->pitch * irb->region->cpp; \
270 void *buf = irb->region->buffer->virtual; \
273 (void)buf; (void)pitch; /* unused for non-gttmap. */ \
274 intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
276 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
277 * the cliprect info from the context, not the driDrawable.
278 * Move this into spantmp2.h someday.
280 #define HW_CLIPLOOP() \
282 int _nc = num_cliprects; \
284 int minx = cliprects[_nc].x1 - x_off; \
285 int miny = cliprects[_nc].y1 - y_off; \
286 int maxx = cliprects[_nc].x2 - x_off; \
287 int maxy = cliprects[_nc].y2 - y_off;
293 #define Y_FLIP(_y) ((_y) * yScale + yBias)
299 /* Convenience macros to avoid typing the swizzle argument over and over */
300 #define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
301 #define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
302 #define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
304 /* r5g6b5 color span and pixel functions */
305 #define INTEL_PIXEL_FMT GL_RGB
306 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
307 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
308 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
309 #define INTEL_TAG(x) x##_RGB565
310 #include "intel_spantmp.h"
312 /* a4r4g4b4 color span and pixel functions */
313 #define INTEL_PIXEL_FMT GL_BGRA
314 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
315 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
316 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
317 #define INTEL_TAG(x) x##_ARGB4444
318 #include "intel_spantmp.h"
320 /* a1r5g5b5 color span and pixel functions */
321 #define INTEL_PIXEL_FMT GL_BGRA
322 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
323 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
324 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
325 #define INTEL_TAG(x) x##_ARGB1555
326 #include "intel_spantmp.h"
328 /* a8r8g8b8 color span and pixel functions */
329 #define INTEL_PIXEL_FMT GL_BGRA
330 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
331 #define INTEL_READ_VALUE(offset) pread_32(irb, offset)
332 #define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v)
333 #define INTEL_TAG(x) x##_ARGB8888
334 #include "intel_spantmp.h"
336 /* x8r8g8b8 color span and pixel functions */
337 #define INTEL_PIXEL_FMT GL_BGR
338 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
339 #define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
340 #define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
341 #define INTEL_TAG(x) x##_xRGB8888
342 #include "intel_spantmp.h"
344 #define LOCAL_DEPTH_VARS \
345 struct intel_context *intel = intel_context(ctx); \
346 struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
347 const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \
348 const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
349 unsigned int num_cliprects; \
350 struct drm_clip_rect *cliprects; \
352 int pitch = irb->region->pitch * irb->region->cpp; \
353 void *buf = irb->region->buffer->virtual; \
354 (void)buf; (void)pitch; /* unused for non-gttmap. */ \
355 intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
358 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
360 /* z16 depthbuffer functions. */
361 #define INTEL_VALUE_TYPE GLushort
362 #define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d)
363 #define INTEL_READ_DEPTH(offset) pread_16(irb, offset)
364 #define INTEL_TAG(name) name##_z16
365 #include "intel_depthtmp.h"
367 /* z24x8 depthbuffer functions. */
368 #define INTEL_VALUE_TYPE GLuint
369 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
370 #define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
371 #define INTEL_TAG(name) name##_z24_x8
372 #include "intel_depthtmp.h"
376 ** 8-bit stencil function (XXX FBO: This is obsolete)
379 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
380 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
381 #define TAG(x) intel_gttmap_##x##_z24_s8
382 #include "stenciltmp.h"
385 ** 8-bit stencil function (XXX FBO: This is obsolete)
387 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
388 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
389 #define TAG(x) intel##x##_z24_s8
390 #include "stenciltmp.h"
393 ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
395 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, X_TILE(_x, _y) + 3, d)
396 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, X_TILE(_x, _y) + 3);
397 #define TAG(x) intel_XTile_##x##_z24_s8
398 #include "stenciltmp.h"
401 ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
403 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, Y_TILE(_x, _y) + 3, d)
404 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, Y_TILE(_x, _y) + 3)
405 #define TAG(x) intel_YTile_##x##_z24_s8
406 #include "stenciltmp.h"
409 intel_renderbuffer_map(struct intel_context
*intel
, struct gl_renderbuffer
*rb
)
411 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
413 if (irb
== NULL
|| irb
->region
== NULL
)
416 if (intel
->intelScreen
->kernel_exec_fencing
)
417 drm_intel_gem_bo_map_gtt(irb
->region
->buffer
);
419 intel_set_span_functions(intel
, rb
);
423 intel_renderbuffer_unmap(struct intel_context
*intel
,
424 struct gl_renderbuffer
*rb
)
426 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
428 if (irb
== NULL
|| irb
->region
== NULL
)
431 if (intel
->intelScreen
->kernel_exec_fencing
)
432 drm_intel_gem_bo_unmap_gtt(irb
->region
->buffer
);
434 clear_span_cache(irb
);
441 * Map or unmap all the renderbuffers which we may need during
442 * software rendering.
443 * XXX in the future, we could probably convey extra information to
444 * reduce the number of mappings needed. I.e. if doing a glReadPixels
445 * from the depth buffer, we really only need one mapping.
447 * XXX Rewrite this function someday.
448 * We can probably just loop over all the renderbuffer attachments,
449 * map/unmap all of them, and not worry about the _ColorDrawBuffers
450 * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
453 intel_map_unmap_framebuffer(struct intel_context
*intel
,
454 struct gl_framebuffer
*fb
,
459 /* color draw buffers */
460 for (i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
462 intel_renderbuffer_map(intel
, fb
->_ColorDrawBuffers
[i
]);
464 intel_renderbuffer_unmap(intel
, fb
->_ColorDrawBuffers
[i
]);
467 /* color read buffer */
469 intel_renderbuffer_map(intel
, fb
->_ColorReadBuffer
);
471 intel_renderbuffer_unmap(intel
, fb
->_ColorReadBuffer
);
473 /* check for render to textures */
474 for (i
= 0; i
< BUFFER_COUNT
; i
++) {
475 struct gl_renderbuffer_attachment
*att
=
477 struct gl_texture_object
*tex
= att
->Texture
;
479 /* render to texture */
480 ASSERT(att
->Renderbuffer
);
482 intel_tex_map_images(intel
, intel_texture_object(tex
));
484 intel_tex_unmap_images(intel
, intel_texture_object(tex
));
488 /* depth buffer (Note wrapper!) */
489 if (fb
->_DepthBuffer
) {
491 intel_renderbuffer_map(intel
, fb
->_DepthBuffer
->Wrapped
);
493 intel_renderbuffer_unmap(intel
, fb
->_DepthBuffer
->Wrapped
);
496 /* stencil buffer (Note wrapper!) */
497 if (fb
->_StencilBuffer
) {
499 intel_renderbuffer_map(intel
, fb
->_StencilBuffer
->Wrapped
);
501 intel_renderbuffer_unmap(intel
, fb
->_StencilBuffer
->Wrapped
);
504 intel_check_front_buffer_rendering(intel
);
508 * Prepare for software rendering. Map current read/draw framebuffers'
509 * renderbuffes and all currently bound texture objects.
511 * Old note: Moved locking out to get reasonable span performance.
514 intelSpanRenderStart(GLcontext
* ctx
)
516 struct intel_context
*intel
= intel_context(ctx
);
519 intelFlush(&intel
->ctx
);
521 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
522 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
523 struct gl_texture_object
*texObj
= ctx
->Texture
.Unit
[i
]._Current
;
524 intel_tex_map_images(intel
, intel_texture_object(texObj
));
528 intel_map_unmap_framebuffer(intel
, ctx
->DrawBuffer
, GL_TRUE
);
529 if (ctx
->ReadBuffer
!= ctx
->DrawBuffer
)
530 intel_map_unmap_framebuffer(intel
, ctx
->ReadBuffer
, GL_TRUE
);
534 * Called when done software rendering. Unmap the buffers we mapped in
535 * the above function.
538 intelSpanRenderFinish(GLcontext
* ctx
)
540 struct intel_context
*intel
= intel_context(ctx
);
545 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
546 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
547 struct gl_texture_object
*texObj
= ctx
->Texture
.Unit
[i
]._Current
;
548 intel_tex_unmap_images(intel
, intel_texture_object(texObj
));
552 intel_map_unmap_framebuffer(intel
, ctx
->DrawBuffer
, GL_FALSE
);
553 if (ctx
->ReadBuffer
!= ctx
->DrawBuffer
)
554 intel_map_unmap_framebuffer(intel
, ctx
->ReadBuffer
, GL_FALSE
);
559 intelInitSpanFuncs(GLcontext
* ctx
)
561 struct swrast_device_driver
*swdd
= _swrast_GetDeviceDriverReference(ctx
);
562 swdd
->SpanRenderStart
= intelSpanRenderStart
;
563 swdd
->SpanRenderFinish
= intelSpanRenderFinish
;
567 intel_map_vertex_shader_textures(GLcontext
*ctx
)
569 struct intel_context
*intel
= intel_context(ctx
);
572 if (ctx
->VertexProgram
._Current
== NULL
)
575 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
576 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
&&
577 ctx
->VertexProgram
._Current
->Base
.TexturesUsed
[i
] != 0) {
578 struct gl_texture_object
*texObj
= ctx
->Texture
.Unit
[i
]._Current
;
580 intel_tex_map_images(intel
, intel_texture_object(texObj
));
586 intel_unmap_vertex_shader_textures(GLcontext
*ctx
)
588 struct intel_context
*intel
= intel_context(ctx
);
591 if (ctx
->VertexProgram
._Current
== NULL
)
594 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
595 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
&&
596 ctx
->VertexProgram
._Current
->Base
.TexturesUsed
[i
] != 0) {
597 struct gl_texture_object
*texObj
= ctx
->Texture
.Unit
[i
]._Current
;
599 intel_tex_unmap_images(intel
, intel_texture_object(texObj
));
605 * Plug in appropriate span read/write functions for the given renderbuffer.
606 * These are used for the software fallbacks.
609 intel_set_span_functions(struct intel_context
*intel
,
610 struct gl_renderbuffer
*rb
)
612 struct intel_renderbuffer
*irb
= (struct intel_renderbuffer
*) rb
;
613 uint32_t tiling
= irb
->region
->tiling
;
615 if (intel
->intelScreen
->kernel_exec_fencing
) {
616 switch (irb
->Base
.Format
) {
617 case MESA_FORMAT_RGB565
:
618 intel_gttmap_InitPointers_RGB565(rb
);
620 case MESA_FORMAT_ARGB4444
:
621 intel_gttmap_InitPointers_ARGB4444(rb
);
623 case MESA_FORMAT_ARGB1555
:
624 intel_gttmap_InitPointers_ARGB1555(rb
);
626 case MESA_FORMAT_XRGB8888
:
627 intel_gttmap_InitPointers_xRGB8888(rb
);
629 case MESA_FORMAT_ARGB8888
:
630 intel_gttmap_InitPointers_ARGB8888(rb
);
632 case MESA_FORMAT_Z16
:
633 intel_gttmap_InitDepthPointers_z16(rb
);
635 case MESA_FORMAT_X8_Z24
:
636 intel_gttmap_InitDepthPointers_z24_x8(rb
);
638 case MESA_FORMAT_S8_Z24
:
639 /* There are a few different ways SW asks us to access the S8Z24 data:
640 * Z24 depth-only depth reads
642 * S8Z24 stencil reads.
644 if (rb
->Format
== MESA_FORMAT_S8_Z24
) {
645 intel_gttmap_InitDepthPointers_z24_x8(rb
);
646 } else if (rb
->Format
== MESA_FORMAT_S8
) {
647 intel_gttmap_InitStencilPointers_z24_s8(rb
);
652 "Unexpected MesaFormat %d in intelSetSpanFunctions",
659 /* If in GEM mode, we need to do the tile address swizzling ourselves,
660 * instead of the fence registers handling it.
662 switch (irb
->Base
.Format
) {
663 case MESA_FORMAT_RGB565
:
665 case I915_TILING_NONE
:
667 intelInitPointers_RGB565(rb
);
670 intel_XTile_InitPointers_RGB565(rb
);
673 intel_YTile_InitPointers_RGB565(rb
);
677 case MESA_FORMAT_ARGB4444
:
679 case I915_TILING_NONE
:
681 intelInitPointers_ARGB4444(rb
);
684 intel_XTile_InitPointers_ARGB4444(rb
);
687 intel_YTile_InitPointers_ARGB4444(rb
);
691 case MESA_FORMAT_ARGB1555
:
693 case I915_TILING_NONE
:
695 intelInitPointers_ARGB1555(rb
);
698 intel_XTile_InitPointers_ARGB1555(rb
);
701 intel_YTile_InitPointers_ARGB1555(rb
);
705 case MESA_FORMAT_XRGB8888
:
707 case I915_TILING_NONE
:
709 intelInitPointers_xRGB8888(rb
);
712 intel_XTile_InitPointers_xRGB8888(rb
);
715 intel_YTile_InitPointers_xRGB8888(rb
);
719 case MESA_FORMAT_ARGB8888
:
722 case I915_TILING_NONE
:
724 intelInitPointers_ARGB8888(rb
);
727 intel_XTile_InitPointers_ARGB8888(rb
);
730 intel_YTile_InitPointers_ARGB8888(rb
);
734 case MESA_FORMAT_Z16
:
736 case I915_TILING_NONE
:
738 intelInitDepthPointers_z16(rb
);
741 intel_XTile_InitDepthPointers_z16(rb
);
744 intel_YTile_InitDepthPointers_z16(rb
);
748 case MESA_FORMAT_X8_Z24
:
749 case MESA_FORMAT_S8_Z24
:
750 /* There are a few different ways SW asks us to access the S8Z24 data:
751 * Z24 depth-only depth reads
753 * S8Z24 stencil reads.
755 if (rb
->Format
== MESA_FORMAT_S8_Z24
) {
757 case I915_TILING_NONE
:
759 intelInitDepthPointers_z24_x8(rb
);
762 intel_XTile_InitDepthPointers_z24_x8(rb
);
765 intel_YTile_InitDepthPointers_z24_x8(rb
);
768 } else if (rb
->Format
== MESA_FORMAT_S8
) {
770 case I915_TILING_NONE
:
772 intelInitStencilPointers_z24_s8(rb
);
775 intel_XTile_InitStencilPointers_z24_s8(rb
);
778 intel_YTile_InitStencilPointers_z24_s8(rb
);
783 "Unexpected ActualFormat in intelSetSpanFunctions");
788 "Unexpected MesaFormat in intelSetSpanFunctions");