src/mesa/drivers/dri/intel/intel_tex_layout.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   *   Michel Dänzer <michel@tungstengraphics.com>
  31   */
  32
  33 #include "intel_mipmap_tree.h"
  34 #include "intel_tex_layout.h"
  35 #include "intel_context.h"
  36
  37 #include "main/image.h"
  38 #include "main/macros.h"
  39
  40 static unsigned int
  41 intel_horizontal_texture_alignment_unit(struct intel_context *intel,
  42                                        gl_format format)
  43 {
  44    /**
  45     * From the "Alignment Unit Size" section of various specs, namely:
  46     * - Gen3 Spec: "Memory Data Formats" Volume,         Section 1.20.1.4
  47     * - i965 and G45 PRMs:             Volume 1,         Section 6.17.3.4.
  48     * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
  49     * - BSpec (for Ivybridge and slight variations in separate stencil)
  50     *
  51     * +----------------------------------------------------------------------+
  52     * |                                        | alignment unit width  ("i") |
  53     * | Surface Property                       |-----------------------------|
  54     * |                                        | 915 | 965 | ILK | SNB | IVB |
  55     * +----------------------------------------------------------------------+
  56     * | YUV 4:2:2 format                       |  8  |  4  |  4  |  4  |  4  |
  57     * | BC1-5 compressed format (DXTn/S3TC)    |  4  |  4  |  4  |  4  |  4  |
  58     * | FXT1  compressed format                |  8  |  8  |  8  |  8  |  8  |
  59     * | Depth Buffer (16-bit)                  |  4  |  4  |  4  |  4  |  8  |
  60     * | Depth Buffer (other)                   |  4  |  4  |  4  |  4  |  4  |
  61     * | Separate Stencil Buffer                | N/A | N/A |  8  |  8  |  8  |
  62     * | All Others                             |  4  |  4  |  4  |  4  |  4  |
  63     * +----------------------------------------------------------------------+
  64     *
  65     * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
  66     * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
  67     */
  68     if (_mesa_is_format_compressed(format)) {
  69        /* The hardware alignment requirements for compressed textures
  70         * happen to match the block boundaries.
  71         */
  72       unsigned int i, j;
  73       _mesa_get_format_block_size(format, &i, &j);
  74       return i;
  75     }
  76
  77    if (format == MESA_FORMAT_S8)
  78       return 8;
  79
  80    /* The depth alignment requirements in the table above are for rendering to
  81     * depth miplevels using the LOD control fields.  We don't use LOD control
  82     * fields, and instead use page offsets plus intra-tile x/y offsets, which
  83     * require that the low 3 bits are zero.  To reduce the number of x/y
  84     * offset workaround blits we do, align the X to 8, which depth texturing
  85     * can handle (sadly, it can't handle 8 in the Y direction).
  86     */
  87    if (intel->gen >= 7 &&
  88        _mesa_get_format_base_format(format) == GL_DEPTH_COMPONENT)
  89       return 8;
  90
  91    return 4;
  92 }
  93
  94 static unsigned int
  95 intel_vertical_texture_alignment_unit(struct intel_context *intel,
  96                                      gl_format format)
  97 {
  98    /**
  99     * From the "Alignment Unit Size" section of various specs, namely:
 100     * - Gen3 Spec: "Memory Data Formats" Volume,         Section 1.20.1.4
 101     * - i965 and G45 PRMs:             Volume 1,         Section 6.17.3.4.
 102     * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
 103     * - BSpec (for Ivybridge and slight variations in separate stencil)
 104     *
 105     * +----------------------------------------------------------------------+
 106     * |                                        | alignment unit height ("j") |
 107     * | Surface Property                       |-----------------------------|
 108     * |                                        | 915 | 965 | ILK | SNB | IVB |
 109     * +----------------------------------------------------------------------+
 110     * | BC1-5 compressed format (DXTn/S3TC)    |  4  |  4  |  4  |  4  |  4  |
 111     * | FXT1  compressed format                |  4  |  4  |  4  |  4  |  4  |
 112     * | Depth Buffer                           |  2  |  2  |  2  |  4  |  4  |
 113     * | Separate Stencil Buffer                | N/A | N/A | N/A |  4  |  8  |
 114     * | Multisampled (4x or 8x) render target  | N/A | N/A | N/A |  4  |  4  |
 115     * | All Others                             |  2  |  2  |  2  |  2  |  2  |
 116     * +----------------------------------------------------------------------+
 117     *
 118     * On SNB+, non-special cases can be overridden by setting the SURFACE_STATE
 119     * "Surface Vertical Alignment" field to VALIGN_2 or VALIGN_4.
 120     *
 121     * We currently don't support multisampling.
 122     */
 123    if (_mesa_is_format_compressed(format))
 124       return 4;
 125
 126    if (format == MESA_FORMAT_S8)
 127       return intel->gen >= 7 ? 8 : 4;
 128
 129    GLenum base_format = _mesa_get_format_base_format(format);
 130
 131    if (intel->gen >= 6 &&
 132        (base_format == GL_DEPTH_COMPONENT ||
 133         base_format == GL_DEPTH_STENCIL)) {
 134       return 4;
 135    }
 136
 137    return 2;
 138 }
 139
 140 void
 141 intel_get_texture_alignment_unit(struct intel_context *intel,
 142                                  gl_format format,
 143                                  unsigned int *w, unsigned int *h)
 144 {
 145    *w = intel_horizontal_texture_alignment_unit(intel, format);
 146    *h = intel_vertical_texture_alignment_unit(intel, format);
 147 }
 148
 149 void i945_miptree_layout_2d(struct intel_mipmap_tree *mt)
 150 {
 151    GLuint level;
 152    GLuint x = 0;
 153    GLuint y = 0;
 154    GLuint width = mt->physical_width0;
 155    GLuint height = mt->physical_height0;
 156    GLuint depth = mt->physical_depth0; /* number of array layers. */
 157
 158    mt->total_width = mt->physical_width0;
 159
 160    if (mt->compressed) {
 161        mt->total_width = ALIGN(mt->physical_width0, mt->align_w);
 162    }
 163
 164    /* May need to adjust width to accomodate the placement of
 165     * the 2nd mipmap.  This occurs when the alignment
 166     * constraints of mipmap placement push the right edge of the
 167     * 2nd mipmap out past the width of its parent.
 168     */
 169    if (mt->first_level != mt->last_level) {
 170        GLuint mip1_width;
 171
 172        if (mt->compressed) {
 173           mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
 174              ALIGN(minify(mt->physical_width0, 2), mt->align_w);
 175        } else {
 176           mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
 177              minify(mt->physical_width0, 2);
 178        }
 179
 180        if (mip1_width > mt->total_width) {
 181            mt->total_width = mip1_width;
 182        }
 183    }
 184
 185    mt->total_height = 0;
 186
 187    for ( level = mt->first_level ; level <= mt->last_level ; level++ ) {
 188       GLuint img_height;
 189
 190       intel_miptree_set_level_info(mt, level, x, y, width,
 191                                    height, depth);
 192
 193       img_height = ALIGN(height, mt->align_h);
 194       if (mt->compressed)
 195          img_height /= mt->align_h;
 196
 197       /* Because the images are packed better, the final offset
 198        * might not be the maximal one:
 199        */
 200       mt->total_height = MAX2(mt->total_height, y + img_height);
 201
 202       /* Layout_below: step right after second mipmap.
 203        */
 204       if (level == mt->first_level + 1) {
 205          x += ALIGN(width, mt->align_w);
 206       }
 207       else {
 208          y += img_height;
 209       }
 210
 211       width  = minify(width, 1);
 212       height = minify(height, 1);
 213    }
 214 }