src/mesa/drivers/dri/intel_winsys/intel_batchbuffer.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <errno.h>
  29 #include "intel_batchbuffer.h"
  30 #include "intel_context.h"
  31 #include "intel_screen.h"
  32 #include "intel_reg.h"
  33 #include "drm.h"
  34
  35 /* Relocations in kernel space:
  36  *    - pass dma buffer seperately
  37  *    - memory manager knows how to patch
  38  *    - pass list of dependent buffers
  39  *    - pass relocation list
  40  *
  41  * Either:
  42  *    - get back an offset for buffer to fire
  43  *    - memory manager knows how to fire buffer
  44  *
  45  * Really want the buffer to be AGP and pinned.
  46  *
  47  */
  48
  49 /* Cliprect fence: The highest fence protecting a dma buffer
  50  * containing explicit cliprect information.  Like the old drawable
  51  * lock but irq-driven.  X server must wait for this fence to expire
  52  * before changing cliprects [and then doing sw rendering?].  For
  53  * other dma buffers, the scheduler will grab current cliprect info
  54  * and mix into buffer.  X server must hold the lock while changing
  55  * cliprects???  Make per-drawable.  Need cliprects in shared memory
  56  * -- beats storing them with every cmd buffer in the queue.
  57  *
  58  * ==> X server must wait for this fence to expire before touching the
  59  * framebuffer with new cliprects.
  60  *
  61  * ==> Cliprect-dependent buffers associated with a
  62  * cliprect-timestamp.  All of the buffers associated with a timestamp
  63  * must go to hardware before any buffer with a newer timestamp.
  64  *
  65  * ==> Dma should be queued per-drawable for correct X/GL
  66  * synchronization.  Or can fences be used for this?
  67  *
  68  * Applies to: Blit operations, metaops, X server operations -- X
  69  * server automatically waits on its own dma to complete before
  70  * modifying cliprects ???
  71  */
  72
  73 static void
  74 intel_dump_batchbuffer(uint offset, uint * ptr, uint count)
  75 {
  76    int i;
  77    printf("\n\n\nSTART BATCH (%d dwords):\n", count / 4);
  78    for (i = 0; i < count / 4; i += 1)
  79       printf("\t0x%08x\n", ptr[i]);
  80    printf("END BATCH\n\n\n");
  81 }
  82
  83
  84 void
  85 intel_batchbuffer_reset(struct intel_batchbuffer *batch)
  86 {
  87    int i;
  88
  89    if (batch->map) {
  90       driBOUnmap(batch->buffer);
  91       batch->map = NULL;
  92    }
  93
  94    /*
  95     * Get a new, free batchbuffer.
  96     */
  97    batch->size =  BATCH_SZ;
  98    driBOData(batch->buffer, batch->size, NULL, 0);
  99
 100    driBOResetList(&batch->list);
 101
 102    /*
 103     * Unreference buffers previously on the relocation list.
 104     */
 105    for (i = 0; i < batch->nr_relocs; i++) {
 106       struct buffer_reloc *r = &batch->reloc[i];
 107       driBOUnReference(r->buf);
 108    }
 109
 110    batch->list_count = 0;
 111    batch->nr_relocs = 0;
 112    batch->flags = 0;
 113
 114    /*
 115     * We don't refcount the batchbuffer itself since we can't destroy it
 116     * while it's on the list.
 117     */
 118
 119    driBOAddListItem(&batch->list, batch->buffer,
 120                     DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_EXE,
 121                     DRM_BO_MASK_MEM | DRM_BO_FLAG_EXE);
 122
 123
 124    batch->map = driBOMap(batch->buffer, DRM_BO_FLAG_WRITE, 0);
 125    batch->ptr = batch->map;
 126 }
 127
 128
 129 /*======================================================================
 130  * Public functions
 131  */
 132 struct intel_batchbuffer *
 133 intel_batchbuffer_alloc(struct intel_context *intel)
 134 {
 135    struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
 136
 137    batch->intel = intel;
 138
 139    driGenBuffers(intel->intelScreen->batchPool, "batchbuffer", 1,
 140                  &batch->buffer, 4096,
 141                  DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_EXE, 0);
 142    batch->last_fence = NULL;
 143    driBOCreateList(20, &batch->list);
 144    intel_batchbuffer_reset(batch);
 145    return batch;
 146 }
 147
 148
 149 void
 150 intel_batchbuffer_free(struct intel_batchbuffer *batch)
 151 {
 152    if (batch->last_fence) {
 153       driFenceFinish(batch->last_fence,
 154                      DRM_FENCE_TYPE_EXE | DRM_I915_FENCE_TYPE_RW,
 155                      GL_FALSE);
 156       driFenceUnReference(batch->last_fence);
 157       batch->last_fence = NULL;
 158    }
 159    if (batch->map) {
 160       driBOUnmap(batch->buffer);
 161       batch->map = NULL;
 162    }
 163    driBOUnReference(batch->buffer);
 164    batch->buffer = NULL;
 165    free(batch);
 166 }
 167
 168
 169 static void
 170 intel_batch_ioctl(struct intel_context *intel,
 171                   uint start_offset, uint used, boolean allow_unlock)
 172 {
 173    drmI830BatchBuffer batch;
 174
 175    batch.start = start_offset;
 176    batch.used = used;
 177    batch.cliprects = NULL; /* unused */
 178    batch.num_cliprects = 0;
 179    batch.DR1 = 0;
 180    batch.DR4 = 0; /* still need this ? */
 181
 182    DBG(IOCTL, "%s: 0x%x..0x%x DR4: %x cliprects: %d\n",
 183        __FUNCTION__,
 184        batch.start,
 185        batch.start + batch.used * 4, batch.DR4, batch.num_cliprects);
 186
 187    if (drmCommandWrite(intel->driFd, DRM_I830_BATCHBUFFER, &batch,
 188                        sizeof(batch))) {
 189       printf("DRM_I830_BATCHBUFFER: %d\n", -errno);
 190       UNLOCK_HARDWARE(intel);
 191       exit(1);
 192    }
 193 }
 194
 195
 196 /* TODO: Push this whole function into bufmgr.
 197  */
 198 static void
 199 do_flush_locked(struct intel_batchbuffer *batch,
 200                 uint used, boolean allow_unlock)
 201 {
 202    uint *ptr;
 203    uint i, fenceFlags;
 204    struct _DriFenceObject *fo;
 205
 206    driBOValidateList(batch->intel->driFd, &batch->list);
 207
 208    /* Apply the relocations.  This nasty map indicates to me that the
 209     * whole task should be done internally by the memory manager, and
 210     * that dma buffers probably need to be pinned within agp space.
 211     */
 212    ptr = (uint *) driBOMap(batch->buffer, DRM_BO_FLAG_WRITE,
 213                              DRM_BO_HINT_ALLOW_UNFENCED_MAP);
 214
 215    for (i = 0; i < batch->nr_relocs; i++) {
 216       struct buffer_reloc *r = &batch->reloc[i];
 217
 218       ptr[r->offset / 4] = driBOOffset(r->buf) + r->delta;
 219    }
 220
 221    if (0)
 222       intel_dump_batchbuffer(0, ptr, used);
 223
 224    driBOUnmap(batch->buffer);
 225    batch->map = NULL;
 226
 227    intel_batch_ioctl(batch->intel,
 228                      driBOOffset(batch->buffer),
 229                      used, allow_unlock);
 230
 231    /*
 232     * Kernel fencing. The flags tells the kernel that we've
 233     * programmed an MI_FLUSH.
 234     */
 235    fenceFlags = DRM_I915_FENCE_FLAG_FLUSHED;
 236    fo = driFenceBuffers(batch->intel->driFd, "Batch fence", fenceFlags);
 237
 238    /*
 239     * User space fencing.
 240     */
 241    driBOFence(batch->buffer, fo);
 242
 243    if (driFenceType(fo) == DRM_FENCE_TYPE_EXE) {
 244      /*
 245       * Oops. We only validated a batch buffer. This means we
 246       * didn't do any proper rendering. Discard this fence object.
 247       */
 248       driFenceUnReference(fo);
 249    }
 250    else {
 251       driFenceUnReference(batch->last_fence);
 252       batch->last_fence = fo;
 253       for (i = 0; i < batch->nr_relocs; i++) {
 254         struct buffer_reloc *r = &batch->reloc[i];
 255         driBOFence(r->buf, fo);
 256       }
 257    }
 258 }
 259
 260
 261 struct _DriFenceObject *
 262 intel_batchbuffer_flush(struct intel_batchbuffer *batch)
 263 {
 264    struct intel_context *intel = batch->intel;
 265    uint used = batch->ptr - batch->map;
 266    const boolean was_locked = intel->locked;
 267
 268    if (used == 0)
 269       return batch->last_fence;
 270
 271 #define MI_FLUSH ((0 << 29) | (4 << 23))
 272
 273    /* Add the MI_BATCH_BUFFER_END.  Always add an MI_FLUSH - this is a
 274     * performance drain that we would like to avoid.
 275     */
 276    if (used & 4) {
 277       ((int *) batch->ptr)[0] = MI_FLUSH;
 278       ((int *) batch->ptr)[1] = 0;
 279       ((int *) batch->ptr)[2] = MI_BATCH_BUFFER_END;
 280       used += 12;
 281    }
 282    else {
 283       ((int *) batch->ptr)[0] = MI_FLUSH;
 284       ((int *) batch->ptr)[1] = MI_BATCH_BUFFER_END;
 285       used += 8;
 286    }
 287
 288    driBOUnmap(batch->buffer);
 289    batch->ptr = NULL;
 290    batch->map = NULL;
 291
 292    /* TODO: Just pass the relocation list and dma buffer up to the
 293     * kernel.
 294     */
 295    if (!was_locked)
 296       LOCK_HARDWARE(intel);
 297
 298    do_flush_locked(batch, used, GL_FALSE);
 299
 300    if (!was_locked)
 301       UNLOCK_HARDWARE(intel);
 302
 303    /* Reset the buffer:
 304     */
 305    intel_batchbuffer_reset(batch);
 306    return batch->last_fence;
 307 }
 308
 309
 310 void
 311 intel_batchbuffer_finish(struct intel_batchbuffer *batch)
 312 {
 313    struct _DriFenceObject *fence = intel_batchbuffer_flush(batch);
 314    if (fence) {
 315       driFenceReference(fence);
 316       driFenceFinish(fence,
 317                      DRM_FENCE_TYPE_EXE | DRM_I915_FENCE_TYPE_RW,
 318                      GL_FALSE);
 319       driFenceUnReference(fence);
 320    }
 321 }
 322
 323
 324 /*  This is the only way buffers get added to the validate list.
 325  */
 326 boolean
 327 intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
 328                              struct _DriBufferObject *buffer,
 329                              uint flags, uint mask, uint delta)
 330 {
 331    assert(batch->nr_relocs < MAX_RELOCS);
 332
 333    driBOAddListItem(&batch->list, buffer, flags, mask);
 334
 335    {
 336       struct buffer_reloc *r = &batch->reloc[batch->nr_relocs++];
 337       driBOReference(buffer);
 338       r->buf = buffer;
 339       r->offset = batch->ptr - batch->map;
 340       r->delta = delta;
 341       *(uint *) batch->ptr = 0x12345678;
 342    }
 343
 344    batch->ptr += 4;
 345    return GL_TRUE;
 346 }
 347
 348
 349 void
 350 intel_batchbuffer_data(struct intel_batchbuffer *batch,
 351                        const void *data, uint bytes, uint flags)
 352 {
 353    assert((bytes & 3) == 0);
 354    intel_batchbuffer_require_space(batch, bytes, flags);
 355    memcpy(batch->ptr, data, bytes);
 356    batch->ptr += bytes;
 357 }