src/mesa/drivers/dri/nouveau/nouveau_fifo.c

   1 /**************************************************************************
   2
   3 Copyright 2006 Stephane Marchesin
   4 All Rights Reserved.
   5
   6 Permission is hereby granted, free of charge, to any person obtaining a
   7 copy of this software and associated documentation files (the "Software"),
   8 to deal in the Software without restriction, including without limitation
   9 on the rights to use, copy, modify, merge, publish, distribute, sub
  10 license, and/or sell copies of the Software, and to permit persons to whom
  11 the Software is furnished to do so, subject to the following conditions:
  12
  13 The above copyright notice and this permission notice (including the next
  14 paragraph) shall be included in all copies or substantial portions of the
  15 Software.
  16
  17 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20 ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
  21 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23 USE OR OTHER DEALINGS IN THE SOFTWARE.
  24
  25 **************************************************************************/
  26
  27
  28 #include "vblank.h"
  29 #include <errno.h>
  30 #include "mtypes.h"
  31 #include "macros.h"
  32 #include "dd.h"
  33 #include "swrast/swrast.h"
  34 #include "nouveau_context.h"
  35 #include "nouveau_msg.h"
  36 #include "nouveau_fifo.h"
  37 #include "nouveau_lock.h"
  38 #include "nouveau_object.h"
  39 #include "nouveau_sync.h"
  40
  41
  42 #define RING_SKIPS 8
  43
  44 void WAIT_RING(nouveauContextPtr nmesa,u_int32_t size)
  45 {
  46 #ifdef NOUVEAU_RING_DEBUG
  47         return;
  48 #endif
  49         u_int32_t fifo_get;
  50         while(nmesa->fifo.free < size+1) {
  51                 fifo_get = NV_FIFO_READ_GET();
  52
  53                 if(nmesa->fifo.put >= fifo_get) {
  54                         nmesa->fifo.free = nmesa->fifo.max - nmesa->fifo.current;
  55                         if(nmesa->fifo.free < size+1) {
  56                                 OUT_RING(NV03_FIFO_CMD_JUMP | nmesa->fifo.put_base);
  57                                 if(fifo_get <= RING_SKIPS) {
  58                                         if(nmesa->fifo.put <= RING_SKIPS) /* corner case - will be idle */
  59                                                 NV_FIFO_WRITE_PUT(RING_SKIPS + 1);
  60                                         do { fifo_get = NV_FIFO_READ_GET(); }
  61                                         while(fifo_get <= RING_SKIPS);
  62                                 }
  63                                 NV_FIFO_WRITE_PUT(RING_SKIPS);
  64                                 nmesa->fifo.current = nmesa->fifo.put = RING_SKIPS;
  65                                 nmesa->fifo.free = fifo_get - (RING_SKIPS + 1);
  66                         }
  67                 } else
  68                         nmesa->fifo.free = fifo_get - nmesa->fifo.current - 1;
  69         }
  70 }
  71
  72 /*
  73  * Wait for the channel to be idle
  74  */
  75 void nouveauWaitForIdleLocked(nouveauContextPtr nmesa)
  76 {
  77         /* Wait for FIFO idle */
  78         FIRE_RING();
  79         while(RING_AHEAD()>0);
  80
  81         /* Wait on notifier to indicate all commands in the channel have
  82          * been completed.
  83          */
  84         nouveau_notifier_wait_nop(nmesa->glCtx, nmesa->syncNotifier, NvSub3D);
  85 }
  86
  87 void nouveauWaitForIdle(nouveauContextPtr nmesa)
  88 {
  89         LOCK_HARDWARE(nmesa);
  90         nouveauWaitForIdleLocked(nmesa);
  91         UNLOCK_HARDWARE(nmesa);
  92 }
  93
  94 // here we call the fifo initialization ioctl and fill in stuff accordingly
  95 GLboolean nouveauFifoInit(nouveauContextPtr nmesa)
  96 {
  97         drm_nouveau_fifo_alloc_t fifo_init;
  98         int i;
  99
 100 #ifdef NOUVEAU_RING_DEBUG
 101         return GL_TRUE;
 102 #endif
 103
 104         int ret;
 105         ret=drmCommandWriteRead(nmesa->driFd, DRM_NOUVEAU_FIFO_ALLOC, &fifo_init, sizeof(fifo_init));
 106         if (ret) {
 107                 FATAL("Fifo initialization ioctl failed (returned %d)\n",ret);
 108                 return GL_FALSE;
 109         }
 110
 111         ret = drmMap(nmesa->driFd, fifo_init.cmdbuf, fifo_init.cmdbuf_size, &nmesa->fifo.buffer);
 112         if (ret) {
 113                 FATAL("Unable to map the fifo (returned %d)\n",ret);
 114                 return GL_FALSE;
 115         }
 116         ret = drmMap(nmesa->driFd, fifo_init.ctrl, fifo_init.ctrl_size, &nmesa->fifo.mmio);
 117         if (ret) {
 118                 FATAL("Unable to map the control regs (returned %d)\n",ret);
 119                 return GL_FALSE;
 120         }
 121
 122         /* Setup our initial FIFO tracking params */
 123         nmesa->fifo.put_base = fifo_init.put_base;
 124         nmesa->fifo.current  = 0;
 125         nmesa->fifo.put      = 0;
 126         nmesa->fifo.max      = (fifo_init.cmdbuf_size >> 2) - 1;
 127         nmesa->fifo.free     = nmesa->fifo.max - nmesa->fifo.current;
 128
 129         for (i=0; i<RING_SKIPS; i++)
 130            OUT_RING(0);
 131         nmesa->fifo.free -= RING_SKIPS;
 132
 133         MESSAGE("Fifo init ok. Using context %d\n", fifo_init.channel);
 134         return GL_TRUE;
 135 }
 136
 137