src/mesa/drivers/dri/nouveau/nouveau_fifo.c

   1 /**************************************************************************
   2
   3 Copyright 2006 Stephane Marchesin
   4 All Rights Reserved.
   5
   6 Permission is hereby granted, free of charge, to any person obtaining a
   7 copy of this software and associated documentation files (the "Software"),
   8 to deal in the Software without restriction, including without limitation
   9 on the rights to use, copy, modify, merge, publish, distribute, sub
  10 license, and/or sell copies of the Software, and to permit persons to whom
  11 the Software is furnished to do so, subject to the following conditions:
  12
  13 The above copyright notice and this permission notice (including the next
  14 paragraph) shall be included in all copies or substantial portions of the
  15 Software.
  16
  17 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20 ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
  21 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23 USE OR OTHER DEALINGS IN THE SOFTWARE.
  24
  25 **************************************************************************/
  26
  27
  28 #include "vblank.h"
  29 #include <errno.h>
  30 #include "mtypes.h"
  31 #include "macros.h"
  32 #include "dd.h"
  33 #include "swrast/swrast.h"
  34 #include "nouveau_context.h"
  35 #include "nouveau_msg.h"
  36 #include "nouveau_fifo.h"
  37 #include "nouveau_lock.h"
  38
  39
  40 #define RING_SKIPS 8
  41
  42 void WAIT_RING(nouveauContextPtr nmesa,u_int32_t size)
  43 {
  44 #ifdef NOUVEAU_RING_DEBUG
  45         return;
  46 #endif
  47         u_int32_t fifo_get;
  48         while(nmesa->fifo.free < size+1) {
  49                 fifo_get = NV_FIFO_READ(NV03_FIFO_REGS_DMAGET);
  50
  51                 if(nmesa->fifo.put >= fifo_get) {
  52                         nmesa->fifo.free = nmesa->fifo.max - nmesa->fifo.current;
  53                         if(nmesa->fifo.free < size+1) {
  54                                 OUT_RING(NV03_FIFO_CMD_REWIND);                                                 \
  55                                 if(fifo_get <= RING_SKIPS) {
  56                                         if(nmesa->fifo.put <= RING_SKIPS) /* corner case - will be idle */
  57                                                 NV_FIFO_WRITE(NV03_FIFO_REGS_DMAPUT, RING_SKIPS + 1);
  58                                         do { fifo_get = NV_FIFO_READ(NV03_FIFO_REGS_DMAGET); }
  59                                         while(fifo_get <= RING_SKIPS);
  60                                 }
  61                                 NV_FIFO_WRITE(NV03_FIFO_REGS_DMAPUT, RING_SKIPS);
  62                                 nmesa->fifo.current = nmesa->fifo.put = RING_SKIPS;
  63                                 nmesa->fifo.free = fifo_get - (RING_SKIPS + 1);
  64                         }
  65                 } else
  66                         nmesa->fifo.free = fifo_get - nmesa->fifo.current - 1;
  67         }
  68 }
  69
  70 /*
  71  * Wait for the card to be idle
  72  */
  73 void nouveauWaitForIdleLocked(nouveauContextPtr nmesa)
  74 {
  75         int i,status;
  76
  77         FIRE_RING();
  78         while(RING_AHEAD()>0);
  79
  80         for(i=0;i<1000000;i++) /* 1 second */
  81         {
  82                 switch(nmesa->screen->card->type)
  83                 {
  84                         case NV_03:
  85                                 status=NV_READ(NV03_STATUS);
  86                                 break;
  87                         case NV_04:
  88                         case NV_05:
  89                         case NV_10:
  90                         case NV_20:
  91                         case NV_30:
  92                         case NV_40:
  93                         case G_70:
  94                         default:
  95                                 status=NV_READ(NV04_STATUS);
  96                                 break;
  97                 }
  98                 if (status)
  99                         return;
 100                 DO_USLEEP(1);
 101         }
 102 }
 103
 104 void nouveauWaitForIdle(nouveauContextPtr nmesa)
 105 {
 106         LOCK_HARDWARE(nmesa);
 107         nouveauWaitForIdleLocked(nmesa);
 108         UNLOCK_HARDWARE(nmesa);
 109 }
 110
 111 // here we call the fifo initialization ioctl and fill in stuff accordingly
 112 GLboolean nouveauFifoInit(nouveauContextPtr nmesa)
 113 {
 114         drm_nouveau_fifo_alloc_t fifo_init;
 115
 116         int ret;
 117         ret=drmCommandWriteRead(nmesa->driFd, DRM_NOUVEAU_FIFO_ALLOC, &fifo_init, sizeof(fifo_init));
 118         if (ret) {
 119                 FATAL("Fifo initialization ioctl failed (returned %d)\n",ret);
 120                 return GL_FALSE;
 121         }
 122
 123         if (drmMap(nmesa->driFd, fifo_init.cmdbuf, fifo_init.cmdbuf_size, &nmesa->fifo.buffer)) {
 124                 FATAL("Unable to map the fifo\n",ret);
 125                 return GL_FALSE;
 126         }
 127         if (drmMap(nmesa->driFd, fifo_init.ctrl, fifo_init.ctrl_size, &nmesa->fifo.mmio)) {
 128                 FATAL("Unable to map the control regs\n",ret);
 129                 return GL_FALSE;
 130         }
 131
 132         MESSAGE("Fifo init ok. Using context %d\n", fifo_init.channel);
 133 }
 134
 135