src/mesa/drivers/dri/nouveau/nouveau_fifo.h

   1 /**************************************************************************
   2
   3 Copyright 2006 Stephane Marchesin
   4 All Rights Reserved.
   5
   6 Permission is hereby granted, free of charge, to any person obtaining a
   7 copy of this software and associated documentation files (the "Software"),
   8 to deal in the Software without restriction, including without limitation
   9 on the rights to use, copy, modify, merge, publish, distribute, sub
  10 license, and/or sell copies of the Software, and to permit persons to whom
  11 the Software is furnished to do so, subject to the following conditions:
  12
  13 The above copyright notice and this permission notice (including the next
  14 paragraph) shall be included in all copies or substantial portions of the
  15 Software.
  16
  17 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20 ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
  21 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23 USE OR OTHER DEALINGS IN THE SOFTWARE.
  24
  25 **************************************************************************/
  26
  27
  28
  29 #ifndef __NOUVEAU_FIFO_H__
  30 #define __NOUVEAU_FIFO_H__
  31
  32 #include "nouveau_context.h"
  33
  34 #define NV_READ(reg) *(volatile u_int32_t *)(nmesa->mmio + (reg))
  35
  36 #define NV_FIFO_READ(reg) *(volatile u_int32_t *)(nmesa->fifo_mmio + (reg))
  37 #define NV_FIFO_WRITE(reg,value) *(volatile u_int32_t *)(nmesa->fifo_mmio + (reg)) = value;
  38
  39 /*
  40  * Ring/fifo interface
  41  *
  42  * - Begin a ring section with BEGIN_RING_SIZE (if you know the full size in advance)
  43  * - Begin a ring section with BEGIN_RING_PRIM otherwise (and then finish with FINISH_RING_PRIM)
  44  * - Output stuff to the ring with either OUT_RINGp (outputs a raw mem chunk), OUT_RING (1 uint32_t) or OUT_RINGf (1 float)
  45  * - RING_AVAILABLE returns the available fifo (in uint32_ts)
  46  * - RING_AHEAD returns how much ahead of the last submission point we are
  47  * - FIRE_RING fire whatever we have that wasn't fired before
  48  * - WAIT_RING waits for size (in uint32_ts) to be available in the fifo
  49  */
  50
  51 #define OUT_RINGp(ptr,sz) do{                                                   \
  52         memcpy(nmesa->fifo.buffer+nmesa->fifo.current,ptr,sz);                  \
  53         nmesa->fifo.current+=sz;                                                \
  54 }while(0)
  55
  56 #define OUT_RING(n) do {                                                        \
  57 nmesa->fifo.buffer[nmesa->fifo.current++]=n;                                    \
  58 }while(0)
  59
  60 #define OUT_RINGf(n) do {                                                       \
  61 *((float*)(nmesa->fifo.buffer+nmesa->fifo.current++))=n;                        \
  62 }while(0)
  63
  64 extern void WAIT_RING(nouveauContextPtr nmesa,u_int32_t size);
  65
  66 #define BEGIN_RING_PRIM(subchannel,tag,size) do {                                       \
  67         if (nmesa->fifo.free<size)                                                      \
  68                 WAIT_RING(nmesa,(size));                                                \
  69         OUT_RING( ((subchannel) << 13) | (tag));                                        \
  70 }while(0)
  71
  72 #define FINISH_RING_PRIM() do{                                                          \
  73         nmesa->fifo.buffer[nmesa->fifo.put]|=((nmesa->fifo.current-nmesa->fifo.put) << 18);             \
  74 }while(0)
  75
  76 #define BEGIN_RING_SIZE(subchannel,tag,size) do {                                       \
  77         if (nmesa->fifo.free<size)                                                      \
  78                 WAIT_RING(nmesa,(size));                                                \
  79         OUT_RING( (size<<18) | ((subchannel) << 13) | (tag));                           \
  80 }while(0)
  81
  82 #define RING_AVAILABLE() (nmesa->fifo.free-1)
  83
  84 #define RING_AHEAD() ((nmesa->fifo.put<=nmesa->fifo.current)?(nmesa->fifo.current-nmesa->fifo.put):nmesa->fifo.max-nmesa->fifo.put+nmesa->fifo.current)
  85
  86 #define FIRE_RING() do {                                                        \
  87         if (nmesa->fifo.current!=nmesa->fifo.put) {\
  88                 nmesa->fifo.put=nmesa->fifo.current;\
  89                 NV_FIFO_WRITE(NV03_FIFO_REGS_DMAPUT,nmesa->fifo.put);\
  90         }\
  91 }while(0)
  92
  93
  94 #endif /* __NOUVEAU_FIFO_H__ */
  95
  96