1 /**************************************************************************
3 Copyright 2006 Stephane Marchesin
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 on the rights to use, copy, modify, merge, publish, distribute, sub
10 license, and/or sell copies of the Software, and to permit persons to whom
11 the Software is furnished to do so, subject to the following conditions:
13 The above copyright notice and this permission notice (including the next
14 paragraph) shall be included in all copies or substantial portions of the
17 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
21 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 USE OR OTHER DEALINGS IN THE SOFTWARE.
25 **************************************************************************/
29 #ifndef __NOUVEAU_FIFO_H__
30 #define __NOUVEAU_FIFO_H__
32 #include "nouveau_context.h"
33 #include "nouveau_ctrlreg.h"
34 #include "nouveau_state_cache.h"
36 //#define NOUVEAU_RING_DEBUG
37 //#define NOUVEAU_STATE_CACHE_DISABLE
39 #define NV_READ(reg) *(volatile u_int32_t *)(nmesa->mmio + (reg))
41 #define NV_FIFO_READ(reg) *(volatile u_int32_t *)(nmesa->fifo.mmio + (reg/4))
42 #define NV_FIFO_WRITE(reg,value) *(volatile u_int32_t *)(nmesa->fifo.mmio + (reg/4)) = value;
43 #define NV_FIFO_READ_GET() ((NV_FIFO_READ(NV03_FIFO_REGS_DMAGET) - nmesa->fifo.put_base) >> 2)
44 #define NV_FIFO_WRITE_PUT(val) NV_FIFO_WRITE(NV03_FIFO_REGS_DMAPUT, ((val)<<2) + nmesa->fifo.put_base)
49 * - Begin a ring section with BEGIN_RING_SIZE (if you know the full size in advance)
50 * - Output stuff to the ring with either OUT_RINGp (outputs a raw mem chunk), OUT_RING (1 uint32_t) or OUT_RINGf (1 float)
51 * - RING_AVAILABLE returns the available fifo (in uint32_ts)
52 * - RING_AHEAD returns how much ahead of the last submission point we are
53 * - FIRE_RING fires whatever we have that wasn't fired before
54 * - WAIT_RING waits for size (in uint32_ts) to be available in the fifo
57 /* Enable for ring debugging. Prints out writes to the ring buffer
58 * but does not actually write to it.
60 #ifdef NOUVEAU_RING_DEBUG
62 #define OUT_RINGp(ptr,sz) do { \
63 uint32_t* p=(uint32_t*)(ptr); \
64 int i; printf("OUT_RINGp: (size 0x%x dwords)\n",sz); for(i=0;i<sz;i++) printf(" 0x%08x %f\n", *(p+i), *((float*)(p+i))); \
67 #define OUT_RING(n) do { \
68 printf("OUT_RINGn: 0x%08x (%s)\n", n, __func__); \
71 #define OUT_RINGf(n) do { \
72 printf("OUT_RINGf: %.04f (%s)\n", n, __func__); \
77 #define OUT_RINGp(ptr,sz) do{ \
78 memcpy(nmesa->fifo.buffer+nmesa->fifo.current,ptr,(sz)*4); \
79 nmesa->fifo.current+=(sz); \
82 #define OUT_RING(n) do { \
83 nmesa->fifo.buffer[nmesa->fifo.current++]=(n); \
86 #define OUT_RINGf(n) do { \
87 *((float*)(nmesa->fifo.buffer+nmesa->fifo.current++))=(n); \
92 #define BEGIN_RING_SIZE(subchannel,tag,size) do { \
93 nouveau_state_cache_flush(nmesa); \
94 if (nmesa->fifo.free <= (size)) \
95 WAIT_RING(nmesa,(size)); \
96 OUT_RING( ((size)<<18) | ((subchannel) << 13) | (tag)); \
97 nmesa->fifo.free -= ((size) + 1); \
100 extern void WAIT_RING(nouveauContextPtr nmesa
,u_int32_t size
);
101 extern void nouveau_state_cache_flush(nouveauContextPtr nmesa
);
102 extern void nouveau_state_cache_init(nouveauContextPtr nmesa
);
104 #ifdef NOUVEAU_STATE_CACHE_DISABLE
105 #define BEGIN_RING_CACHE(subc,tag,size) BEGIN_RING_SIZE((subc), (tag), (size))
106 #define OUT_RING_CACHE(n) OUT_RING((n))
107 #define OUT_RING_CACHEf(n) OUT_RINGf((n))
108 #define OUT_RING_CACHEp(ptr, sz) OUT_RINGp((ptr), (sz))
110 #define BEGIN_RING_CACHE(subchannel,tag,size) do { \
111 nmesa->state_cache.dirty=1; \
112 nmesa->state_cache.current_pos=((tag)/4); \
115 #define OUT_RING_CACHE(n) do { \
116 if (nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value!=(n)) { \
117 nmesa->state_cache.atoms[nmesa->state_cache.current_pos].dirty=1; \
118 nmesa->state_cache.hdirty[nmesa->state_cache.current_pos/NOUVEAU_STATE_CACHE_HIER_SIZE]=1; \
119 nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value=(n); \
121 nmesa->state_cache.current_pos++; \
124 #define OUT_RING_CACHEf(n) do { \
125 if ((*(float*)(&nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value))!=(n)){ \
126 nmesa->state_cache.atoms[nmesa->state_cache.current_pos].dirty=1; \
127 nmesa->state_cache.hdirty[nmesa->state_cache.current_pos/NOUVEAU_STATE_CACHE_HIER_SIZE]=1; \
128 (*(float*)(&nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value))=(n);\
130 nmesa->state_cache.current_pos++; \
133 #define OUT_RING_CACHEp(ptr,sz) do { \
134 uint32_t* p=(uint32_t*)(ptr); \
135 int i; for(i=0;i<sz;i++) OUT_RING_CACHE(*(p+i)); \
139 #define RING_AVAILABLE() (nmesa->fifo.free-1)
141 #define RING_AHEAD() ((nmesa->fifo.put<=nmesa->fifo.current)?(nmesa->fifo.current-nmesa->fifo.put):nmesa->fifo.max-nmesa->fifo.put+nmesa->fifo.current)
143 #define FIRE_RING() do { \
144 if (nmesa->fifo.current!=nmesa->fifo.put) { \
145 nmesa->fifo.put=nmesa->fifo.current; \
146 NV_FIFO_WRITE_PUT(nmesa->fifo.put); \
150 extern void nouveauWaitForIdle(nouveauContextPtr nmesa
);
151 extern void nouveauWaitForIdleLocked(nouveauContextPtr nmesa
);
152 extern GLboolean
nouveauFifoInit(nouveauContextPtr nmesa
);
154 #endif /* __NOUVEAU_FIFO_H__ */