src/mesa/drivers/dri/nouveau/nouveau_fifo.h

   1 /**************************************************************************
   2
   3 Copyright 2006 Stephane Marchesin
   4 All Rights Reserved.
   5
   6 Permission is hereby granted, free of charge, to any person obtaining a
   7 copy of this software and associated documentation files (the "Software"),
   8 to deal in the Software without restriction, including without limitation
   9 on the rights to use, copy, modify, merge, publish, distribute, sub
  10 license, and/or sell copies of the Software, and to permit persons to whom
  11 the Software is furnished to do so, subject to the following conditions:
  12
  13 The above copyright notice and this permission notice (including the next
  14 paragraph) shall be included in all copies or substantial portions of the
  15 Software.
  16
  17 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20 ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
  21 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23 USE OR OTHER DEALINGS IN THE SOFTWARE.
  24
  25 **************************************************************************/
  26
  27
  28
  29 #ifndef __NOUVEAU_FIFO_H__
  30 #define __NOUVEAU_FIFO_H__
  31
  32 #include "nouveau_context.h"
  33 #include "nouveau_ctrlreg.h"
  34
  35 //#define NOUVEAU_RING_DEBUG
  36 //#define NOUVEAU_STATE_CACHE_DISABLE
  37
  38 #define NV_READ(reg) *(volatile u_int32_t *)(nmesa->mmio + (reg))
  39
  40 #define NV_FIFO_READ(reg) *(volatile u_int32_t *)(nmesa->fifo.mmio + (reg/4))
  41 #define NV_FIFO_WRITE(reg,value) *(volatile u_int32_t *)(nmesa->fifo.mmio + (reg/4)) = value;
  42 #define NV_FIFO_READ_GET() ((NV_FIFO_READ(NV03_FIFO_REGS_DMAGET) - nmesa->fifo.put_base) >> 2)
  43 #define NV_FIFO_WRITE_PUT(val) NV_FIFO_WRITE(NV03_FIFO_REGS_DMAPUT, ((val)<<2) + nmesa->fifo.put_base)
  44
  45 /*
  46  * Ring/fifo interface
  47  *
  48  * - Begin a ring section with BEGIN_RING_SIZE (if you know the full size in advance)
  49  * - Output stuff to the ring with either OUT_RINGp (outputs a raw mem chunk), OUT_RING (1 uint32_t) or OUT_RINGf (1 float)
  50  * - RING_AVAILABLE returns the available fifo (in uint32_ts)
  51  * - RING_AHEAD returns how much ahead of the last submission point we are
  52  * - FIRE_RING fires whatever we have that wasn't fired before
  53  * - WAIT_RING waits for size (in uint32_ts) to be available in the fifo
  54  */
  55
  56 /* Enable for ring debugging.  Prints out writes to the ring buffer
  57  * but does not actually write to it.
  58  */
  59 #ifdef NOUVEAU_RING_DEBUG
  60
  61 #define OUT_RINGp(ptr,sz) do {                                                  \
  62 uint32_t* p=(uint32_t*)(ptr);                                                   \
  63 int i; printf("OUT_RINGp: (size 0x%x dwords)\n",sz); for(i=0;i<sz;i++) printf(" 0x%08x\n", *(p+i));     \
  64 }while(0)
  65
  66 #define OUT_RING(n) do {                                                        \
  67     printf("OUT_RINGn: 0x%08x (%s)\n", n, __func__);                            \
  68 }while(0)
  69
  70 #define OUT_RINGf(n) do {                                                       \
  71     printf("OUT_RINGf: %.04f (%s)\n", n, __func__);                             \
  72 }while(0)
  73
  74 #else
  75
  76 #define OUT_RINGp(ptr,sz) do{                                                   \
  77         memcpy(nmesa->fifo.buffer+nmesa->fifo.current,ptr,(sz)*4);              \
  78         nmesa->fifo.current+=(sz);                                              \
  79 }while(0)
  80
  81 #define OUT_RING(n) do {                                                        \
  82 nmesa->fifo.buffer[nmesa->fifo.current++]=(n);                                  \
  83 }while(0)
  84
  85 #define OUT_RINGf(n) do {                                                       \
  86 *((float*)(nmesa->fifo.buffer+nmesa->fifo.current++))=(n);                      \
  87 }while(0)
  88
  89 #endif
  90
  91 #define BEGIN_RING_SIZE(subchannel,tag,size) do {                                       \
  92         nouveau_state_cache_flush(nmesa);                                               \
  93         if (nmesa->fifo.free <= (size))                                                 \
  94                 WAIT_RING(nmesa,(size));                                                \
  95         OUT_RING( ((size)<<18) | ((subchannel) << 13) | (tag));                         \
  96         nmesa->fifo.free -= ((size) + 1);                                               \
  97 }while(0)
  98
  99 extern void WAIT_RING(nouveauContextPtr nmesa,u_int32_t size);
 100 extern void nouveau_state_cache_flush(nouveauContextPtr nmesa);
 101 extern void nouveau_state_cache_init(nouveauContextPtr nmesa);
 102
 103 #ifdef NOUVEAU_STATE_CACHE_DISABLE
 104 #define BEGIN_RING_CACHE(subc,tag,size) BEGIN_RING_SIZE((subc), (tag), (size))
 105 #define OUT_RING_CACHE(n) OUT_RING((n))
 106 #define OUT_RING_CACHEf(n) OUT_RINGf((n))
 107 #define OUT_RING_CACHEp(ptr, sz) OUT_RINGp((ptr), (sz))
 108 #else
 109 #define BEGIN_RING_CACHE(subchannel,tag,size) do {                                      \
 110         nmesa->state_cache.dirty=1;                                                     \
 111         nmesa->state_cache.current_pos=((tag)/4);                                       \
 112 }while(0)
 113
 114 #define OUT_RING_CACHE(n) do {                                                                  \
 115         if (nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value!=(n))        {       \
 116                 nmesa->state_cache.atoms[nmesa->state_cache.current_pos].dirty=1;               \
 117                 nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value=(n);             \
 118         }                                                                                       \
 119         nmesa->state_cache.current_pos++;                                                       \
 120 }while(0)
 121
 122 #define OUT_RING_CACHEf(n) do {                                                                 \
 123         if ((*(float*)(&nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value))!=(n)){ \
 124                 nmesa->state_cache.atoms[nmesa->state_cache.current_pos].dirty=1;               \
 125                 (*(float*)(&nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value))=(n);\
 126         }                                                                                       \
 127         nmesa->state_cache.current_pos++;                                                       \
 128 }while(0)
 129
 130 #define OUT_RING_CACHEp(ptr,sz) do {                                                    \
 131 uint32_t* p=(uint32_t*)(ptr);                                                           \
 132 int i; for(i=0;i<sz;i++) OUT_RING_CACHE(*(p+i));                                        \
 133 }while(0)
 134 #endif
 135
 136 #define RING_AVAILABLE() (nmesa->fifo.free-1)
 137
 138 #define RING_AHEAD() ((nmesa->fifo.put<=nmesa->fifo.current)?(nmesa->fifo.current-nmesa->fifo.put):nmesa->fifo.max-nmesa->fifo.put+nmesa->fifo.current)
 139
 140 #define FIRE_RING() do {                             \
 141         if (nmesa->fifo.current!=nmesa->fifo.put) {  \
 142                 nmesa->fifo.put=nmesa->fifo.current; \
 143                 NV_FIFO_WRITE_PUT(nmesa->fifo.put);  \
 144         }                                            \
 145 }while(0)
 146
 147 extern void nouveauWaitForIdle(nouveauContextPtr nmesa);
 148 extern GLboolean nouveauFifoInit(nouveauContextPtr nmesa);
 149
 150 #endif /* __NOUVEAU_FIFO_H__ */
 151
 152