src/mesa/drivers/dri/nouveau/nv20_shader.h

   1 /* NV20_TCL_PRIMITIVE_3D_0x0B00 */
   2 #define NV20_VP_INST_0B00       0x00000000 /* always 0? */
   3 #define NV20_VP_INST0_KNOWN     0
   4
   5 /* NV20_TCL_PRIMITIVE_3D_0x0B04 */
   6 #define NV20_VP_INST_SCA_OPCODE_SHIFT                           25
   7 #define NV20_VP_INST_SCA_OPCODE_MASK                            (0x0F << 25)
   8 #define NV20_VP_INST_OPCODE_RCP 0x2
   9 #define NV20_VP_INST_OPCODE_RCC 0x3
  10 #define NV20_VP_INST_OPCODE_RSQ 0x4
  11 #define NV20_VP_INST_OPCODE_EXP 0x5
  12 #define NV20_VP_INST_OPCODE_LOG 0x6
  13 #define NV20_VP_INST_OPCODE_LIT 0x7
  14 #define NV20_VP_INST_VEC_OPCODE_SHIFT                           21
  15 #define NV20_VP_INST_VEC_OPCODE_MASK                            (0x0F << 21)
  16 #define NV20_VP_INST_OPCODE_NOP 0x0 /* guess */
  17 #define NV20_VP_INST_OPCODE_MOV 0x1
  18 #define NV20_VP_INST_OPCODE_MUL 0x2
  19 #define NV20_VP_INST_OPCODE_ADD 0x3
  20 #define NV20_VP_INST_OPCODE_MAD 0x4
  21 #define NV20_VP_INST_OPCODE_DP3 0x5
  22 #define NV20_VP_INST_OPCODE_DPH 0x6
  23 #define NV20_VP_INST_OPCODE_DP4 0x7
  24 #define NV20_VP_INST_OPCODE_DST 0x8
  25 #define NV20_VP_INST_OPCODE_MIN 0x9
  26 #define NV20_VP_INST_OPCODE_MAX 0xA
  27 #define NV20_VP_INST_OPCODE_SLT 0xB
  28 #define NV20_VP_INST_OPCODE_SGE 0xC
  29 #define NV20_VP_INST_OPCODE_ARL 0xD
  30 #define NV20_VP_INST_CONST_SRC_SHIFT                            13
  31 #define NV20_VP_INST_CONST_SRC_MASK                             (0xFF << 13)
  32 #define NV20_VP_INST_INPUT_SRC_SHIFT                            9
  33 #define NV20_VP_INST_INPUT_SRC_MASK                             (0xF << 9) /* guess */
  34 #define NV20_VP_INST_INPUT_SRC_POS      0
  35 #define NV20_VP_INST_INPUT_SRC_COL0     3
  36 #define NV20_VP_INST_INPUT_SRC_COL1     4
  37 #define NV20_VP_INST_INPUT_SRC_TC(n)    (9+n)
  38 #define NV20_VP_INST_SRC0H_SHIFT                                0
  39 #define NV20_VP_INST_SRC0H_MASK                                 (0x1FF << 0)
  40 #define NV20_VP_INST1_KNOWN     ( \
  41         NV20_VP_INST_OPCODE_MASK | \
  42         NV20_VP_INST_CONST_SRC_MASK | \
  43         NV20_VP_INST_INPUT_SRC_MASK | \
  44         NV20_VP_INST_SRC0H_MASK \
  45         )
  46
  47 /* NV20_TCL_PRIMITIVE_3D_0x0B08 */
  48 #define NV20_VP_INST_SRC0L_SHIFT                                26
  49 #define NV20_VP_INST_SRC0L_MASK                                 (0x3F  <<26)
  50 #define NV20_VP_INST_SRC1_SHIFT                                 11
  51 #define NV20_VP_INST_SRC1_MASK                                  (0x7FFF<<11)
  52 #define NV20_VP_INST_SRC2H_SHIFT                                0
  53 #define NV20_VP_INST_SRC2H_MASK                                 (0x7FF << 0)
  54
  55 /* NV20_TCL_PRIMITIVE_3D_0x0B0C */
  56 #define NV20_VP_INST_SRC2L_SHIFT                                28
  57 #define NV20_VP_INST_SRC2L_MASK                                 (0x0F  <<28)
  58 #define NV20_VP_INST_VTEMP_WRITEMASK_SHIFT                      24
  59 #define NV20_VP_INST_VTEMP_WRITEMASK_MASK                       (0x0F  <<24)
  60 #    define NV20_VP_INST_TEMP_WRITEMASK_X       (1<<27)
  61 #    define NV20_VP_INST_TEMP_WRITEMASK_Y       (1<<26)
  62 #    define NV20_VP_INST_TEMP_WRITEMASK_Z       (1<<25)
  63 #    define NV20_VP_INST_TEMP_WRITEMASK_W       (1<<24)
  64 #define NV20_VP_INST_DEST_TEMP_ID_SHIFT                         20
  65 #define NV20_VP_INST_DEST_TEMP_ID_MASK                          (0x0F  <<20)
  66 #define NV20_VP_INST_STEMP_WRITEMASK_SHIFT                      16
  67 #define NV20_VP_INST_STEMP_WRITEMASK_MASK                       (0x0F  <<16)
  68 #    define NV20_VP_INST_STEMP_WRITEMASK_X      (1<<19)
  69 #    define NV20_VP_INST_STEMP_WRITEMASK_Y      (1<<18)
  70 #    define NV20_VP_INST_STEMP_WRITEMASK_Z      (1<<17)
  71 #    define NV20_VP_INST_STEMP_WRITEMASK_W      (1<<16)
  72 #define NV20_VP_INST_DEST_WRITEMASK_SHIFT                       12
  73 #define NV20_VP_INST_DEST_WRITEMASK_MASK                        (0x0F  <<12)
  74 #    define NV20_VP_INST_DEST_WRITEMASK_X       (1<<15)
  75 #    define NV20_VP_INST_DEST_WRITEMASK_Y       (1<<14)
  76 #    define NV20_VP_INST_DEST_WRITEMASK_Z       (1<<13)
  77 #    define NV20_VP_INST_DEST_WRITEMASK_W       (1<<12)
  78 #define NV20_VP_INST_DEST_SHIFT                                 3
  79 #define NV20_VP_INST_DEST_MASK                                  (0xF << 3) /* guess */
  80 #define NV20_VP_INST_DEST_POS   0
  81 #define NV20_VP_INST_DEST_COL0  3
  82 #define NV20_VP_INST_DEST_COL1  4
  83 #define NV20_VP_INST_DEST_TC(n) (9+n)
  84 #define NV20_VP_INST_INDEX_CONST                                (1<<1)
  85 #define NV20_VP_INST3_KNOWN ( \
  86         NV20_VP_INST_SRC2L_MASK | \
  87         NV20_VP_INST_TEMP_WRITEMASK_MASK | \
  88         NV20_VP_INST_DEST_TEMP_ID_MASK | \
  89         NV20_VP_INST_STEMP_WRITEMASK_MASK | \
  90         NV20_VP_INST_DEST_WRITEMASK_MASK | \
  91         NV20_VP_INST_DEST_MASK | \
  92         NV20_VP_INST_INDEX_CONST \
  93         )
  94
  95 /* Useful to split the source selection regs into their pieces */
  96 #define NV20_VP_SRC0_HIGH_SHIFT 6
  97 #define NV20_VP_SRC0_HIGH_MASK  0x00007FC0
  98 #define NV20_VP_SRC0_LOW_MASK   0x0000003F
  99 #define NV20_VP_SRC2_HIGH_SHIFT 4
 100 #define NV20_VP_SRC2_HIGH_MASK  0x00007FF0
 101 #define NV20_VP_SRC2_LOW_MASK   0x0000000F
 102
 103 #define NV20_VP_SRC_REG_NEGATE                                  (1<<14)
 104 #define NV20_VP_SRC_REG_SWZ_X_SHIFT                             12
 105 #define NV20_VP_SRC_REG_SWZ_X_MASK                              (0x03  <<12)
 106 #define NV20_VP_SRC_REG_SWZ_Y_SHIFT                             10
 107 #define NV20_VP_SRC_REG_SWZ_Y_MASK                              (0x03  <<10)
 108 #define NV20_VP_SRC_REG_SWZ_Z_SHIFT                             8
 109 #define NV20_VP_SRC_REG_SWZ_Z_MASK                              (0x03  << 8)
 110 #define NV20_VP_SRC_REG_SWZ_W_SHIFT                             6
 111 #define NV20_VP_SRC_REG_SWZ_W_MASK                              (0x03  << 6)
 112 #define NV20_VP_SRC_REG_SWZ_ALL_SHIFT                           6
 113 #define NV20_VP_SRC_REG_SWZ_ALL_MASK                            (0xFF  << 6)
 114 #define NV20_VP_SRC_REG_TEMP_ID_SHIFT                           2
 115 #define NV20_VP_SRC_REG_TEMP_ID_MASK                            (0x0F  << 0)
 116 #define NV20_VP_SRC_REG_TYPE_SHIFT                              0
 117 #define NV20_VP_SRC_REG_TYPE_MASK                               (0x03  << 0)
 118 #define NV20_VP_SRC_REG_TYPE_TEMP       1
 119 #define NV20_VP_SRC_REG_TYPE_INPUT      2
 120 #define NV20_VP_SRC_REG_TYPE_CONST      3       /* guess */
 121