1 #ifndef __NV40_SHADER_H__
2 #define __NV40_SHADER_H__
4 /* Vertex programs instruction set
6 * The NV40 instruction set is very similar to NV30. Most fields are in
7 * a slightly different position in the instruction however.
10 * In some cases it is possible to put two instructions into one opcode
11 * slot. The rules for when this is OK is not entirely clear to me yet.
13 * There are separate writemasks and dest temp register fields for each
14 * grouping of instructions. There is however only one field with the
15 * ID of a result register. Writing to temp/result regs is selected by
16 * setting VEC_RESULT/SCA_RESULT.
19 * The source/dest temp register fields have been extended by 1 bit, to
20 * give a total of 32 temporary registers.
23 * NV40 can use an address register to index into vertex attribute regs.
24 * This is done by putting the offset value into INPUT_SRC and setting
25 * the INDEX_INPUT flag.
27 * Conditional execution (see NV_vertex_program{2,3} for details)
28 * There is a second condition code register on NV40, it's use is enabled
29 * by setting the COND_REG_SELECT_1 flag.
35 /* ---- OPCODE BITS 127:96 / data DWORD 0 --- */
36 #define NV40_VP_INST_VEC_RESULT (1 << 30)
38 #define NV40_VP_INST_COND_UPDATE_ENABLE ((1 << 14)|1<<29)
39 /* use address reg as index into attribs */
40 #define NV40_VP_INST_INDEX_INPUT (1 << 27)
41 #define NV40_VP_INST_COND_REG_SELECT_1 (1 << 25)
42 #define NV40_VP_INST_ADDR_REG_SELECT_1 (1 << 24)
43 #define NV40_VP_INST_SRC2_ABS (1 << 23)
44 #define NV40_VP_INST_SRC1_ABS (1 << 22)
45 #define NV40_VP_INST_SRC0_ABS (1 << 21)
46 #define NV40_VP_INST_VEC_DEST_TEMP_SHIFT 15
47 #define NV40_VP_INST_VEC_DEST_TEMP_MASK (0x1F << 15)
48 #define NV40_VP_INST_COND_TEST_ENABLE (1 << 13)
49 #define NV40_VP_INST_COND_SHIFT 10
50 #define NV40_VP_INST_COND_MASK (0x7 << 10)
51 # define NV40_VP_INST_COND_FL 0
52 # define NV40_VP_INST_COND_LT 1
53 # define NV40_VP_INST_COND_EQ 2
54 # define NV40_VP_INST_COND_LE 3
55 # define NV40_VP_INST_COND_GT 4
56 # define NV40_VP_INST_COND_NE 5
57 # define NV40_VP_INST_COND_GE 6
58 # define NV40_VP_INST_COND_TR 7
59 #define NV40_VP_INST_COND_SWZ_X_SHIFT 8
60 #define NV40_VP_INST_COND_SWZ_X_MASK (3 << 8)
61 #define NV40_VP_INST_COND_SWZ_Y_SHIFT 6
62 #define NV40_VP_INST_COND_SWZ_Y_MASK (3 << 6)
63 #define NV40_VP_INST_COND_SWZ_Z_SHIFT 4
64 #define NV40_VP_INST_COND_SWZ_Z_MASK (3 << 4)
65 #define NV40_VP_INST_COND_SWZ_W_SHIFT 2
66 #define NV40_VP_INST_COND_SWZ_W_MASK (3 << 2)
67 #define NV40_VP_INST_COND_SWZ_ALL_SHIFT 2
68 #define NV40_VP_INST_COND_SWZ_ALL_MASK (0xFF << 2)
69 #define NV40_VP_INST_ADDR_SWZ_SHIFT 0
70 #define NV40_VP_INST_ADDR_SWZ_MASK (0x03 << 0)
71 #define NV40_VP_INST0_KNOWN ( \
72 NV40_VP_INST_INDEX_INPUT | \
73 NV40_VP_INST_COND_REG_SELECT_1 | \
74 NV40_VP_INST_ADDR_REG_SELECT_1 | \
75 NV40_VP_INST_SRC2_ABS | \
76 NV40_VP_INST_SRC1_ABS | \
77 NV40_VP_INST_SRC0_ABS | \
78 NV40_VP_INST_VEC_DEST_TEMP_MASK | \
79 NV40_VP_INST_COND_TEST_ENABLE | \
80 NV40_VP_INST_COND_MASK | \
81 NV40_VP_INST_COND_SWZ_ALL_MASK | \
82 NV40_VP_INST_ADDR_SWZ_MASK)
84 /* ---- OPCODE BITS 95:64 / data DWORD 1 --- */
85 #define NV40_VP_INST_VEC_OPCODE_SHIFT 22
86 #define NV40_VP_INST_VEC_OPCODE_MASK (0x1F << 22)
87 # define NV40_VP_INST_OP_NOP 0x00
88 # define NV40_VP_INST_OP_MOV 0x01
89 # define NV40_VP_INST_OP_MUL 0x02
90 # define NV40_VP_INST_OP_ADD 0x03
91 # define NV40_VP_INST_OP_MAD 0x04
92 # define NV40_VP_INST_OP_DP3 0x05
93 # define NV40_VP_INST_OP_DP4 0x07
94 # define NV40_VP_INST_OP_DPH 0x06
95 # define NV40_VP_INST_OP_DST 0x08
96 # define NV40_VP_INST_OP_MIN 0x09
97 # define NV40_VP_INST_OP_MAX 0x0A
98 # define NV40_VP_INST_OP_SLT 0x0B
99 # define NV40_VP_INST_OP_SGE 0x0C
100 # define NV40_VP_INST_OP_ARL 0x0D
101 # define NV40_VP_INST_OP_FRC 0x0E
102 # define NV40_VP_INST_OP_FLR 0x0F
103 # define NV40_VP_INST_OP_SEQ 0x10
104 # define NV40_VP_INST_OP_SFL 0x11
105 # define NV40_VP_INST_OP_SGT 0x12
106 # define NV40_VP_INST_OP_SLE 0x13
107 # define NV40_VP_INST_OP_SNE 0x14
108 # define NV40_VP_INST_OP_STR 0x15
109 # define NV40_VP_INST_OP_SSG 0x16
110 # define NV40_VP_INST_OP_ARR 0x17
111 # define NV40_VP_INST_OP_ARA 0x18
112 # define NV40_VP_INST_OP_TXWHAT 0x19
113 #define NV40_VP_INST_SCA_OPCODE_SHIFT 27
114 #define NV40_VP_INST_SCA_OPCODE_MASK (0x1F << 27)
115 # define NV40_VP_INST_OP_RCP 0x02
116 # define NV40_VP_INST_OP_RCC 0x03
117 # define NV40_VP_INST_OP_RSQ 0x04
118 # define NV40_VP_INST_OP_EXP 0x05
119 # define NV40_VP_INST_OP_LOG 0x06
120 # define NV40_VP_INST_OP_LIT 0x07
121 # define NV40_VP_INST_OP_BRA 0x09
122 # define NV40_VP_INST_OP_CAL 0x0B
123 # define NV40_VP_INST_OP_RET 0x0C
124 # define NV40_VP_INST_OP_LG2 0x0D
125 # define NV40_VP_INST_OP_EX2 0x0E
126 # define NV40_VP_INST_OP_SIN 0x0F
127 # define NV40_VP_INST_OP_COS 0x10
128 # define NV40_VP_INST_OP_PUSHA 0x13
129 # define NV40_VP_INST_OP_POPA 0x14
130 #define NV40_VP_INST_CONST_SRC_SHIFT 12
131 #define NV40_VP_INST_CONST_SRC_MASK (0xFF << 12)
132 #define NV40_VP_INST_INPUT_SRC_SHIFT 8
133 #define NV40_VP_INST_INPUT_SRC_MASK (0x0F << 8)
134 # define NV40_VP_INST_IN_POS 0
135 # define NV40_VP_INST_IN_WEIGHT 1
136 # define NV40_VP_INST_IN_NORMAL 2
137 # define NV40_VP_INST_IN_COL0 3
138 # define NV40_VP_INST_IN_COL1 4
139 # define NV40_VP_INST_IN_FOGC 5
140 # define NV40_VP_INST_IN_TC0 8
141 # define NV40_VP_INST_IN_TC(n) (8+n)
142 #define NV40_VP_INST_SRC0H_SHIFT 0
143 #define NV40_VP_INST_SRC0H_MASK (0xFF << 0)
144 #define NV40_VP_INST1_KNOWN ( \
145 NV40_VP_INST_VEC_OPCODE_MASK | \
146 NV40_VP_INST_SCA_OPCODE_MASK | \
147 NV40_VP_INST_CONST_SRC_MASK | \
148 NV40_VP_INST_INPUT_SRC_MASK | \
149 NV40_VP_INST_SRC0H_MASK \
152 /* ---- OPCODE BITS 63:32 / data DWORD 2 --- */
153 #define NV40_VP_INST_SRC0L_SHIFT 23
154 #define NV40_VP_INST_SRC0L_MASK (0x1FF << 23)
155 #define NV40_VP_INST_SRC1_SHIFT 6
156 #define NV40_VP_INST_SRC1_MASK (0x1FFFF << 6)
157 #define NV40_VP_INST_SRC2H_SHIFT 0
158 #define NV40_VP_INST_SRC2H_MASK (0x3F << 0)
159 #define NV40_VP_INST_IADDRH_SHIFT 0
160 #define NV40_VP_INST_IADDRH_MASK (0x1F << 0)
162 /* ---- OPCODE BITS 31:0 / data DWORD 3 --- */
163 #define NV40_VP_INST_IADDRL_SHIFT 29
164 #define NV40_VP_INST_IADDRL_MASK (7 << 29)
165 #define NV40_VP_INST_SRC2L_SHIFT 21
166 #define NV40_VP_INST_SRC2L_MASK (0x7FF << 21)
167 #define NV40_VP_INST_SCA_WRITEMASK_SHIFT 17
168 #define NV40_VP_INST_SCA_WRITEMASK_MASK (0xF << 17)
169 # define NV40_VP_INST_SCA_WRITEMASK_X (1 << 20)
170 # define NV40_VP_INST_SCA_WRITEMASK_Y (1 << 19)
171 # define NV40_VP_INST_SCA_WRITEMASK_Z (1 << 18)
172 # define NV40_VP_INST_SCA_WRITEMASK_W (1 << 17)
173 #define NV40_VP_INST_VEC_WRITEMASK_SHIFT 13
174 #define NV40_VP_INST_VEC_WRITEMASK_MASK (0xF << 13)
175 # define NV40_VP_INST_VEC_WRITEMASK_X (1 << 16)
176 # define NV40_VP_INST_VEC_WRITEMASK_Y (1 << 15)
177 # define NV40_VP_INST_VEC_WRITEMASK_Z (1 << 14)
178 # define NV40_VP_INST_VEC_WRITEMASK_W (1 << 13)
179 #define NV40_VP_INST_SCA_RESULT (1 << 12)
180 #define NV40_VP_INST_SCA_DEST_TEMP_SHIFT 7
181 #define NV40_VP_INST_SCA_DEST_TEMP_MASK (0x1F << 7)
182 #define NV40_VP_INST_DEST_SHIFT 2
183 #define NV40_VP_INST_DEST_MASK (31 << 2)
184 # define NV40_VP_INST_DEST_POS 0
185 # define NV40_VP_INST_DEST_COL0 1
186 # define NV40_VP_INST_DEST_COL1 2
187 # define NV40_VP_INST_DEST_BFC0 3
188 # define NV40_VP_INST_DEST_BFC1 4
189 # define NV40_VP_INST_DEST_FOGC 5
190 # define NV40_VP_INST_DEST_PSZ 6
191 # define NV40_VP_INST_DEST_TC0 7
192 # define NV40_VP_INST_DEST_TC(n) (7+n)
193 # define NV40_VP_INST_DEST_TEMP 0x1F
194 #define NV40_VP_INST_INDEX_CONST (1 << 1)
195 #define NV40_VP_INST_LAST (1 << 0)
196 #define NV40_VP_INST3_KNOWN ( \
197 NV40_VP_INST_SRC2L_MASK |\
198 NV40_VP_INST_SCA_WRITEMASK_MASK |\
199 NV40_VP_INST_VEC_WRITEMASK_MASK |\
200 NV40_VP_INST_SCA_DEST_TEMP_MASK |\
201 NV40_VP_INST_DEST_MASK |\
202 NV40_VP_INST_INDEX_CONST)
204 /* Useful to split the source selection regs into their pieces */
205 #define NV40_VP_SRC0_HIGH_SHIFT 9
206 #define NV40_VP_SRC0_HIGH_MASK 0x0001FE00
207 #define NV40_VP_SRC0_LOW_MASK 0x000001FF
208 #define NV40_VP_SRC2_HIGH_SHIFT 11
209 #define NV40_VP_SRC2_HIGH_MASK 0x0001F800
210 #define NV40_VP_SRC2_LOW_MASK 0x000007FF
212 /* Source selection - these are the bits you fill NV40_VP_INST_SRCn with */
213 #define NV40_VP_SRC_NEGATE (1 << 16)
214 #define NV40_VP_SRC_SWZ_X_SHIFT 14
215 #define NV40_VP_SRC_SWZ_X_MASK (3 << 14)
216 #define NV40_VP_SRC_SWZ_Y_SHIFT 12
217 #define NV40_VP_SRC_SWZ_Y_MASK (3 << 12)
218 #define NV40_VP_SRC_SWZ_Z_SHIFT 10
219 #define NV40_VP_SRC_SWZ_Z_MASK (3 << 10)
220 #define NV40_VP_SRC_SWZ_W_SHIFT 8
221 #define NV40_VP_SRC_SWZ_W_MASK (3 << 8)
222 #define NV40_VP_SRC_SWZ_ALL_SHIFT 8
223 #define NV40_VP_SRC_SWZ_ALL_MASK (0xFF << 8)
224 #define NV40_VP_SRC_TEMP_SRC_SHIFT 2
225 #define NV40_VP_SRC_TEMP_SRC_MASK (0x1F << 2)
226 #define NV40_VP_SRC_REG_TYPE_SHIFT 0
227 #define NV40_VP_SRC_REG_TYPE_MASK (3 << 0)
228 # define NV40_VP_SRC_REG_TYPE_UNK0 0
229 # define NV40_VP_SRC_REG_TYPE_TEMP 1
230 # define NV40_VP_SRC_REG_TYPE_INPUT 2
231 # define NV40_VP_SRC_REG_TYPE_CONST 3
235 * Each fragment program opcode appears to be comprised of 4 32-bit values.
237 * 0 - Opcode, output reg/mask, ATTRIB source
242 * There appears to be no special difference between result regs and temp regs.
243 * result.color == R0.xyzw
244 * result.depth == R1.z
245 * When the fragprog contains instructions to write depth,
246 * NV30_TCL_PRIMITIVE_3D_UNK1D78=0 otherwise it is set to 1.
248 * Constants are inserted directly after the instruction that uses them.
250 * It appears that it's not possible to use two input registers in one
251 * instruction as the input sourcing is done in the instruction dword
252 * and not the source selection dwords. As such instructions such as:
254 * ADD result.color, fragment.color, fragment.texcoord[0];
256 * must be split into two MOV's and then an ADD (nvidia does this) but
257 * I'm not sure why it's not just one MOV and then source the second input
258 * in the ADD instruction..
260 * Negation of the full source is done with NV30_FP_REG_NEGATE, arbitrary
261 * negation requires multiplication with a const.
263 * Arbitrary swizzling is supported with the exception of SWIZZLE_ZERO and
266 * The temp/result regs appear to be initialised to (0.0, 0.0, 0.0, 0.0) as
267 * SWIZZLE_ZERO is implemented simply by not writing to the relevant components
268 * of the destination.
271 * Loops appear to be fairly expensive on NV40 at least, the proprietary
272 * driver goes to a lot of effort to avoid using the native looping
273 * instructions. If the total number of *executed* instructions between
274 * REP/ENDREP or LOOP/ENDLOOP is <=500, the driver will unroll the loop.
275 * The maximum loop count is 255.
277 * Conditional execution
280 * Non-native instructions:
283 * SUB - ADD, negate second source
285 * POW - LG2 + MUL + EX2
292 //== Opcode / Destination selection ==
293 #define NV40_FP_OP_PROGRAM_END (1 << 0)
294 #define NV40_FP_OP_OUT_REG_SHIFT 1
295 #define NV40_FP_OP_OUT_REG_MASK (31 << 1)
296 /* Needs to be set when writing outputs to get expected result.. */
297 #define NV40_FP_OP_UNK0_7 (1 << 7)
298 #define NV40_FP_OP_COND_WRITE_ENABLE (1 << 8)
299 #define NV40_FP_OP_OUTMASK_SHIFT 9
300 #define NV40_FP_OP_OUTMASK_MASK (0xF << 9)
301 # define NV40_FP_OP_OUT_X (1 << 9)
302 # define NV40_FP_OP_OUT_Y (1 <<10)
303 # define NV40_FP_OP_OUT_Z (1 <<11)
304 # define NV40_FP_OP_OUT_W (1 <<12)
305 /* Uncertain about these, especially the input_src values.. it's possible that
306 * they can be dynamically changed.
308 #define NV40_FP_OP_INPUT_SRC_SHIFT 13
309 #define NV40_FP_OP_INPUT_SRC_MASK (15 << 13)
310 # define NV40_FP_OP_INPUT_SRC_POSITION 0x0
311 # define NV40_FP_OP_INPUT_SRC_COL0 0x1
312 # define NV40_FP_OP_INPUT_SRC_COL1 0x2
313 # define NV40_FP_OP_INPUT_SRC_FOGC 0x3
314 # define NV40_FP_OP_INPUT_SRC_TC0 0x4
315 # define NV40_FP_OP_INPUT_SRC_TC(n) (0x4 + n)
316 # define NV40_FP_OP_INPUT_SRC_FACING 0xE
317 #define NV40_FP_OP_TEX_UNIT_SHIFT 17
318 #define NV40_FP_OP_TEX_UNIT_MASK (0xF << 17)
319 #define NV40_FP_OP_PRECISION_SHIFT 22
320 #define NV40_FP_OP_PRECISION_MASK (3 << 22)
321 # define NV40_FP_PRECISION_FP32 0
322 # define NV40_FP_PRECISION_FP16 1
323 # define NV40_FP_PRECISION_FX12 2
324 #define NV40_FP_OP_OPCODE_SHIFT 24
325 #define NV40_FP_OP_OPCODE_MASK (0x3F << 24)
326 # define NV40_FP_OP_OPCODE_NOP 0x00
327 # define NV40_FP_OP_OPCODE_MOV 0x01
328 # define NV40_FP_OP_OPCODE_MUL 0x02
329 # define NV40_FP_OP_OPCODE_ADD 0x03
330 # define NV40_FP_OP_OPCODE_MAD 0x04
331 # define NV40_FP_OP_OPCODE_DP3 0x05
332 # define NV40_FP_OP_OPCODE_DP4 0x06
333 # define NV40_FP_OP_OPCODE_DST 0x07
334 # define NV40_FP_OP_OPCODE_MIN 0x08
335 # define NV40_FP_OP_OPCODE_MAX 0x09
336 # define NV40_FP_OP_OPCODE_SLT 0x0A
337 # define NV40_FP_OP_OPCODE_SGE 0x0B
338 # define NV40_FP_OP_OPCODE_SLE 0x0C
339 # define NV40_FP_OP_OPCODE_SGT 0x0D
340 # define NV40_FP_OP_OPCODE_SNE 0x0E
341 # define NV40_FP_OP_OPCODE_SEQ 0x0F
342 # define NV40_FP_OP_OPCODE_FRC 0x10
343 # define NV40_FP_OP_OPCODE_FLR 0x11
344 # define NV40_FP_OP_OPCODE_KIL 0x12
345 # define NV40_FP_OP_OPCODE_PK4B 0x13
346 # define NV40_FP_OP_OPCODE_UP4B 0x14
347 /* DDX/DDY can only write to XY */
348 # define NV40_FP_OP_OPCODE_DDX 0x15
349 # define NV40_FP_OP_OPCODE_DDY 0x16
350 # define NV40_FP_OP_OPCODE_TEX 0x17
351 # define NV40_FP_OP_OPCODE_TXP 0x18
352 # define NV40_FP_OP_OPCODE_TXD 0x19
353 # define NV40_FP_OP_OPCODE_RCP 0x1A
354 # define NV40_FP_OP_OPCODE_EX2 0x1C
355 # define NV40_FP_OP_OPCODE_LG2 0x1D
356 # define NV40_FP_OP_OPCODE_COS 0x22
357 # define NV40_FP_OP_OPCODE_SIN 0x23
358 # define NV40_FP_OP_OPCODE_PK2H 0x24
359 # define NV40_FP_OP_OPCODE_UP2H 0x25
360 # define NV40_FP_OP_OPCODE_PK4UB 0x27
361 # define NV40_FP_OP_OPCODE_UP4UB 0x28
362 # define NV40_FP_OP_OPCODE_PK2US 0x29
363 # define NV40_FP_OP_OPCODE_UP2US 0x2A
364 # define NV40_FP_OP_OPCODE_DP2A 0x2E
365 # define NV40_FP_OP_OPCODE_TXL 0x2F
366 # define NV40_FP_OP_OPCODE_TXB 0x31
367 # define NV40_FP_OP_OPCODE_DIV 0x3A
368 /* The use of these instructions appears to be indicated by bit 31 of DWORD 2.*/
369 # define NV40_FP_OP_BRA_OPCODE_BRK 0x0
370 # define NV40_FP_OP_BRA_OPCODE_CAL 0x1
371 # define NV40_FP_OP_BRA_OPCODE_IF 0x2
372 # define NV40_FP_OP_BRA_OPCODE_LOOP 0x3
373 # define NV40_FP_OP_BRA_OPCODE_REP 0x4
374 # define NV40_FP_OP_BRA_OPCODE_RET 0x5
375 #define NV40_FP_OP_OUT_SAT (1 << 31)
377 /* high order bits of SRC0 */
378 #define NV40_FP_OP_OUT_ABS (1 << 29)
379 #define NV40_FP_OP_COND_SWZ_W_SHIFT 27
380 #define NV40_FP_OP_COND_SWZ_W_MASK (3 << 27)
381 #define NV40_FP_OP_COND_SWZ_Z_SHIFT 25
382 #define NV40_FP_OP_COND_SWZ_Z_MASK (3 << 25)
383 #define NV40_FP_OP_COND_SWZ_Y_SHIFT 23
384 #define NV40_FP_OP_COND_SWZ_Y_MASK (3 << 23)
385 #define NV40_FP_OP_COND_SWZ_X_SHIFT 21
386 #define NV40_FP_OP_COND_SWZ_X_MASK (3 << 21)
387 #define NV40_FP_OP_COND_SWZ_ALL_SHIFT 21
388 #define NV40_FP_OP_COND_SWZ_ALL_MASK (0xFF << 21)
389 #define NV40_FP_OP_COND_SHIFT 18
390 #define NV40_FP_OP_COND_MASK (0x07 << 18)
391 # define NV40_FP_OP_COND_FL 0
392 # define NV40_FP_OP_COND_LT 1
393 # define NV40_FP_OP_COND_EQ 2
394 # define NV40_FP_OP_COND_LE 3
395 # define NV40_FP_OP_COND_GT 4
396 # define NV40_FP_OP_COND_NE 5
397 # define NV40_FP_OP_COND_GE 6
398 # define NV40_FP_OP_COND_TR 7
400 /* high order bits of SRC1 */
401 #define NV40_FP_OP_OPCODE_IS_BRANCH (1<<31)
402 #define NV40_FP_OP_DST_SCALE_SHIFT 28
403 #define NV40_FP_OP_DST_SCALE_MASK (3 << 28)
406 #define NV40_FP_OP_LOOP_INCR_SHIFT 19
407 #define NV40_FP_OP_LOOP_INCR_MASK (0xFF << 19)
408 #define NV40_FP_OP_LOOP_INDEX_SHIFT 10
409 #define NV40_FP_OP_LOOP_INDEX_MASK (0xFF << 10)
410 #define NV40_FP_OP_LOOP_COUNT_SHIFT 2
411 #define NV40_FP_OP_LOOP_COUNT_MASK (0xFF << 2)
414 #define NV40_FP_OP_ELSE_ID_SHIFT 2
415 #define NV40_FP_OP_ELSE_ID_MASK (0xFF << 2)
418 #define NV40_FP_OP_IADDR_SHIFT 2
419 #define NV40_FP_OP_IADDR_MASK (0xFF << 2)
422 * I have no idea why there are 3 count values here.. but they
423 * have always been filled with the same value in my tests so
426 #define NV40_FP_OP_REP_COUNT1_SHIFT 2
427 #define NV40_FP_OP_REP_COUNT1_MASK (0xFF << 2)
428 #define NV40_FP_OP_REP_COUNT2_SHIFT 10
429 #define NV40_FP_OP_REP_COUNT2_MASK (0xFF << 10)
430 #define NV40_FP_OP_REP_COUNT3_SHIFT 19
431 #define NV40_FP_OP_REP_COUNT3_MASK (0xFF << 19)
434 #define NV40_FP_OP_END_ID_SHIFT 2
435 #define NV40_FP_OP_END_ID_MASK (0xFF << 2)
438 #define NV40_FP_OP_INDEX_INPUT (1 << 30)
439 #define NV40_FP_OP_ADDR_INDEX_SHIFT 19
440 #define NV40_FP_OP_ADDR_INDEX_MASK (0xF << 19)
442 //== Register selection ==
443 #define NV40_FP_REG_TYPE_SHIFT 0
444 #define NV40_FP_REG_TYPE_MASK (3 << 0)
445 # define NV40_FP_REG_TYPE_TEMP 0
446 # define NV40_FP_REG_TYPE_INPUT 1
447 # define NV40_FP_REG_TYPE_CONST 2
448 #define NV40_FP_REG_SRC_SHIFT 2
449 #define NV40_FP_REG_SRC_MASK (31 << 2)
450 #define NV40_FP_REG_UNK_0 (1 << 8)
451 #define NV40_FP_REG_SWZ_ALL_SHIFT 9
452 #define NV40_FP_REG_SWZ_ALL_MASK (255 << 9)
453 #define NV40_FP_REG_SWZ_X_SHIFT 9
454 #define NV40_FP_REG_SWZ_X_MASK (3 << 9)
455 #define NV40_FP_REG_SWZ_Y_SHIFT 11
456 #define NV40_FP_REG_SWZ_Y_MASK (3 << 11)
457 #define NV40_FP_REG_SWZ_Z_SHIFT 13
458 #define NV40_FP_REG_SWZ_Z_MASK (3 << 13)
459 #define NV40_FP_REG_SWZ_W_SHIFT 15
460 #define NV40_FP_REG_SWZ_W_MASK (3 << 15)
461 # define NV40_FP_SWIZZLE_X 0
462 # define NV40_FP_SWIZZLE_Y 1
463 # define NV40_FP_SWIZZLE_Z 2
464 # define NV40_FP_SWIZZLE_W 3
465 #define NV40_FP_REG_NEGATE (1 << 17)
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