patch to import Jon Smirl's work from Bitkeeper
[mesa.git] / src / mesa / drivers / dri / r128 / server / r128.h
1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h,v 1.24 2002/12/16 16:19:10 dawes Exp $ */
2 /*
3 * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
4 * Precision Insight, Inc., Cedar Park, Texas, and
5 * VA Linux Systems Inc., Fremont, California.
6 *
7 * All Rights Reserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining
10 * a copy of this software and associated documentation files (the
11 * "Software"), to deal in the Software without restriction, including
12 * without limitation on the rights to use, copy, modify, merge,
13 * publish, distribute, sublicense, and/or sell copies of the Software,
14 * and to permit persons to whom the Software is furnished to do so,
15 * subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice (including the
18 * next paragraph) shall be included in all copies or substantial
19 * portions of the Software.
20 *
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
24 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
25 * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
26 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
27 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
28 * OTHER DEALINGS IN THE SOFTWARE.
29 */
30
31 /*
32 * Authors:
33 * Rickard E. Faith <faith@valinux.com>
34 * Kevin E. Martin <martin@valinux.com>
35 *
36 */
37
38 #ifndef _R128_H_
39 #define _R128_H_
40
41 #include "dri_util.h"
42 #ifndef _SOLO
43 #include "xf86str.h"
44
45 /* PCI support */
46 #include "xf86Pci.h"
47
48 /* XAA and Cursor Support */
49 #include "xaa.h"
50 #include "xf86Cursor.h"
51
52 /* DDC support */
53 #include "xf86DDC.h"
54
55 /* Xv support */
56 #include "xf86xv.h"
57
58 /* DRI support */
59 #ifdef XF86DRI
60 #define _XF86DRI_SERVER_
61 #include "r128_dripriv.h"
62 #include "dri.h"
63 #include "GL/glxint.h"
64 #endif
65 #endif
66 #ifdef _SOLO
67 #define XF86DRI
68 #endif
69
70 #define R128_DEBUG 0 /* Turn off debugging output */
71 #define R128_IDLE_RETRY 32 /* Fall out of idle loops after this count */
72 #define R128_TIMEOUT 2000000 /* Fall out of wait loops after this count */
73 #define R128_MMIOSIZE 0x4000
74
75 #define R128_VBIOS_SIZE 0x00010000
76
77 #if R128_DEBUG
78 #define R128TRACE(x) \
79 do { \
80 ErrorF("(**) %s(%d): ", R128_NAME, pScrn->scrnIndex); \
81 ErrorF x; \
82 } while (0);
83 #else
84 #define R128TRACE(x)
85 #endif
86
87
88 /* Other macros */
89 #define R128_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
90 #define R128_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1))
91 #define R128PTR(pScrn) ((R128InfoPtr)(pScrn)->driverPrivate)
92
93 /**
94 * \brief Chip families.
95 */
96 typedef enum {
97 CHIP_FAMILY_UNKNOWN,
98 CHIP_FAMILY_R128_PCI,
99 CHIP_FAMILY_R128_AGP,
100 } R128ChipFamily;
101
102 typedef struct { /* All values in XCLKS */
103 int ML; /* Memory Read Latency */
104 int MB; /* Memory Burst Length */
105 int Trcd; /* RAS to CAS delay */
106 int Trp; /* RAS percentage */
107 int Twr; /* Write Recovery */
108 int CL; /* CAS Latency */
109 int Tr2w; /* Read to Write Delay */
110 int Rloop; /* Loop Latency */
111 int Rloop_fudge; /* Add to ML to get Rloop */
112 char *name;
113 } R128RAMRec, *R128RAMPtr;
114
115 typedef struct {
116 /* Common registers */
117 CARD32 ovr_clr;
118 CARD32 ovr_wid_left_right;
119 CARD32 ovr_wid_top_bottom;
120 CARD32 ov0_scale_cntl;
121 CARD32 mpp_tb_config;
122 CARD32 mpp_gp_config;
123 CARD32 subpic_cntl;
124 CARD32 viph_control;
125 CARD32 i2c_cntl_1;
126 CARD32 gen_int_cntl;
127 CARD32 cap0_trig_cntl;
128 CARD32 cap1_trig_cntl;
129 CARD32 bus_cntl;
130 CARD32 config_cntl;
131
132 /* Other registers to save for VT switches */
133 CARD32 dp_datatype;
134 CARD32 gen_reset_cntl;
135 CARD32 clock_cntl_index;
136 CARD32 amcgpio_en_reg;
137 CARD32 amcgpio_mask;
138
139 /* CRTC registers */
140 CARD32 crtc_gen_cntl;
141 CARD32 crtc_ext_cntl;
142 CARD32 dac_cntl;
143 CARD32 crtc_h_total_disp;
144 CARD32 crtc_h_sync_strt_wid;
145 CARD32 crtc_v_total_disp;
146 CARD32 crtc_v_sync_strt_wid;
147 CARD32 crtc_offset;
148 CARD32 crtc_offset_cntl;
149 CARD32 crtc_pitch;
150
151 /* CRTC2 registers */
152 CARD32 crtc2_gen_cntl;
153
154 /* Flat panel registers */
155 CARD32 fp_crtc_h_total_disp;
156 CARD32 fp_crtc_v_total_disp;
157 CARD32 fp_gen_cntl;
158 CARD32 fp_h_sync_strt_wid;
159 CARD32 fp_horz_stretch;
160 CARD32 fp_panel_cntl;
161 CARD32 fp_v_sync_strt_wid;
162 CARD32 fp_vert_stretch;
163 CARD32 lvds_gen_cntl;
164 CARD32 tmds_crc;
165 CARD32 tmds_transmitter_cntl;
166
167 /* Computed values for PLL */
168 CARD32 dot_clock_freq;
169 CARD32 pll_output_freq;
170 int feedback_div;
171 int post_div;
172
173 /* PLL registers */
174 CARD32 ppll_ref_div;
175 CARD32 ppll_div_3;
176 CARD32 htotal_cntl;
177
178 /* DDA register */
179 CARD32 dda_config;
180 CARD32 dda_on_off;
181
182 /* Pallet */
183 GLboolean palette_valid;
184 CARD32 palette[256];
185 } R128SaveRec, *R128SavePtr;
186
187 #ifndef _SOLO
188 typedef struct {
189 CARD16 reference_freq;
190 CARD16 reference_div;
191 CARD32 min_pll_freq;
192 CARD32 max_pll_freq;
193 CARD16 xclk;
194 } R128PLLRec, *R128PLLPtr;
195
196 typedef struct {
197 int bitsPerPixel;
198 int depth;
199 int displayWidth;
200 int pixel_code;
201 int pixel_bytes;
202 DisplayModePtr mode;
203 } R128FBLayout;
204 #endif
205
206 typedef struct {
207 #ifndef _SOLO
208 EntityInfoPtr pEnt;
209 pciVideoPtr PciInfo;
210 PCITAG PciTag;
211 #endif
212 int Chipset;
213 GLboolean Primary;
214
215 GLboolean FBDev;
216
217 unsigned long LinearAddr; /* Frame buffer physical address */
218 unsigned long BIOSAddr; /* BIOS physical address */
219
220 unsigned char *MMIO; /* Map of MMIO region */
221 unsigned char *FB; /* Map of frame buffer */
222
223 CARD32 MemCntl;
224 CARD32 BusCntl;
225 unsigned long FbMapSize; /* Size of frame buffer, in bytes */
226 int Flags; /* Saved copy of mode flags */
227
228 #ifndef _SOLO
229 CARD8 BIOSDisplay; /* Device the BIOS is set to display to */
230
231 GLboolean HasPanelRegs; /* Current chip can connect to a FP */
232 CARD8 *VBIOS; /* Video BIOS for mode validation on FPs */
233 int FPBIOSstart; /* Start of the flat panel info */
234 #endif
235 /* Computed values for FPs */
236 int PanelXRes;
237 int PanelYRes;
238 int HOverPlus;
239 int HSyncWidth;
240 int HBlank;
241 int VOverPlus;
242 int VSyncWidth;
243 int VBlank;
244 int PanelPwrDly;
245 #ifndef _SOLO
246 R128PLLRec pll;
247 R128RAMPtr ram;
248
249 R128SaveRec SavedReg; /* Original (text) mode */
250 R128SaveRec ModeReg; /* Current mode */
251 GLboolean (*CloseScreen)(int, ScreenPtr);
252 void (*BlockHandler)(int, pointer, pointer, pointer);
253
254 GLboolean PaletteSavedOnVT; /* Palette saved on last VT switch */
255
256 XAAInfoRecPtr accel;
257 GLboolean accelOn;
258 xf86CursorInfoPtr cursor;
259 #endif
260 unsigned long cursor_start;
261 unsigned long cursor_end;
262
263 /*
264 * XAAForceTransBlit is used to change the behavior of the XAA
265 * SetupForScreenToScreenCopy function, to make it DGA-friendly.
266 */
267 GLboolean XAAForceTransBlit;
268
269 int fifo_slots; /* Free slots in the FIFO (64 max) */
270 int pix24bpp; /* Depth of pixmap for 24bpp framebuffer */
271 GLboolean dac6bits; /* Use 6 bit DAC? */
272
273 /* Computed values for Rage 128 */
274 int pitch;
275 int datatype;
276 CARD32 dp_gui_master_cntl;
277
278 /* Saved values for ScreenToScreenCopy */
279 int xdir;
280 int ydir;
281
282 /* ScanlineScreenToScreenColorExpand support */
283 unsigned char *scratch_buffer[1];
284 unsigned char *scratch_save;
285 int scanline_x;
286 int scanline_y;
287 int scanline_w;
288 int scanline_h;
289 #ifdef XF86DRI
290 int scanline_hpass;
291 int scanline_x1clip;
292 int scanline_x2clip;
293 int scanline_rop;
294 int scanline_fg;
295 int scanline_bg;
296 #endif /* XF86DRI */
297 int scanline_words;
298 int scanline_direct;
299 int scanline_bpp; /* Only used for ImageWrite */
300
301 #ifndef _SOLO
302 DGAModePtr DGAModes;
303 int numDGAModes;
304 GLboolean DGAactive;
305 int DGAViewportStatus;
306 DGAFunctionRec DGAFuncs;
307
308 R128FBLayout CurrentLayout;
309 #endif
310 #ifdef XF86DRI
311 drmContext drmCtx;
312 #ifndef _SOLO
313 DRIInfoPtr pDRIInfo;
314 int numVisualConfigs;
315 __GLXvisualConfig *pVisualConfigs;
316 R128ConfigPrivPtr pVisualConfigsPriv;
317 #endif
318
319 drmSize registerSize;
320 drmHandle registerHandle;
321
322 GLboolean IsPCI; /* Current card is a PCI card */
323 drmSize pciSize;
324 drmHandle pciMemHandle;
325 unsigned char *PCI; /* Map */
326
327 GLboolean allowPageFlip; /* Enable 3d page flipping */
328 GLboolean have3DWindows; /* Are there any 3d clients? */
329 int drmMinor;
330
331 drmSize agpSize;
332 drmHandle agpMemHandle; /* Handle from drmAgpAlloc */
333 unsigned long agpOffset;
334 unsigned char *AGP; /* Map */
335 int agpMode;
336
337 GLboolean CCEInUse; /* CCE is currently active */
338 int CCEMode; /* CCE mode that server/clients use */
339 int CCEFifoSize; /* Size of the CCE command FIFO */
340 GLboolean CCESecure; /* CCE security enabled */
341 int CCEusecTimeout; /* CCE timeout in usecs */
342
343 /* CCE ring buffer data */
344 unsigned long ringStart; /* Offset into AGP space */
345 drmHandle ringHandle; /* Handle from drmAddMap */
346 drmSize ringMapSize; /* Size of map */
347 int ringSize; /* Size of ring (in MB) */
348 unsigned char *ring; /* Map */
349 int ringSizeLog2QW;
350
351 unsigned long ringReadOffset; /* Offset into AGP space */
352 drmHandle ringReadPtrHandle; /* Handle from drmAddMap */
353 drmSize ringReadMapSize; /* Size of map */
354 unsigned char *ringReadPtr; /* Map */
355
356 /* CCE vertex/indirect buffer data */
357 unsigned long bufStart; /* Offset into AGP space */
358 drmHandle bufHandle; /* Handle from drmAddMap */
359 drmSize bufMapSize; /* Size of map */
360 int bufSize; /* Size of buffers (in MB) */
361 unsigned char *buf; /* Map */
362 int bufNumBufs; /* Number of buffers */
363 drmBufMapPtr buffers; /* Buffer map */
364
365 /* CCE AGP Texture data */
366 unsigned long agpTexStart; /* Offset into AGP space */
367 drmHandle agpTexHandle; /* Handle from drmAddMap */
368 drmSize agpTexMapSize; /* Size of map */
369 int agpTexSize; /* Size of AGP tex space (in MB) */
370 unsigned char *agpTex; /* Map */
371 int log2AGPTexGran;
372
373 /* CCE 2D accleration */
374 drmBufPtr indirectBuffer;
375 int indirectStart;
376
377 /* DRI screen private data */
378 int fbX;
379 int fbY;
380 int backX;
381 int backY;
382 int depthX;
383 int depthY;
384
385 int frontOffset;
386 int frontPitch;
387 int backOffset;
388 int backPitch;
389 int depthOffset;
390 int depthPitch;
391 int spanOffset;
392 int textureOffset;
393 int textureSize;
394 int log2TexGran;
395
396 /* Saved scissor values */
397 CARD32 sc_left;
398 CARD32 sc_right;
399 CARD32 sc_top;
400 CARD32 sc_bottom;
401
402 CARD32 re_top_left;
403 CARD32 re_width_height;
404
405 CARD32 aux_sc_cntl;
406
407 int irq;
408 CARD32 gen_int_cntl;
409
410 GLboolean DMAForXv;
411 #endif
412
413 #ifndef _SOLO
414 XF86VideoAdaptorPtr adaptor;
415 void (*VideoTimerCallback)(ScrnInfoPtr, Time);
416 int videoKey;
417 GLboolean showCache;
418 OptionInfoPtr Options;
419
420 GLboolean isDFP;
421 GLboolean isPro2;
422 I2CBusPtr pI2CBus;
423 CARD32 DDCReg;
424 #endif
425 } R128InfoRec, *R128InfoPtr;
426
427 #define R128WaitForFifo(pScrn, entries) \
428 do { \
429 if (info->fifo_slots < entries) R128WaitForFifoFunction(pScrn, entries); \
430 info->fifo_slots -= entries; \
431 } while (0)
432
433 extern void r128WaitForFifoFunction(const DRIDriverContext *ctx, int entries);
434 extern void r128WaitForIdle(const DRIDriverContext *ctx);
435
436 extern void r128WaitForVerticalSync(const DRIDriverContext *ctx);
437
438 extern GLboolean r128AccelInit(const DRIDriverContext *ctx);
439 extern void r128EngineInit(const DRIDriverContext *ctx);
440 extern GLboolean r128CursorInit(const DRIDriverContext *ctx);
441 extern GLboolean r128DGAInit(const DRIDriverContext *ctx);
442
443 extern void r128InitVideo(const DRIDriverContext *ctx);
444
445 extern GLboolean r128DRIScreenInit(const DRIDriverContext *ctx);
446 extern void r128DRICloseScreen(const DRIDriverContext *ctx);
447 extern GLboolean r128DRIFinishScreenInit(const DRIDriverContext *ctx);
448
449 #define R128CCE_START(ctx, info) \
450 do { \
451 int _ret = drmCommandNone(ctx->drmFD, DRM_R128_CCE_START); \
452 if (_ret) { \
453 fprintf(stderr, \
454 "%s: CCE start %d\n", __FUNCTION__, _ret); \
455 } \
456 } while (0)
457
458 #define R128CCE_STOP(ctx, info) \
459 do { \
460 int _ret = R128CCEStop(ctx); \
461 if (_ret) { \
462 fprintf(stderr, \
463 "%s: CCE stop %d\n", __FUNCTION__, _ret); \
464 } \
465 } while (0)
466
467 #define R128CCE_RESET(ctx, info) \
468 do { \
469 if (info->directRenderingEnabled \
470 && R128CCE_USE_RING_BUFFER(info->CCEMode)) { \
471 int _ret = drmCommandNone(info->drmFD, DRM_R128_CCE_RESET); \
472 if (_ret) { \
473 fprintf(stderr, \
474 "%s: CCE reset %d\n", __FUNCTION__, _ret); \
475 } \
476 } \
477 } while (0)
478
479
480 #define CCE_PACKET0( reg, n ) \
481 (R128_CCE_PACKET0 | ((n) << 16) | ((reg) >> 2))
482 #define CCE_PACKET1( reg0, reg1 ) \
483 (R128_CCE_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2))
484 #define CCE_PACKET2() \
485 (R128_CCE_PACKET2)
486 #define CCE_PACKET3( pkt, n ) \
487 (R128_CCE_PACKET3 | (pkt) | ((n) << 16))
488
489
490 #define R128_VERBOSE 0
491
492 #define RING_LOCALS CARD32 *__head; int __count;
493
494 #define R128CCE_REFRESH(pScrn, info) \
495 do { \
496 if ( R128_VERBOSE ) { \
497 fprintf(stderr, "REFRESH( %d ) in %s\n", \
498 !info->CCEInUse , __FUNCTION__ ); \
499 } \
500 if ( !info->CCEInUse ) { \
501 R128CCEWaitForIdle(pScrn); \
502 BEGIN_RING( 6 ); \
503 OUT_RING_REG( R128_RE_TOP_LEFT, info->re_top_left ); \
504 OUT_RING_REG( R128_RE_WIDTH_HEIGHT, info->re_width_height ); \
505 OUT_RING_REG( R128_AUX_SC_CNTL, info->aux_sc_cntl ); \
506 ADVANCE_RING(); \
507 info->CCEInUse = TRUE; \
508 } \
509 } while (0)
510
511 #define BEGIN_RING( n ) do { \
512 if ( R128_VERBOSE ) { \
513 fprintf(stderr, \
514 "BEGIN_RING( %d ) in %s\n", n, __FUNCTION__ ); \
515 } \
516 if ( !info->indirectBuffer ) { \
517 info->indirectBuffer = R128CCEGetBuffer( pScrn ); \
518 info->indirectStart = 0; \
519 } else if ( (info->indirectBuffer->used + 4*(n)) > \
520 info->indirectBuffer->total ) { \
521 R128CCEFlushIndirect( pScrn, 1 ); \
522 } \
523 __head = (pointer)((char *)info->indirectBuffer->address + \
524 info->indirectBuffer->used); \
525 __count = 0; \
526 } while (0)
527
528 #define ADVANCE_RING() do { \
529 if ( R128_VERBOSE ) { \
530 fprintf(stderr, \
531 "ADVANCE_RING() used: %d+%d=%d/%d\n", \
532 info->indirectBuffer->used - info->indirectStart, \
533 __count * sizeof(CARD32), \
534 info->indirectBuffer->used - info->indirectStart + \
535 __count * sizeof(CARD32), \
536 info->indirectBuffer->total - info->indirectStart ); \
537 } \
538 info->indirectBuffer->used += __count * (int)sizeof(CARD32); \
539 } while (0)
540
541 #define OUT_RING( x ) do { \
542 if ( R128_VERBOSE ) { \
543 fprintf(stderr, \
544 " OUT_RING( 0x%08x )\n", (unsigned int)(x) ); \
545 } \
546 MMIO_OUT32(&__head[__count++], 0, (x)); \
547 } while (0)
548
549 #define OUT_RING_REG( reg, val ) \
550 do { \
551 OUT_RING( CCE_PACKET0( reg, 0 ) ); \
552 OUT_RING( val ); \
553 } while (0)
554
555 #define FLUSH_RING() \
556 do { \
557 if ( R128_VERBOSE ) \
558 fprintf(stderr, \
559 "FLUSH_RING in %s\n", __FUNCTION__ ); \
560 if ( info->indirectBuffer ) { \
561 R128CCEFlushIndirect( pScrn, 0 ); \
562 } \
563 } while (0)
564
565
566 #endif