2 * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "radeon_common.h"
29 #include "r200_context.h"
30 #include "r200_blit.h"
32 static inline uint32_t cmdpacket0(struct radeon_screen
*rscrn
,
36 return CP_PACKET0(reg
, count
- 1);
40 static inline void emit_vtx_state(struct r200_context
*r200
)
42 BATCH_LOCALS(&r200
->radeon
);
45 if (r200
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
46 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS
, 0);
48 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS
, RADEON_TCL_BYPASS
);
50 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL
, (R200_VAP_FORCE_W_TO_ONE
|
51 (9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT
)));
52 OUT_BATCH_REGVAL(R200_SE_VTX_STATE_CNTL
, 0);
53 OUT_BATCH_REGVAL(R200_SE_VTE_CNTL
, 0);
54 OUT_BATCH_REGVAL(R200_SE_VTX_FMT_0
, R200_VTX_XY
);
55 OUT_BATCH_REGVAL(R200_SE_VTX_FMT_1
, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT
));
56 OUT_BATCH_REGVAL(RADEON_SE_CNTL
, (RADEON_DIFFUSE_SHADE_GOURAUD
|
59 RADEON_VTX_PIX_CENTER_OGL
|
60 RADEON_ROUND_MODE_ROUND
|
61 RADEON_ROUND_PREC_4TH_PIX
));
65 static void inline emit_tx_setup(struct r200_context
*r200
,
66 gl_format mesa_format
,
73 uint32_t txformat
= R200_TXFORMAT_NON_POWER2
;
74 BATCH_LOCALS(&r200
->radeon
);
76 assert(width
<= 2047);
77 assert(height
<= 2047);
78 assert(offset
% 32 == 0);
80 /* XXX others? BE/LE? */
81 switch (mesa_format
) {
82 case MESA_FORMAT_ARGB8888
:
83 txformat
|= R200_TXFORMAT_ARGB8888
| R200_TXFORMAT_ALPHA_IN_MAP
;
85 case MESA_FORMAT_XRGB8888
:
86 txformat
|= R200_TXFORMAT_ARGB8888
;
88 case MESA_FORMAT_RGB565
:
89 txformat
|= R200_TXFORMAT_RGB565
;
91 case MESA_FORMAT_ARGB4444
:
92 txformat
|= R200_TXFORMAT_ARGB4444
| R200_TXFORMAT_ALPHA_IN_MAP
;
94 case MESA_FORMAT_ARGB1555
:
95 txformat
|= R200_TXFORMAT_ARGB1555
| R200_TXFORMAT_ALPHA_IN_MAP
;
98 txformat
|= R200_TXFORMAT_I8
| R200_TXFORMAT_ALPHA_IN_MAP
;
105 OUT_BATCH_REGVAL(RADEON_PP_CNTL
, RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
);
106 OUT_BATCH_REGVAL(R200_PP_CNTL_X
, 0);
107 OUT_BATCH_REGVAL(R200_PP_TXMULTI_CTL_0
, 0);
108 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0
, (R200_TXC_ARG_A_ZERO
|
109 R200_TXC_ARG_B_ZERO
|
110 R200_TXC_ARG_C_R0_COLOR
|
112 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0
, R200_TXC_CLAMP_0_1
| R200_TXC_OUTPUT_REG_R0
);
113 OUT_BATCH_REGVAL(R200_PP_TXABLEND_0
, (R200_TXA_ARG_A_ZERO
|
114 R200_TXA_ARG_B_ZERO
|
115 R200_TXA_ARG_C_R0_ALPHA
|
117 OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0
, R200_TXA_CLAMP_0_1
| R200_TXA_OUTPUT_REG_R0
);
118 OUT_BATCH_REGVAL(R200_PP_TXFILTER_0
, (R200_CLAMP_S_CLAMP_LAST
|
119 R200_CLAMP_T_CLAMP_LAST
|
120 R200_MAG_FILTER_NEAREST
|
121 R200_MIN_FILTER_NEAREST
));
122 OUT_BATCH_REGVAL(R200_PP_TXFORMAT_0
, txformat
);
123 OUT_BATCH_REGVAL(R200_PP_TXFORMAT_X_0
, 0);
124 OUT_BATCH_REGVAL(R200_PP_TXSIZE_0
, ((width
- 1) |
125 ((height
- 1) << RADEON_TEX_VSIZE_SHIFT
)));
126 OUT_BATCH_REGVAL(R200_PP_TXPITCH_0
, pitch
- 32);
128 OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0
, 1);
129 OUT_BATCH_RELOC(0, bo
, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
134 static inline void emit_cb_setup(struct r200_context
*r200
,
135 struct radeon_bo
*bo
,
137 gl_format mesa_format
,
142 uint32_t dst_pitch
= pitch
;
143 uint32_t dst_format
= 0;
144 BATCH_LOCALS(&r200
->radeon
);
146 /* XXX others? BE/LE? */
147 switch (mesa_format
) {
148 case MESA_FORMAT_ARGB8888
:
149 case MESA_FORMAT_XRGB8888
:
150 dst_format
= RADEON_COLOR_FORMAT_ARGB8888
;
152 case MESA_FORMAT_RGB565
:
153 dst_format
= RADEON_COLOR_FORMAT_RGB565
;
155 case MESA_FORMAT_ARGB4444
:
156 dst_format
= RADEON_COLOR_FORMAT_ARGB4444
;
158 case MESA_FORMAT_ARGB1555
:
159 dst_format
= RADEON_COLOR_FORMAT_ARGB1555
;
162 dst_format
= RADEON_COLOR_FORMAT_RGB8
;
168 BEGIN_BATCH_NO_AUTOSTATE(22);
169 OUT_BATCH_REGVAL(R200_RE_AUX_SCISSOR_CNTL
, 0);
170 OUT_BATCH_REGVAL(R200_RE_CNTL
, 0);
171 OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT
, 0);
172 OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT
, ((width
<< RADEON_RE_WIDTH_SHIFT
) |
173 (height
<< RADEON_RE_HEIGHT_SHIFT
)));
174 OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK
, 0xffffffff);
175 OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL
, RADEON_SRC_BLEND_GL_ONE
| RADEON_DST_BLEND_GL_ZERO
);
176 OUT_BATCH_REGVAL(RADEON_RB3D_CNTL
, dst_format
);
178 OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET
, 1);
179 OUT_BATCH_RELOC(0, bo
, 0, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0);
180 OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH
, 1);
181 OUT_BATCH_RELOC(dst_pitch
, bo
, dst_pitch
, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0);
186 static GLboolean
validate_buffers(struct r200_context
*r200
,
187 struct radeon_bo
*src_bo
,
188 struct radeon_bo
*dst_bo
)
191 radeon_cs_space_add_persistent_bo(r200
->radeon
.cmdbuf
.cs
,
192 src_bo
, RADEON_GEM_DOMAIN_VRAM
, 0);
194 radeon_cs_space_add_persistent_bo(r200
->radeon
.cmdbuf
.cs
,
195 dst_bo
, 0, RADEON_GEM_DOMAIN_VRAM
);
197 ret
= radeon_cs_space_check_with_bo(r200
->radeon
.cmdbuf
.cs
,
198 first_elem(&r200
->radeon
.dma
.reserved
)->bo
,
199 RADEON_GEM_DOMAIN_GTT
, 0);
207 * Calculate texcoords for given image region.
208 * Output values are [minx, maxx, miny, maxy]
210 static inline void calc_tex_coords(float img_width
, float img_height
,
212 float reg_width
, float reg_height
,
213 unsigned flip_y
, float *buf
)
215 buf
[0] = x
/ img_width
;
216 buf
[1] = buf
[0] + reg_width
/ img_width
;
217 buf
[2] = y
/ img_height
;
218 buf
[3] = buf
[2] + reg_height
/ img_height
;
222 buf
[2] = 1.0 - buf
[3];
227 static inline void emit_draw_packet(struct r200_context
*r200
,
228 unsigned src_width
, unsigned src_height
,
229 unsigned src_x_offset
, unsigned src_y_offset
,
230 unsigned dst_x_offset
, unsigned dst_y_offset
,
231 unsigned reg_width
, unsigned reg_height
,
236 BATCH_LOCALS(&r200
->radeon
);
238 calc_tex_coords(src_width
, src_height
,
239 src_x_offset
, src_y_offset
,
240 reg_width
, reg_height
,
243 verts
[0] = dst_x_offset
;
244 verts
[1] = dst_y_offset
+ reg_height
;
245 verts
[2] = texcoords
[0];
246 verts
[3] = texcoords
[2];
248 verts
[4] = dst_x_offset
+ reg_width
;
249 verts
[5] = dst_y_offset
+ reg_height
;
250 verts
[6] = texcoords
[1];
251 verts
[7] = texcoords
[2];
253 verts
[8] = dst_x_offset
+ reg_width
;
254 verts
[9] = dst_y_offset
;
255 verts
[10] = texcoords
[1];
256 verts
[11] = texcoords
[3];
259 OUT_BATCH(R200_CP_CMD_3D_DRAW_IMMD_2
| (12 << 16));
260 OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING
|
261 RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST
|
263 OUT_BATCH_TABLE(verts
, 12);
268 * Copy a region of [@a width x @a height] pixels from source buffer
269 * to destination buffer.
270 * @param[in] r200 r200 context
271 * @param[in] src_bo source radeon buffer object
272 * @param[in] src_offset offset of the source image in the @a src_bo
273 * @param[in] src_mesaformat source image format
274 * @param[in] src_pitch aligned source image width
275 * @param[in] src_width source image width
276 * @param[in] src_height source image height
277 * @param[in] src_x_offset x offset in the source image
278 * @param[in] src_y_offset y offset in the source image
279 * @param[in] dst_bo destination radeon buffer object
280 * @param[in] dst_offset offset of the destination image in the @a dst_bo
281 * @param[in] dst_mesaformat destination image format
282 * @param[in] dst_pitch aligned destination image width
283 * @param[in] dst_width destination image width
284 * @param[in] dst_height destination image height
285 * @param[in] dst_x_offset x offset in the destination image
286 * @param[in] dst_y_offset y offset in the destination image
287 * @param[in] width region width
288 * @param[in] height region height
289 * @param[in] flip_y set if y coords of the source image need to be flipped
291 GLboolean
r200_blit(struct r200_context
*r200
,
292 struct radeon_bo
*src_bo
,
294 gl_format src_mesaformat
,
298 unsigned src_x_offset
,
299 unsigned src_y_offset
,
300 struct radeon_bo
*dst_bo
,
302 gl_format dst_mesaformat
,
306 unsigned dst_x_offset
,
307 unsigned dst_y_offset
,
312 if (_mesa_get_format_bits(src_mesaformat
, GL_DEPTH_BITS
) > 0)
315 /* Make sure that colorbuffer has even width - hw limitation */
316 if (dst_pitch
% 2 > 0)
319 /* Rendering to small buffer doesn't work.
320 * Looks like a hw limitation.
325 /* Need to clamp the region size to make sure
326 * we don't read outside of the source buffer
327 * or write outside of the destination buffer.
329 if (reg_width
+ src_x_offset
> src_width
)
330 reg_width
= src_width
- src_x_offset
;
331 if (reg_height
+ src_y_offset
> src_height
)
332 reg_height
= src_height
- src_y_offset
;
333 if (reg_width
+ dst_x_offset
> dst_width
)
334 reg_width
= dst_width
- dst_x_offset
;
335 if (reg_height
+ dst_y_offset
> dst_height
)
336 reg_height
= dst_height
- dst_y_offset
;
338 if (src_bo
== dst_bo
) {
343 fprintf(stderr
, "src: size [%d x %d], pitch %d, "
344 "offset [%d x %d], format %s, bo %p\n",
345 src_width
, src_height
, src_pitch
,
346 src_x_offset
, src_y_offset
,
347 _mesa_get_format_name(src_mesaformat
),
349 fprintf(stderr
, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
350 dst_pitch
, dst_x_offset
, dst_y_offset
,
351 _mesa_get_format_name(dst_mesaformat
), dst_bo
);
352 fprintf(stderr
, "region: %d x %d\n", reg_width
, reg_height
);
355 /* Flush is needed to make sure that source buffer has correct data */
356 radeonFlush(r200
->radeon
.glCtx
);
358 rcommonEnsureCmdBufSpace(&r200
->radeon
, 78, __FUNCTION__
);
360 if (!validate_buffers(r200
, src_bo
, dst_bo
))
364 emit_vtx_state(r200
);
366 emit_tx_setup(r200
, src_mesaformat
, src_bo
, src_offset
, src_width
, src_height
, src_pitch
);
368 emit_cb_setup(r200
, dst_bo
, dst_offset
, dst_mesaformat
, dst_pitch
, dst_width
, dst_height
);
370 emit_draw_packet(r200
, src_width
, src_height
,
371 src_x_offset
, src_y_offset
,
372 dst_x_offset
, dst_y_offset
,
373 reg_width
, reg_height
,
376 radeonFlush(r200
->radeon
.glCtx
);