2 * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "radeon_common.h"
29 #include "r200_context.h"
30 #include "r200_blit.h"
32 static inline uint32_t cmdpacket0(struct radeon_screen
*rscrn
,
36 return CP_PACKET0(reg
, count
- 1);
40 /* common formats supported as both textures and render targets */
41 unsigned r200_check_blit(gl_format mesa_format
)
43 /* XXX others? BE/LE? */
44 switch (mesa_format
) {
45 case MESA_FORMAT_ARGB8888
:
46 case MESA_FORMAT_XRGB8888
:
47 case MESA_FORMAT_RGB565
:
48 case MESA_FORMAT_ARGB4444
:
49 case MESA_FORMAT_ARGB1555
:
54 case MESA_FORMAT_RGBA8888
:
55 case MESA_FORMAT_RGBA8888_REV
:
62 if (_mesa_get_format_bits(mesa_format
, GL_DEPTH_BITS
) > 0)
68 static inline void emit_vtx_state(struct r200_context
*r200
)
70 BATCH_LOCALS(&r200
->radeon
);
73 if (r200
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
74 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS
, 0);
76 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS
, RADEON_TCL_BYPASS
);
78 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL
, (R200_VAP_FORCE_W_TO_ONE
|
79 (9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT
)));
80 OUT_BATCH_REGVAL(R200_SE_VTX_STATE_CNTL
, 0);
81 OUT_BATCH_REGVAL(R200_SE_VTE_CNTL
, 0);
82 OUT_BATCH_REGVAL(R200_SE_VTX_FMT_0
, R200_VTX_XY
);
83 OUT_BATCH_REGVAL(R200_SE_VTX_FMT_1
, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT
));
84 OUT_BATCH_REGVAL(RADEON_SE_CNTL
, (RADEON_DIFFUSE_SHADE_GOURAUD
|
87 RADEON_VTX_PIX_CENTER_OGL
|
88 RADEON_ROUND_MODE_ROUND
|
89 RADEON_ROUND_PREC_4TH_PIX
));
93 static void inline emit_tx_setup(struct r200_context
*r200
,
94 gl_format src_mesa_format
,
95 gl_format dst_mesa_format
,
102 uint32_t txformat
= R200_TXFORMAT_NON_POWER2
;
103 BATCH_LOCALS(&r200
->radeon
);
105 assert(width
<= 2047);
106 assert(height
<= 2047);
107 assert(offset
% 32 == 0);
109 /* XXX others? BE/LE? */
110 switch (src_mesa_format
) {
111 case MESA_FORMAT_ARGB8888
:
112 txformat
|= R200_TXFORMAT_ARGB8888
| R200_TXFORMAT_ALPHA_IN_MAP
;
114 case MESA_FORMAT_RGBA8888
:
115 txformat
|= R200_TXFORMAT_RGBA8888
| R200_TXFORMAT_ALPHA_IN_MAP
;
117 case MESA_FORMAT_RGBA8888_REV
:
118 txformat
|= R200_TXFORMAT_ABGR8888
| R200_TXFORMAT_ALPHA_IN_MAP
;
120 case MESA_FORMAT_XRGB8888
:
121 txformat
|= R200_TXFORMAT_ARGB8888
;
123 case MESA_FORMAT_RGB565
:
124 txformat
|= R200_TXFORMAT_RGB565
;
126 case MESA_FORMAT_ARGB4444
:
127 txformat
|= R200_TXFORMAT_ARGB4444
| R200_TXFORMAT_ALPHA_IN_MAP
;
129 case MESA_FORMAT_ARGB1555
:
130 txformat
|= R200_TXFORMAT_ARGB1555
| R200_TXFORMAT_ALPHA_IN_MAP
;
134 txformat
|= R200_TXFORMAT_I8
| R200_TXFORMAT_ALPHA_IN_MAP
;
137 txformat
|= R200_TXFORMAT_I8
;
139 case MESA_FORMAT_AL88
:
140 txformat
|= R200_TXFORMAT_AI88
| R200_TXFORMAT_ALPHA_IN_MAP
;
146 switch (dst_mesa_format
) {
147 case MESA_FORMAT_ARGB8888
:
148 case MESA_FORMAT_XRGB8888
:
149 case MESA_FORMAT_RGB565
:
150 case MESA_FORMAT_ARGB4444
:
151 case MESA_FORMAT_ARGB1555
:
156 /* no swizzle required */
158 OUT_BATCH_REGVAL(RADEON_PP_CNTL
, (RADEON_TEX_0_ENABLE
|
159 RADEON_TEX_BLEND_0_ENABLE
));
160 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0
, (R200_TXC_ARG_A_ZERO
|
161 R200_TXC_ARG_B_ZERO
|
162 R200_TXC_ARG_C_R0_COLOR
|
164 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0
, (R200_TXC_CLAMP_0_1
|
165 R200_TXC_OUTPUT_REG_R0
));
166 OUT_BATCH_REGVAL(R200_PP_TXABLEND_0
, (R200_TXA_ARG_A_ZERO
|
167 R200_TXA_ARG_B_ZERO
|
168 R200_TXA_ARG_C_R0_ALPHA
|
170 OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0
, (R200_TXA_CLAMP_0_1
|
171 R200_TXA_OUTPUT_REG_R0
));
174 case MESA_FORMAT_RGBA8888
:
176 OUT_BATCH_REGVAL(RADEON_PP_CNTL
, (RADEON_TEX_0_ENABLE
|
177 RADEON_TEX_BLEND_0_ENABLE
));
178 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0
, (R200_TXC_ARG_A_ZERO
|
179 R200_TXC_ARG_B_ZERO
|
180 R200_TXC_ARG_C_R0_COLOR
|
182 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0
, (R200_TXC_CLAMP_0_1
|
183 R200_TXC_OUTPUT_ROTATE_GBA
|
184 R200_TXC_OUTPUT_REG_R0
));
185 OUT_BATCH_REGVAL(R200_PP_TXABLEND_0
, (R200_TXA_ARG_A_ZERO
|
186 R200_TXA_ARG_B_ZERO
|
187 R200_TXA_ARG_C_R0_ALPHA
|
189 OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0
, (R200_TXA_CLAMP_0_1
|
190 (R200_TXA_REPL_RED
<< R200_TXA_REPL_ARG_C_SHIFT
) |
191 R200_TXA_OUTPUT_REG_R0
));
194 case MESA_FORMAT_RGBA8888_REV
:
196 OUT_BATCH_REGVAL(RADEON_PP_CNTL
, (RADEON_TEX_0_ENABLE
|
197 RADEON_TEX_BLEND_0_ENABLE
|
198 RADEON_TEX_BLEND_1_ENABLE
|
199 RADEON_TEX_BLEND_2_ENABLE
|
200 RADEON_TEX_BLEND_3_ENABLE
));
202 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0
, (R200_TXC_ARG_A_ZERO
|
203 R200_TXC_ARG_B_ZERO
|
204 R200_TXC_ARG_C_R0_COLOR
|
206 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0
, (R200_TXC_CLAMP_0_1
|
207 R200_TXC_OUTPUT_MASK_R
|
208 (R200_TXC_REPL_BLUE
<< R200_TXC_REPL_ARG_C_SHIFT
) |
209 R200_TXC_OUTPUT_REG_R1
));
211 OUT_BATCH_REGVAL(R200_PP_TXABLEND_0
, (R200_TXA_ARG_A_ZERO
|
212 R200_TXA_ARG_B_ZERO
|
213 R200_TXA_ARG_C_R0_ALPHA
|
215 OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0
, (R200_TXA_CLAMP_0_1
|
216 R200_TXA_OUTPUT_REG_R1
));
218 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_1
, (R200_TXC_ARG_A_ZERO
|
219 R200_TXC_ARG_B_ZERO
|
220 R200_TXC_ARG_C_R0_COLOR
|
222 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_1
, (R200_TXC_CLAMP_0_1
|
223 R200_TXC_OUTPUT_MASK_G
|
224 (R200_TXC_REPL_GREEN
<< R200_TXC_REPL_ARG_C_SHIFT
) |
225 R200_TXC_OUTPUT_REG_R1
));
227 OUT_BATCH_REGVAL(R200_PP_TXABLEND_1
, (R200_TXA_ARG_A_ZERO
|
228 R200_TXA_ARG_B_ZERO
|
229 R200_TXA_ARG_C_R0_ALPHA
|
231 OUT_BATCH_REGVAL(R200_PP_TXABLEND2_1
, (R200_TXA_CLAMP_0_1
|
232 R200_TXA_OUTPUT_REG_R1
));
234 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_2
, (R200_TXC_ARG_A_ZERO
|
235 R200_TXC_ARG_B_ZERO
|
236 R200_TXC_ARG_C_R0_COLOR
|
238 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_2
, (R200_TXC_CLAMP_0_1
|
239 R200_TXC_OUTPUT_MASK_B
|
240 (R200_TXC_REPL_RED
<< R200_TXC_REPL_ARG_C_SHIFT
) |
241 R200_TXC_OUTPUT_REG_R1
));
243 OUT_BATCH_REGVAL(R200_PP_TXABLEND_2
, (R200_TXA_ARG_A_ZERO
|
244 R200_TXA_ARG_B_ZERO
|
245 R200_TXA_ARG_C_R0_ALPHA
|
247 OUT_BATCH_REGVAL(R200_PP_TXABLEND2_2
, (R200_TXA_CLAMP_0_1
|
248 R200_TXA_OUTPUT_REG_R1
));
249 /* r0.rgb = r1.rgb */
250 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_3
, (R200_TXC_ARG_A_ZERO
|
251 R200_TXC_ARG_B_ZERO
|
252 R200_TXC_ARG_C_R1_COLOR
|
254 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_3
, (R200_TXC_CLAMP_0_1
|
255 R200_TXC_OUTPUT_REG_R0
));
257 OUT_BATCH_REGVAL(R200_PP_TXABLEND_3
, (R200_TXA_ARG_A_ZERO
|
258 R200_TXA_ARG_B_ZERO
|
259 R200_TXA_ARG_C_R1_ALPHA
|
261 OUT_BATCH_REGVAL(R200_PP_TXABLEND2_3
, (R200_TXA_CLAMP_0_1
|
262 R200_TXA_OUTPUT_REG_R0
));
268 OUT_BATCH_REGVAL(R200_PP_CNTL_X
, 0);
269 OUT_BATCH_REGVAL(R200_PP_TXMULTI_CTL_0
, 0);
270 OUT_BATCH_REGVAL(R200_PP_TXFILTER_0
, (R200_CLAMP_S_CLAMP_LAST
|
271 R200_CLAMP_T_CLAMP_LAST
|
272 R200_MAG_FILTER_NEAREST
|
273 R200_MIN_FILTER_NEAREST
));
274 OUT_BATCH_REGVAL(R200_PP_TXFORMAT_0
, txformat
);
275 OUT_BATCH_REGVAL(R200_PP_TXFORMAT_X_0
, 0);
276 OUT_BATCH_REGVAL(R200_PP_TXSIZE_0
, ((width
- 1) |
277 ((height
- 1) << RADEON_TEX_VSIZE_SHIFT
)));
278 OUT_BATCH_REGVAL(R200_PP_TXPITCH_0
, pitch
* _mesa_get_format_bytes(src_mesa_format
) - 32);
280 OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0
, 1);
281 OUT_BATCH_RELOC(0, bo
, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
286 static inline void emit_cb_setup(struct r200_context
*r200
,
287 struct radeon_bo
*bo
,
289 gl_format mesa_format
,
294 uint32_t dst_pitch
= pitch
;
295 uint32_t dst_format
= 0;
296 BATCH_LOCALS(&r200
->radeon
);
298 /* XXX others? BE/LE? */
299 switch (mesa_format
) {
300 case MESA_FORMAT_ARGB8888
:
301 case MESA_FORMAT_XRGB8888
:
302 case MESA_FORMAT_RGBA8888
:
303 case MESA_FORMAT_RGBA8888_REV
:
304 dst_format
= RADEON_COLOR_FORMAT_ARGB8888
;
306 case MESA_FORMAT_RGB565
:
307 dst_format
= RADEON_COLOR_FORMAT_RGB565
;
309 case MESA_FORMAT_ARGB4444
:
310 dst_format
= RADEON_COLOR_FORMAT_ARGB4444
;
312 case MESA_FORMAT_ARGB1555
:
313 dst_format
= RADEON_COLOR_FORMAT_ARGB1555
;
318 dst_format
= RADEON_COLOR_FORMAT_RGB8
;
324 BEGIN_BATCH_NO_AUTOSTATE(22);
325 OUT_BATCH_REGVAL(R200_RE_AUX_SCISSOR_CNTL
, 0);
326 OUT_BATCH_REGVAL(R200_RE_CNTL
, 0);
327 OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT
, 0);
328 OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT
, ((width
<< RADEON_RE_WIDTH_SHIFT
) |
329 (height
<< RADEON_RE_HEIGHT_SHIFT
)));
330 OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK
, 0xffffffff);
331 OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL
, RADEON_SRC_BLEND_GL_ONE
| RADEON_DST_BLEND_GL_ZERO
);
332 OUT_BATCH_REGVAL(RADEON_RB3D_CNTL
, dst_format
);
334 OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET
, 1);
335 OUT_BATCH_RELOC(0, bo
, 0, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0);
336 OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH
, 1);
337 OUT_BATCH_RELOC(dst_pitch
, bo
, dst_pitch
, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0);
342 static GLboolean
validate_buffers(struct r200_context
*r200
,
343 struct radeon_bo
*src_bo
,
344 struct radeon_bo
*dst_bo
)
348 radeon_cs_space_reset_bos(r200
->radeon
.cmdbuf
.cs
);
350 ret
= radeon_cs_space_check_with_bo(r200
->radeon
.cmdbuf
.cs
,
351 src_bo
, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
355 ret
= radeon_cs_space_check_with_bo(r200
->radeon
.cmdbuf
.cs
,
356 dst_bo
, 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
);
364 * Calculate texcoords for given image region.
365 * Output values are [minx, maxx, miny, maxy]
367 static inline void calc_tex_coords(float img_width
, float img_height
,
369 float reg_width
, float reg_height
,
370 unsigned flip_y
, float *buf
)
372 buf
[0] = x
/ img_width
;
373 buf
[1] = buf
[0] + reg_width
/ img_width
;
374 buf
[2] = y
/ img_height
;
375 buf
[3] = buf
[2] + reg_height
/ img_height
;
378 buf
[2] = 1.0 - buf
[2];
379 buf
[3] = 1.0 - buf
[3];
383 static inline void emit_draw_packet(struct r200_context
*r200
,
384 unsigned src_width
, unsigned src_height
,
385 unsigned src_x_offset
, unsigned src_y_offset
,
386 unsigned dst_x_offset
, unsigned dst_y_offset
,
387 unsigned reg_width
, unsigned reg_height
,
392 BATCH_LOCALS(&r200
->radeon
);
394 calc_tex_coords(src_width
, src_height
,
395 src_x_offset
, src_y_offset
,
396 reg_width
, reg_height
,
399 verts
[0] = dst_x_offset
;
400 verts
[1] = dst_y_offset
+ reg_height
;
401 verts
[2] = texcoords
[0];
402 verts
[3] = texcoords
[3];
404 verts
[4] = dst_x_offset
+ reg_width
;
405 verts
[5] = dst_y_offset
+ reg_height
;
406 verts
[6] = texcoords
[1];
407 verts
[7] = texcoords
[3];
409 verts
[8] = dst_x_offset
+ reg_width
;
410 verts
[9] = dst_y_offset
;
411 verts
[10] = texcoords
[1];
412 verts
[11] = texcoords
[2];
415 OUT_BATCH(R200_CP_CMD_3D_DRAW_IMMD_2
| (12 << 16));
416 OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING
|
417 RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST
|
419 OUT_BATCH_TABLE(verts
, 12);
424 * Copy a region of [@a width x @a height] pixels from source buffer
425 * to destination buffer.
426 * @param[in] r200 r200 context
427 * @param[in] src_bo source radeon buffer object
428 * @param[in] src_offset offset of the source image in the @a src_bo
429 * @param[in] src_mesaformat source image format
430 * @param[in] src_pitch aligned source image width
431 * @param[in] src_width source image width
432 * @param[in] src_height source image height
433 * @param[in] src_x_offset x offset in the source image
434 * @param[in] src_y_offset y offset in the source image
435 * @param[in] dst_bo destination radeon buffer object
436 * @param[in] dst_offset offset of the destination image in the @a dst_bo
437 * @param[in] dst_mesaformat destination image format
438 * @param[in] dst_pitch aligned destination image width
439 * @param[in] dst_width destination image width
440 * @param[in] dst_height destination image height
441 * @param[in] dst_x_offset x offset in the destination image
442 * @param[in] dst_y_offset y offset in the destination image
443 * @param[in] width region width
444 * @param[in] height region height
445 * @param[in] flip_y set if y coords of the source image need to be flipped
447 unsigned r200_blit(GLcontext
*ctx
,
448 struct radeon_bo
*src_bo
,
450 gl_format src_mesaformat
,
454 unsigned src_x_offset
,
455 unsigned src_y_offset
,
456 struct radeon_bo
*dst_bo
,
458 gl_format dst_mesaformat
,
462 unsigned dst_x_offset
,
463 unsigned dst_y_offset
,
468 struct r200_context
*r200
= R200_CONTEXT(ctx
);
470 if (!r200_check_blit(dst_mesaformat
))
473 /* Make sure that colorbuffer has even width - hw limitation */
474 if (dst_pitch
% 2 > 0)
477 /* Rendering to small buffer doesn't work.
478 * Looks like a hw limitation.
483 /* Need to clamp the region size to make sure
484 * we don't read outside of the source buffer
485 * or write outside of the destination buffer.
487 if (reg_width
+ src_x_offset
> src_width
)
488 reg_width
= src_width
- src_x_offset
;
489 if (reg_height
+ src_y_offset
> src_height
)
490 reg_height
= src_height
- src_y_offset
;
491 if (reg_width
+ dst_x_offset
> dst_width
)
492 reg_width
= dst_width
- dst_x_offset
;
493 if (reg_height
+ dst_y_offset
> dst_height
)
494 reg_height
= dst_height
- dst_y_offset
;
496 if (src_bo
== dst_bo
) {
500 if (src_offset
% 32 || dst_offset
% 32) {
505 fprintf(stderr
, "src: size [%d x %d], pitch %d, "
506 "offset [%d x %d], format %s, bo %p\n",
507 src_width
, src_height
, src_pitch
,
508 src_x_offset
, src_y_offset
,
509 _mesa_get_format_name(src_mesaformat
),
511 fprintf(stderr
, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
512 dst_pitch
, dst_x_offset
, dst_y_offset
,
513 _mesa_get_format_name(dst_mesaformat
), dst_bo
);
514 fprintf(stderr
, "region: %d x %d\n", reg_width
, reg_height
);
517 /* Flush is needed to make sure that source buffer has correct data */
518 radeonFlush(r200
->radeon
.glCtx
);
520 rcommonEnsureCmdBufSpace(&r200
->radeon
, 102, __FUNCTION__
);
522 if (!validate_buffers(r200
, src_bo
, dst_bo
))
526 emit_vtx_state(r200
);
528 emit_tx_setup(r200
, src_mesaformat
, dst_mesaformat
, src_bo
, src_offset
, src_width
, src_height
, src_pitch
);
530 emit_cb_setup(r200
, dst_bo
, dst_offset
, dst_mesaformat
, dst_pitch
, dst_width
, dst_height
);
532 emit_draw_packet(r200
, src_width
, src_height
,
533 src_x_offset
, src_y_offset
,
534 dst_x_offset
, dst_y_offset
,
535 reg_width
, reg_height
,