src/mesa/drivers/dri/r200/r200_blit.c

   1 /*
   2  * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_common.h"
  29 #include "r200_context.h"
  30 #include "r200_blit.h"
  31
  32 static inline uint32_t cmdpacket0(struct radeon_screen *rscrn,
  33                                   int reg, int count)
  34 {
  35     if (count)
  36             return CP_PACKET0(reg, count - 1);
  37     return CP_PACKET2;
  38 }
  39
  40 static inline void emit_vtx_state(struct r200_context *r200)
  41 {
  42     BATCH_LOCALS(&r200->radeon);
  43
  44     BEGIN_BATCH(14);
  45     if (r200->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
  46             OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, 0);
  47     } else {
  48             OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
  49     }
  50     OUT_BATCH_REGVAL(R200_SE_VAP_CNTL, (R200_VAP_FORCE_W_TO_ONE |
  51                                         (9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT)));
  52     OUT_BATCH_REGVAL(R200_SE_VTX_STATE_CNTL, 0);
  53     OUT_BATCH_REGVAL(R200_SE_VTE_CNTL, 0);
  54     OUT_BATCH_REGVAL(R200_SE_VTX_FMT_0, R200_VTX_XY);
  55     OUT_BATCH_REGVAL(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
  56     OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
  57                                       RADEON_BFACE_SOLID |
  58                                       RADEON_FFACE_SOLID |
  59                                       RADEON_VTX_PIX_CENTER_OGL |
  60                                       RADEON_ROUND_MODE_ROUND |
  61                                       RADEON_ROUND_PREC_4TH_PIX));
  62     END_BATCH();
  63 }
  64
  65 static void inline emit_tx_setup(struct r200_context *r200,
  66                                  gl_format mesa_format,
  67                                  struct radeon_bo *bo,
  68                                  intptr_t offset,
  69                                  unsigned width,
  70                                  unsigned height,
  71                                  unsigned pitch)
  72 {
  73     uint32_t txformat = R200_TXFORMAT_NON_POWER2;
  74     BATCH_LOCALS(&r200->radeon);
  75
  76     assert(width <= 2047);
  77     assert(height <= 2047);
  78     assert(offset % 32 == 0);
  79
  80     /* XXX others?  BE/LE? */
  81     switch (mesa_format) {
  82     case MESA_FORMAT_ARGB8888:
  83             txformat |= R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP;
  84             break;
  85     case MESA_FORMAT_XRGB8888:
  86             txformat |= R200_TXFORMAT_ARGB8888;
  87             break;
  88     case MESA_FORMAT_RGB565:
  89             txformat |= R200_TXFORMAT_RGB565;
  90             break;
  91     case MESA_FORMAT_ARGB1555:
  92             txformat |= R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP;
  93             break;
  94     case MESA_FORMAT_A8:
  95             txformat |= R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP;
  96             break;
  97     default:
  98             break;
  99     }
 100
 101     BEGIN_BATCH(28);
 102     OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
 103     OUT_BATCH_REGVAL(R200_PP_CNTL_X, 0);
 104     OUT_BATCH_REGVAL(R200_PP_TXMULTI_CTL_0, 0);
 105     OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
 106                                           R200_TXC_ARG_B_ZERO |
 107                                           R200_TXC_ARG_C_R0_COLOR |
 108                                           R200_TXC_OP_MADD));
 109     OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
 110     OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO |
 111                                           R200_TXA_ARG_B_ZERO |
 112                                           R200_TXA_ARG_C_R0_ALPHA |
 113                                           R200_TXA_OP_MADD));
 114     OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
 115     OUT_BATCH_REGVAL(R200_PP_TXFILTER_0, (R200_CLAMP_S_CLAMP_LAST |
 116                                           R200_CLAMP_T_CLAMP_LAST |
 117                                           R200_MAG_FILTER_NEAREST |
 118                                           R200_MIN_FILTER_NEAREST));
 119     OUT_BATCH_REGVAL(R200_PP_TXFORMAT_0, txformat);
 120     OUT_BATCH_REGVAL(R200_PP_TXFORMAT_X_0, 0);
 121     OUT_BATCH_REGVAL(R200_PP_TXSIZE_0, ((width - 1) |
 122                                         ((height - 1) << RADEON_TEX_VSIZE_SHIFT)));
 123     OUT_BATCH_REGVAL(R200_PP_TXPITCH_0, pitch - 32);
 124
 125     OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1);
 126     OUT_BATCH_RELOC(0, bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 127
 128     END_BATCH();
 129 }
 130
 131 static inline void emit_cb_setup(struct r200_context *r200,
 132                                  struct radeon_bo *bo,
 133                                  intptr_t offset,
 134                                  gl_format mesa_format,
 135                                  unsigned pitch,
 136                                  unsigned width,
 137                                  unsigned height)
 138 {
 139     uint32_t dst_pitch = pitch;
 140     uint32_t dst_format = 0;
 141     BATCH_LOCALS(&r200->radeon);
 142
 143     /* XXX others?  BE/LE? */
 144     switch (mesa_format) {
 145     case MESA_FORMAT_ARGB8888:
 146     case MESA_FORMAT_XRGB8888:
 147             dst_format = RADEON_COLOR_FORMAT_ARGB8888;
 148             break;
 149     case MESA_FORMAT_RGB565:
 150             dst_format = RADEON_COLOR_FORMAT_RGB565;
 151             break;
 152     case MESA_FORMAT_ARGB1555:
 153             dst_format = RADEON_COLOR_FORMAT_ARGB1555;
 154             break;
 155     case MESA_FORMAT_A8:
 156             dst_format = RADEON_COLOR_FORMAT_RGB8;
 157             break;
 158     default:
 159             break;
 160     }
 161
 162     BEGIN_BATCH_NO_AUTOSTATE(22);
 163     OUT_BATCH_REGVAL(R200_RE_AUX_SCISSOR_CNTL, 0);
 164     OUT_BATCH_REGVAL(R200_RE_CNTL, 0);
 165     OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0);
 166     OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, ((width << RADEON_RE_WIDTH_SHIFT) |
 167                                               (height << RADEON_RE_HEIGHT_SHIFT)));
 168     OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff);
 169     OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
 170     OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format);
 171
 172     OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1);
 173     OUT_BATCH_RELOC(0, bo, 0, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
 174     OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1);
 175     OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
 176
 177     END_BATCH();
 178 }
 179
 180 static GLboolean validate_buffers(struct r200_context *r200,
 181                                   struct radeon_bo *src_bo,
 182                                   struct radeon_bo *dst_bo)
 183 {
 184     int ret;
 185     radeon_cs_space_add_persistent_bo(r200->radeon.cmdbuf.cs,
 186                                       src_bo, RADEON_GEM_DOMAIN_VRAM, 0);
 187
 188     radeon_cs_space_add_persistent_bo(r200->radeon.cmdbuf.cs,
 189                                       dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
 190
 191     ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs,
 192                                         first_elem(&r200->radeon.dma.reserved)->bo,
 193                                         RADEON_GEM_DOMAIN_GTT, 0);
 194     if (ret)
 195         return GL_FALSE;
 196
 197     return GL_TRUE;
 198 }
 199
 200 /**
 201  * Calculate texcoords for given image region.
 202  * Output values are [minx, maxx, miny, maxy]
 203  */
 204 static inline void calc_tex_coords(float img_width, float img_height,
 205                                    float x, float y,
 206                                    float reg_width, float reg_height,
 207                                    unsigned flip_y, float *buf)
 208 {
 209     buf[0] = x / img_width;
 210     buf[1] = buf[0] + reg_width / img_width;
 211     buf[2] = y / img_height;
 212     buf[3] = buf[2] + reg_height / img_height;
 213     if (flip_y)
 214     {
 215         float tmp = buf[2];
 216         buf[2] = 1.0 - buf[3];
 217         buf[3] = 1.0 - tmp;
 218     }
 219 }
 220
 221 static inline void emit_draw_packet(struct r200_context *r200,
 222                                     unsigned src_width, unsigned src_height,
 223                                     unsigned src_x_offset, unsigned src_y_offset,
 224                                     unsigned dst_x_offset, unsigned dst_y_offset,
 225                                     unsigned reg_width, unsigned reg_height,
 226                                     unsigned flip_y)
 227 {
 228     float texcoords[4];
 229     float verts[12];
 230     BATCH_LOCALS(&r200->radeon);
 231
 232     calc_tex_coords(src_width, src_height,
 233                     src_x_offset, src_y_offset,
 234                     reg_width, reg_height,
 235                     flip_y, texcoords);
 236
 237     verts[0] = dst_x_offset;
 238     verts[1] = dst_y_offset + reg_height;
 239     verts[2] = texcoords[0];
 240     verts[3] = texcoords[2];
 241
 242     verts[4] = dst_x_offset + reg_width;
 243     verts[5] = dst_y_offset + reg_height;
 244     verts[6] = texcoords[1];
 245     verts[7] = texcoords[2];
 246
 247     verts[8] = dst_x_offset + reg_width;
 248     verts[9] = dst_y_offset;
 249     verts[10] = texcoords[1];
 250     verts[11] = texcoords[3];
 251
 252     BEGIN_BATCH(14);
 253     OUT_BATCH(R200_CP_CMD_3D_DRAW_IMMD_2 | (12 << 16));
 254     OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING |
 255               RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
 256               (3 << 16));
 257     OUT_BATCH_TABLE(verts, 12);
 258     END_BATCH();
 259 }
 260
 261 /**
 262  * Copy a region of [@a width x @a height] pixels from source buffer
 263  * to destination buffer.
 264  * @param[in] r200 r200 context
 265  * @param[in] src_bo source radeon buffer object
 266  * @param[in] src_offset offset of the source image in the @a src_bo
 267  * @param[in] src_mesaformat source image format
 268  * @param[in] src_pitch aligned source image width
 269  * @param[in] src_width source image width
 270  * @param[in] src_height source image height
 271  * @param[in] src_x_offset x offset in the source image
 272  * @param[in] src_y_offset y offset in the source image
 273  * @param[in] dst_bo destination radeon buffer object
 274  * @param[in] dst_offset offset of the destination image in the @a dst_bo
 275  * @param[in] dst_mesaformat destination image format
 276  * @param[in] dst_pitch aligned destination image width
 277  * @param[in] dst_width destination image width
 278  * @param[in] dst_height destination image height
 279  * @param[in] dst_x_offset x offset in the destination image
 280  * @param[in] dst_y_offset y offset in the destination image
 281  * @param[in] width region width
 282  * @param[in] height region height
 283  * @param[in] flip_y set if y coords of the source image need to be flipped
 284  */
 285 GLboolean r200_blit(struct r200_context *r200,
 286                     struct radeon_bo *src_bo,
 287                     intptr_t src_offset,
 288                     gl_format src_mesaformat,
 289                     unsigned src_pitch,
 290                     unsigned src_width,
 291                     unsigned src_height,
 292                     unsigned src_x_offset,
 293                     unsigned src_y_offset,
 294                     struct radeon_bo *dst_bo,
 295                     intptr_t dst_offset,
 296                     gl_format dst_mesaformat,
 297                     unsigned dst_pitch,
 298                     unsigned dst_width,
 299                     unsigned dst_height,
 300                     unsigned dst_x_offset,
 301                     unsigned dst_y_offset,
 302                     unsigned reg_width,
 303                     unsigned reg_height,
 304                     unsigned flip_y)
 305 {
 306     if (_mesa_get_format_bits(src_mesaformat, GL_DEPTH_BITS) > 0)
 307         return GL_FALSE;
 308
 309     /* Make sure that colorbuffer has even width - hw limitation */
 310     if (dst_pitch % 2 > 0)
 311         ++dst_pitch;
 312
 313     /* Rendering to small buffer doesn't work.
 314      * Looks like a hw limitation.
 315      */
 316     if (dst_pitch < 32)
 317         return GL_FALSE;
 318
 319     /* Need to clamp the region size to make sure
 320      * we don't read outside of the source buffer
 321      * or write outside of the destination buffer.
 322      */
 323     if (reg_width + src_x_offset > src_width)
 324         reg_width = src_width - src_x_offset;
 325     if (reg_height + src_y_offset > src_height)
 326         reg_height = src_height - src_y_offset;
 327     if (reg_width + dst_x_offset > dst_width)
 328         reg_width = dst_width - dst_x_offset;
 329     if (reg_height + dst_y_offset > dst_height)
 330         reg_height = dst_height - dst_y_offset;
 331
 332     if (src_bo == dst_bo) {
 333         return GL_FALSE;
 334     }
 335
 336     if (0) {
 337         fprintf(stderr, "src: size [%d x %d], pitch %d, "
 338                 "offset [%d x %d], format %s, bo %p\n",
 339                 src_width, src_height, src_pitch,
 340                 src_x_offset, src_y_offset,
 341                 _mesa_get_format_name(src_mesaformat),
 342                 src_bo);
 343         fprintf(stderr, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
 344                 dst_pitch, dst_x_offset, dst_y_offset,
 345                 _mesa_get_format_name(dst_mesaformat), dst_bo);
 346         fprintf(stderr, "region: %d x %d\n", reg_width, reg_height);
 347     }
 348
 349     /* Flush is needed to make sure that source buffer has correct data */
 350     radeonFlush(r200->radeon.glCtx);
 351
 352     rcommonEnsureCmdBufSpace(&r200->radeon, 78, __FUNCTION__);
 353
 354     if (!validate_buffers(r200, src_bo, dst_bo))
 355         return GL_FALSE;
 356
 357     /* 14 */
 358     emit_vtx_state(r200);
 359     /* 28 */
 360     emit_tx_setup(r200, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
 361     /* 22 */
 362     emit_cb_setup(r200, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);
 363     /* 14 */
 364     emit_draw_packet(r200, src_width, src_height,
 365                      src_x_offset, src_y_offset,
 366                      dst_x_offset, dst_y_offset,
 367                      reg_width, reg_height,
 368                      flip_y);
 369
 370     radeonFlush(r200->radeon.glCtx);
 371
 372     return GL_TRUE;
 373 }