2 * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "radeon_common.h"
29 #include "r200_context.h"
30 #include "r200_blit.h"
32 static inline uint32_t cmdpacket0(struct radeon_screen
*rscrn
,
36 return CP_PACKET0(reg
, count
- 1);
40 /* common formats supported as both textures and render targets */
41 unsigned r200_check_blit(gl_format mesa_format
)
43 /* XXX others? BE/LE? */
44 switch (mesa_format
) {
45 case MESA_FORMAT_ARGB8888
:
46 case MESA_FORMAT_XRGB8888
:
47 case MESA_FORMAT_RGB565
:
48 case MESA_FORMAT_ARGB4444
:
49 case MESA_FORMAT_ARGB1555
:
57 if (_mesa_get_format_bits(mesa_format
, GL_DEPTH_BITS
) > 0)
63 static inline void emit_vtx_state(struct r200_context
*r200
)
65 BATCH_LOCALS(&r200
->radeon
);
68 if (r200
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
69 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS
, 0);
71 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS
, RADEON_TCL_BYPASS
);
73 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL
, (R200_VAP_FORCE_W_TO_ONE
|
74 (9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT
)));
75 OUT_BATCH_REGVAL(R200_SE_VTX_STATE_CNTL
, 0);
76 OUT_BATCH_REGVAL(R200_SE_VTE_CNTL
, 0);
77 OUT_BATCH_REGVAL(R200_SE_VTX_FMT_0
, R200_VTX_XY
);
78 OUT_BATCH_REGVAL(R200_SE_VTX_FMT_1
, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT
));
79 OUT_BATCH_REGVAL(RADEON_SE_CNTL
, (RADEON_DIFFUSE_SHADE_GOURAUD
|
82 RADEON_VTX_PIX_CENTER_OGL
|
83 RADEON_ROUND_MODE_ROUND
|
84 RADEON_ROUND_PREC_4TH_PIX
));
88 static void inline emit_tx_setup(struct r200_context
*r200
,
89 gl_format mesa_format
,
96 uint32_t txformat
= R200_TXFORMAT_NON_POWER2
;
97 BATCH_LOCALS(&r200
->radeon
);
99 assert(width
<= 2047);
100 assert(height
<= 2047);
101 assert(offset
% 32 == 0);
103 /* XXX others? BE/LE? */
104 switch (mesa_format
) {
105 case MESA_FORMAT_ARGB8888
:
106 txformat
|= R200_TXFORMAT_ARGB8888
| R200_TXFORMAT_ALPHA_IN_MAP
;
108 case MESA_FORMAT_XRGB8888
:
109 txformat
|= R200_TXFORMAT_ARGB8888
;
111 case MESA_FORMAT_RGB565
:
112 txformat
|= R200_TXFORMAT_RGB565
;
114 case MESA_FORMAT_ARGB4444
:
115 txformat
|= R200_TXFORMAT_ARGB4444
| R200_TXFORMAT_ALPHA_IN_MAP
;
117 case MESA_FORMAT_ARGB1555
:
118 txformat
|= R200_TXFORMAT_ARGB1555
| R200_TXFORMAT_ALPHA_IN_MAP
;
121 txformat
|= R200_TXFORMAT_I8
| R200_TXFORMAT_ALPHA_IN_MAP
;
128 OUT_BATCH_REGVAL(RADEON_PP_CNTL
, RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
);
129 OUT_BATCH_REGVAL(R200_PP_CNTL_X
, 0);
130 OUT_BATCH_REGVAL(R200_PP_TXMULTI_CTL_0
, 0);
131 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0
, (R200_TXC_ARG_A_ZERO
|
132 R200_TXC_ARG_B_ZERO
|
133 R200_TXC_ARG_C_R0_COLOR
|
135 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0
, R200_TXC_CLAMP_0_1
| R200_TXC_OUTPUT_REG_R0
);
136 OUT_BATCH_REGVAL(R200_PP_TXABLEND_0
, (R200_TXA_ARG_A_ZERO
|
137 R200_TXA_ARG_B_ZERO
|
138 R200_TXA_ARG_C_R0_ALPHA
|
140 OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0
, R200_TXA_CLAMP_0_1
| R200_TXA_OUTPUT_REG_R0
);
141 OUT_BATCH_REGVAL(R200_PP_TXFILTER_0
, (R200_CLAMP_S_CLAMP_LAST
|
142 R200_CLAMP_T_CLAMP_LAST
|
143 R200_MAG_FILTER_NEAREST
|
144 R200_MIN_FILTER_NEAREST
));
145 OUT_BATCH_REGVAL(R200_PP_TXFORMAT_0
, txformat
);
146 OUT_BATCH_REGVAL(R200_PP_TXFORMAT_X_0
, 0);
147 OUT_BATCH_REGVAL(R200_PP_TXSIZE_0
, ((width
- 1) |
148 ((height
- 1) << RADEON_TEX_VSIZE_SHIFT
)));
149 OUT_BATCH_REGVAL(R200_PP_TXPITCH_0
, pitch
* _mesa_get_format_bytes(mesa_format
) - 32);
151 OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0
, 1);
152 OUT_BATCH_RELOC(0, bo
, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
157 static inline void emit_cb_setup(struct r200_context
*r200
,
158 struct radeon_bo
*bo
,
160 gl_format mesa_format
,
165 uint32_t dst_pitch
= pitch
;
166 uint32_t dst_format
= 0;
167 BATCH_LOCALS(&r200
->radeon
);
169 /* XXX others? BE/LE? */
170 switch (mesa_format
) {
171 case MESA_FORMAT_ARGB8888
:
172 case MESA_FORMAT_XRGB8888
:
173 dst_format
= RADEON_COLOR_FORMAT_ARGB8888
;
175 case MESA_FORMAT_RGB565
:
176 dst_format
= RADEON_COLOR_FORMAT_RGB565
;
178 case MESA_FORMAT_ARGB4444
:
179 dst_format
= RADEON_COLOR_FORMAT_ARGB4444
;
181 case MESA_FORMAT_ARGB1555
:
182 dst_format
= RADEON_COLOR_FORMAT_ARGB1555
;
185 dst_format
= RADEON_COLOR_FORMAT_RGB8
;
191 BEGIN_BATCH_NO_AUTOSTATE(22);
192 OUT_BATCH_REGVAL(R200_RE_AUX_SCISSOR_CNTL
, 0);
193 OUT_BATCH_REGVAL(R200_RE_CNTL
, 0);
194 OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT
, 0);
195 OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT
, ((width
<< RADEON_RE_WIDTH_SHIFT
) |
196 (height
<< RADEON_RE_HEIGHT_SHIFT
)));
197 OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK
, 0xffffffff);
198 OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL
, RADEON_SRC_BLEND_GL_ONE
| RADEON_DST_BLEND_GL_ZERO
);
199 OUT_BATCH_REGVAL(RADEON_RB3D_CNTL
, dst_format
);
201 OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET
, 1);
202 OUT_BATCH_RELOC(0, bo
, 0, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0);
203 OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH
, 1);
204 OUT_BATCH_RELOC(dst_pitch
, bo
, dst_pitch
, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0);
209 static GLboolean
validate_buffers(struct r200_context
*r200
,
210 struct radeon_bo
*src_bo
,
211 struct radeon_bo
*dst_bo
)
215 radeon_cs_space_reset_bos(r200
->radeon
.cmdbuf
.cs
);
217 ret
= radeon_cs_space_check_with_bo(r200
->radeon
.cmdbuf
.cs
,
218 src_bo
, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
222 ret
= radeon_cs_space_check_with_bo(r200
->radeon
.cmdbuf
.cs
,
223 dst_bo
, 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
);
231 * Calculate texcoords for given image region.
232 * Output values are [minx, maxx, miny, maxy]
234 static inline void calc_tex_coords(float img_width
, float img_height
,
236 float reg_width
, float reg_height
,
237 unsigned flip_y
, float *buf
)
239 buf
[0] = x
/ img_width
;
240 buf
[1] = buf
[0] + reg_width
/ img_width
;
241 buf
[2] = y
/ img_height
;
242 buf
[3] = buf
[2] + reg_height
/ img_height
;
245 buf
[2] = 1.0 - buf
[2];
246 buf
[3] = 1.0 - buf
[3];
250 static inline void emit_draw_packet(struct r200_context
*r200
,
251 unsigned src_width
, unsigned src_height
,
252 unsigned src_x_offset
, unsigned src_y_offset
,
253 unsigned dst_x_offset
, unsigned dst_y_offset
,
254 unsigned reg_width
, unsigned reg_height
,
259 BATCH_LOCALS(&r200
->radeon
);
261 calc_tex_coords(src_width
, src_height
,
262 src_x_offset
, src_y_offset
,
263 reg_width
, reg_height
,
266 verts
[0] = dst_x_offset
;
267 verts
[1] = dst_y_offset
+ reg_height
;
268 verts
[2] = texcoords
[0];
269 verts
[3] = texcoords
[3];
271 verts
[4] = dst_x_offset
+ reg_width
;
272 verts
[5] = dst_y_offset
+ reg_height
;
273 verts
[6] = texcoords
[1];
274 verts
[7] = texcoords
[3];
276 verts
[8] = dst_x_offset
+ reg_width
;
277 verts
[9] = dst_y_offset
;
278 verts
[10] = texcoords
[1];
279 verts
[11] = texcoords
[2];
282 OUT_BATCH(R200_CP_CMD_3D_DRAW_IMMD_2
| (12 << 16));
283 OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING
|
284 RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST
|
286 OUT_BATCH_TABLE(verts
, 12);
291 * Copy a region of [@a width x @a height] pixels from source buffer
292 * to destination buffer.
293 * @param[in] r200 r200 context
294 * @param[in] src_bo source radeon buffer object
295 * @param[in] src_offset offset of the source image in the @a src_bo
296 * @param[in] src_mesaformat source image format
297 * @param[in] src_pitch aligned source image width
298 * @param[in] src_width source image width
299 * @param[in] src_height source image height
300 * @param[in] src_x_offset x offset in the source image
301 * @param[in] src_y_offset y offset in the source image
302 * @param[in] dst_bo destination radeon buffer object
303 * @param[in] dst_offset offset of the destination image in the @a dst_bo
304 * @param[in] dst_mesaformat destination image format
305 * @param[in] dst_pitch aligned destination image width
306 * @param[in] dst_width destination image width
307 * @param[in] dst_height destination image height
308 * @param[in] dst_x_offset x offset in the destination image
309 * @param[in] dst_y_offset y offset in the destination image
310 * @param[in] width region width
311 * @param[in] height region height
312 * @param[in] flip_y set if y coords of the source image need to be flipped
314 unsigned r200_blit(GLcontext
*ctx
,
315 struct radeon_bo
*src_bo
,
317 gl_format src_mesaformat
,
321 unsigned src_x_offset
,
322 unsigned src_y_offset
,
323 struct radeon_bo
*dst_bo
,
325 gl_format dst_mesaformat
,
329 unsigned dst_x_offset
,
330 unsigned dst_y_offset
,
335 struct r200_context
*r200
= R200_CONTEXT(ctx
);
337 if (!r200_check_blit(dst_mesaformat
))
340 /* Make sure that colorbuffer has even width - hw limitation */
341 if (dst_pitch
% 2 > 0)
344 /* Rendering to small buffer doesn't work.
345 * Looks like a hw limitation.
350 /* Need to clamp the region size to make sure
351 * we don't read outside of the source buffer
352 * or write outside of the destination buffer.
354 if (reg_width
+ src_x_offset
> src_width
)
355 reg_width
= src_width
- src_x_offset
;
356 if (reg_height
+ src_y_offset
> src_height
)
357 reg_height
= src_height
- src_y_offset
;
358 if (reg_width
+ dst_x_offset
> dst_width
)
359 reg_width
= dst_width
- dst_x_offset
;
360 if (reg_height
+ dst_y_offset
> dst_height
)
361 reg_height
= dst_height
- dst_y_offset
;
363 if (src_bo
== dst_bo
) {
367 if (src_offset
% 32 || dst_offset
% 32) {
372 fprintf(stderr
, "src: size [%d x %d], pitch %d, "
373 "offset [%d x %d], format %s, bo %p\n",
374 src_width
, src_height
, src_pitch
,
375 src_x_offset
, src_y_offset
,
376 _mesa_get_format_name(src_mesaformat
),
378 fprintf(stderr
, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
379 dst_pitch
, dst_x_offset
, dst_y_offset
,
380 _mesa_get_format_name(dst_mesaformat
), dst_bo
);
381 fprintf(stderr
, "region: %d x %d\n", reg_width
, reg_height
);
384 /* Flush is needed to make sure that source buffer has correct data */
385 radeonFlush(r200
->radeon
.glCtx
);
387 rcommonEnsureCmdBufSpace(&r200
->radeon
, 78, __FUNCTION__
);
389 if (!validate_buffers(r200
, src_bo
, dst_bo
))
393 emit_vtx_state(r200
);
395 emit_tx_setup(r200
, src_mesaformat
, src_bo
, src_offset
, src_width
, src_height
, src_pitch
);
397 emit_cb_setup(r200
, dst_bo
, dst_offset
, dst_mesaformat
, dst_pitch
, dst_width
, dst_height
);
399 emit_draw_packet(r200
, src_width
, src_height
,
400 src_x_offset
, src_y_offset
,
401 dst_x_offset
, dst_y_offset
,
402 reg_width
, reg_height
,