src/mesa/drivers/dri/r200/r200_blit.c

   1 /*
   2  * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_common.h"
  29 #include "r200_context.h"
  30 #include "r200_blit.h"
  31 #include "r200_tex.h"
  32
  33 static inline uint32_t cmdpacket0(struct radeon_screen *rscrn,
  34                                   int reg, int count)
  35 {
  36     if (count)
  37             return CP_PACKET0(reg, count - 1);
  38     return CP_PACKET2;
  39 }
  40
  41 /* common formats supported as both textures and render targets */
  42 unsigned r200_check_blit(mesa_format mesa_format, uint32_t dst_pitch)
  43 {
  44     /* XXX others? */
  45     switch (mesa_format) {
  46 #if UTIL_ARCH_LITTLE_ENDIAN
  47     case MESA_FORMAT_B8G8R8A8_UNORM:
  48     case MESA_FORMAT_B8G8R8X8_UNORM:
  49     case MESA_FORMAT_B5G6R5_UNORM:
  50     case MESA_FORMAT_B4G4R4A4_UNORM:
  51     case MESA_FORMAT_B5G5R5A1_UNORM:
  52 #else
  53     case MESA_FORMAT_A8R8G8B8_UNORM:
  54     case MESA_FORMAT_X8R8G8B8_UNORM:
  55     case MESA_FORMAT_R5G6B5_UNORM:
  56     case MESA_FORMAT_A4R4G4B4_UNORM:
  57     case MESA_FORMAT_A1R5G5B5_UNORM:
  58 #endif
  59     case MESA_FORMAT_A_UNORM8:
  60     case MESA_FORMAT_L_UNORM8:
  61     case MESA_FORMAT_I_UNORM8:
  62     /* swizzled - probably can't happen with the disabled Choose8888TexFormat code */
  63     case MESA_FORMAT_A8B8G8R8_UNORM:
  64     case MESA_FORMAT_R8G8B8A8_UNORM:
  65         break;
  66     default:
  67         return 0;
  68     }
  69
  70     /* Rendering to small buffer doesn't work.
  71      * Looks like a hw limitation.
  72      */
  73     if (dst_pitch < 32)
  74             return 0;
  75
  76     /* ??? */
  77     if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0)
  78             return 0;
  79
  80     return 1;
  81 }
  82
  83 static inline void emit_vtx_state(struct r200_context *r200)
  84 {
  85     BATCH_LOCALS(&r200->radeon);
  86
  87     BEGIN_BATCH(14);
  88     if (r200->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
  89             OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, 0);
  90     } else {
  91             OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
  92     }
  93     OUT_BATCH_REGVAL(R200_SE_VAP_CNTL, (R200_VAP_FORCE_W_TO_ONE |
  94                                         (9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT)));
  95     OUT_BATCH_REGVAL(R200_SE_VTX_STATE_CNTL, 0);
  96     OUT_BATCH_REGVAL(R200_SE_VTE_CNTL, 0);
  97     OUT_BATCH_REGVAL(R200_SE_VTX_FMT_0, R200_VTX_XY);
  98     OUT_BATCH_REGVAL(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
  99     OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
 100                                       RADEON_BFACE_SOLID |
 101                                       RADEON_FFACE_SOLID |
 102                                       RADEON_VTX_PIX_CENTER_OGL |
 103                                       RADEON_ROUND_MODE_ROUND |
 104                                       RADEON_ROUND_PREC_4TH_PIX));
 105     END_BATCH();
 106 }
 107
 108 static void inline emit_tx_setup(struct r200_context *r200,
 109                                  mesa_format src_mesa_format,
 110                                  mesa_format dst_mesa_format,
 111                                  struct radeon_bo *bo,
 112                                  intptr_t offset,
 113                                  unsigned width,
 114                                  unsigned height,
 115                                  unsigned pitch)
 116 {
 117     uint32_t txformat = R200_TXFORMAT_NON_POWER2;
 118     BATCH_LOCALS(&r200->radeon);
 119
 120     assert(width <= 2048);
 121     assert(height <= 2048);
 122     assert(offset % 32 == 0);
 123
 124 #if UTIL_ARCH_LITTLE_ENDIAN
 125     txformat |= tx_table_le[src_mesa_format].format;
 126 #else
 127     txformat |= tx_table_be[src_mesa_format].format;
 128 #endif
 129
 130     if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 131         offset |= R200_TXO_MACRO_TILE;
 132     if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
 133         offset |= R200_TXO_MICRO_TILE;
 134
 135     switch (dst_mesa_format) {
 136     /* le */
 137     case MESA_FORMAT_B8G8R8A8_UNORM:
 138     case MESA_FORMAT_B8G8R8X8_UNORM:
 139     case MESA_FORMAT_B5G6R5_UNORM:
 140     case MESA_FORMAT_B4G4R4A4_UNORM:
 141     case MESA_FORMAT_B5G5R5A1_UNORM:
 142     /* be */
 143     case MESA_FORMAT_A8R8G8B8_UNORM:
 144     case MESA_FORMAT_X8R8G8B8_UNORM:
 145     case MESA_FORMAT_R5G6B5_UNORM:
 146     case MESA_FORMAT_A4R4G4B4_UNORM:
 147     case MESA_FORMAT_A1R5G5B5_UNORM:
 148     /* little and big */
 149     case MESA_FORMAT_A_UNORM8:
 150     case MESA_FORMAT_L_UNORM8:
 151     case MESA_FORMAT_I_UNORM8:
 152     default:
 153             /* no swizzle required */
 154             BEGIN_BATCH(10);
 155             OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
 156                                               RADEON_TEX_BLEND_0_ENABLE));
 157             OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
 158                                                   R200_TXC_ARG_B_ZERO |
 159                                                   R200_TXC_ARG_C_R0_COLOR |
 160                                                   R200_TXC_OP_MADD));
 161             OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
 162                                                    R200_TXC_OUTPUT_REG_R0));
 163             OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO |
 164                                                   R200_TXA_ARG_B_ZERO |
 165                                                   R200_TXA_ARG_C_R0_ALPHA |
 166                                                   R200_TXA_OP_MADD));
 167             OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 |
 168                                                    R200_TXA_OUTPUT_REG_R0));
 169             END_BATCH();
 170             break;
 171     case MESA_FORMAT_A8B8G8R8_UNORM:
 172     case MESA_FORMAT_R8G8B8A8_UNORM:
 173 #if UTIL_ARCH_LITTLE_ENDIAN
 174        if (dst_mesa_format == MESA_FORMAT_A8B8G8R8_UNORM) {
 175 #else
 176        if (dst_mesa_format == MESA_FORMAT_R8G8B8A8_UNORM) {
 177 #endif
 178             BEGIN_BATCH(10);
 179             OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
 180                                               RADEON_TEX_BLEND_0_ENABLE));
 181             OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
 182                                                   R200_TXC_ARG_B_ZERO |
 183                                                   R200_TXC_ARG_C_R0_COLOR |
 184                                                   R200_TXC_OP_MADD));
 185             /* XXX I don't think this can work. This is output rotation, and alpha contains
 186              * red, not alpha (we'd write gbrr). */
 187             OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
 188                                                    R200_TXC_OUTPUT_ROTATE_GBA |
 189                                                    R200_TXC_OUTPUT_REG_R0));
 190             OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO |
 191                                                   R200_TXA_ARG_B_ZERO |
 192                                                   R200_TXA_ARG_C_R0_ALPHA |
 193                                                   R200_TXA_OP_MADD));
 194             OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 |
 195                                                    (R200_TXA_REPL_RED << R200_TXA_REPL_ARG_C_SHIFT) |
 196                                                    R200_TXA_OUTPUT_REG_R0));
 197             END_BATCH();
 198        }
 199        else {
 200             /* XXX pretty sure could do this with just 2 instead of 4 instructions.
 201              * Like so:
 202              * 1st: use RGA output rotation, rgb arg replicate b, a arg r, write mask rb.
 203              * That's just one instruction in fact but I'm not entirely sure it works
 204              * if some of those incoming r0 components are never written (due to mask)
 205              * in the shader itself to r0.
 206              * In any case this case (and the one above) may not be reachable with
 207              * disabled Choose8888TexFormat code. */
 208             BEGIN_BATCH(34);
 209             OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
 210                                               RADEON_TEX_BLEND_0_ENABLE |
 211                                               RADEON_TEX_BLEND_1_ENABLE |
 212                                               RADEON_TEX_BLEND_2_ENABLE |
 213                                               RADEON_TEX_BLEND_3_ENABLE));
 214             /* r1.r = r0.b */
 215             OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
 216                                                   R200_TXC_ARG_B_ZERO |
 217                                                   R200_TXC_ARG_C_R0_COLOR |
 218                                                   R200_TXC_OP_MADD));
 219             OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
 220                                                    R200_TXC_OUTPUT_MASK_R |
 221                                                    (R200_TXC_REPL_BLUE << R200_TXC_REPL_ARG_C_SHIFT) |
 222                                                    R200_TXC_OUTPUT_REG_R1));
 223             /* r1.a = r0.a */
 224             OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO |
 225                                                   R200_TXA_ARG_B_ZERO |
 226                                                   R200_TXA_ARG_C_R0_ALPHA |
 227                                                   R200_TXA_OP_MADD));
 228             OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 |
 229                                                    R200_TXA_OUTPUT_REG_R1));
 230             /* r1.g = r0.g */
 231             OUT_BATCH_REGVAL(R200_PP_TXCBLEND_1, (R200_TXC_ARG_A_ZERO |
 232                                                   R200_TXC_ARG_B_ZERO |
 233                                                   R200_TXC_ARG_C_R0_COLOR |
 234                                                   R200_TXC_OP_MADD));
 235             OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_1, (R200_TXC_CLAMP_0_1 |
 236                                                    R200_TXC_OUTPUT_MASK_G |
 237                                                    (R200_TXC_REPL_GREEN << R200_TXC_REPL_ARG_C_SHIFT) |
 238                                                    R200_TXC_OUTPUT_REG_R1));
 239             /* r1.a = r0.a */
 240             OUT_BATCH_REGVAL(R200_PP_TXABLEND_1, (R200_TXA_ARG_A_ZERO |
 241                                                   R200_TXA_ARG_B_ZERO |
 242                                                   R200_TXA_ARG_C_R0_ALPHA |
 243                                                   R200_TXA_OP_MADD));
 244             OUT_BATCH_REGVAL(R200_PP_TXABLEND2_1, (R200_TXA_CLAMP_0_1 |
 245                                                    R200_TXA_OUTPUT_REG_R1));
 246             /* r1.b = r0.r */
 247             OUT_BATCH_REGVAL(R200_PP_TXCBLEND_2, (R200_TXC_ARG_A_ZERO |
 248                                                   R200_TXC_ARG_B_ZERO |
 249                                                   R200_TXC_ARG_C_R0_COLOR |
 250                                                   R200_TXC_OP_MADD));
 251             OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_2, (R200_TXC_CLAMP_0_1 |
 252                                                    R200_TXC_OUTPUT_MASK_B |
 253                                                    (R200_TXC_REPL_RED << R200_TXC_REPL_ARG_C_SHIFT) |
 254                                                    R200_TXC_OUTPUT_REG_R1));
 255             /* r1.a = r0.a */
 256             OUT_BATCH_REGVAL(R200_PP_TXABLEND_2, (R200_TXA_ARG_A_ZERO |
 257                                                   R200_TXA_ARG_B_ZERO |
 258                                                   R200_TXA_ARG_C_R0_ALPHA |
 259                                                   R200_TXA_OP_MADD));
 260             OUT_BATCH_REGVAL(R200_PP_TXABLEND2_2, (R200_TXA_CLAMP_0_1 |
 261                                                    R200_TXA_OUTPUT_REG_R1));
 262             /* r0.rgb = r1.rgb */
 263             OUT_BATCH_REGVAL(R200_PP_TXCBLEND_3, (R200_TXC_ARG_A_ZERO |
 264                                                   R200_TXC_ARG_B_ZERO |
 265                                                   R200_TXC_ARG_C_R1_COLOR |
 266                                                   R200_TXC_OP_MADD));
 267             OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_3, (R200_TXC_CLAMP_0_1 |
 268                                                    R200_TXC_OUTPUT_REG_R0));
 269             /* r0.a = r1.a */
 270             OUT_BATCH_REGVAL(R200_PP_TXABLEND_3, (R200_TXA_ARG_A_ZERO |
 271                                                   R200_TXA_ARG_B_ZERO |
 272                                                   R200_TXA_ARG_C_R1_ALPHA |
 273                                                   R200_TXA_OP_MADD));
 274             OUT_BATCH_REGVAL(R200_PP_TXABLEND2_3, (R200_TXA_CLAMP_0_1 |
 275                                                    R200_TXA_OUTPUT_REG_R0));
 276             END_BATCH();
 277         }
 278         break;
 279     }
 280
 281     BEGIN_BATCH(18);
 282     OUT_BATCH_REGVAL(R200_PP_CNTL_X, 0);
 283     OUT_BATCH_REGVAL(R200_PP_TXMULTI_CTL_0, 0);
 284     OUT_BATCH_REGVAL(R200_PP_TXFILTER_0, (R200_CLAMP_S_CLAMP_LAST |
 285                                           R200_CLAMP_T_CLAMP_LAST |
 286                                           R200_MAG_FILTER_NEAREST |
 287                                           R200_MIN_FILTER_NEAREST));
 288     OUT_BATCH_REGVAL(R200_PP_TXFORMAT_0, txformat);
 289     OUT_BATCH_REGVAL(R200_PP_TXFORMAT_X_0, 0);
 290     OUT_BATCH_REGVAL(R200_PP_TXSIZE_0, ((width - 1) |
 291                                         ((height - 1) << RADEON_TEX_VSIZE_SHIFT)));
 292     OUT_BATCH_REGVAL(R200_PP_TXPITCH_0, pitch * _mesa_get_format_bytes(src_mesa_format) - 32);
 293
 294     OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1);
 295     OUT_BATCH_RELOC(bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 296
 297     END_BATCH();
 298 }
 299
 300 static inline void emit_cb_setup(struct r200_context *r200,
 301                                  struct radeon_bo *bo,
 302                                  intptr_t offset,
 303                                  mesa_format mesa_format,
 304                                  unsigned pitch,
 305                                  unsigned width,
 306                                  unsigned height)
 307 {
 308     uint32_t dst_pitch = pitch;
 309     uint32_t dst_format = 0;
 310     BATCH_LOCALS(&r200->radeon);
 311
 312     switch (mesa_format) {
 313     /* The first of each pair is for little, the second for big endian */
 314     case MESA_FORMAT_B8G8R8A8_UNORM:
 315     case MESA_FORMAT_A8R8G8B8_UNORM:
 316     case MESA_FORMAT_B8G8R8X8_UNORM:
 317     case MESA_FORMAT_X8R8G8B8_UNORM:
 318     /* These two are valid both for little and big endian (swizzled) */
 319     case MESA_FORMAT_A8B8G8R8_UNORM:
 320     case MESA_FORMAT_R8G8B8A8_UNORM:
 321             dst_format = RADEON_COLOR_FORMAT_ARGB8888;
 322             break;
 323     case MESA_FORMAT_B5G6R5_UNORM:
 324     case MESA_FORMAT_R5G6B5_UNORM:
 325             dst_format = RADEON_COLOR_FORMAT_RGB565;
 326             break;
 327     case MESA_FORMAT_B4G4R4A4_UNORM:
 328     case MESA_FORMAT_A4R4G4B4_UNORM:
 329             dst_format = RADEON_COLOR_FORMAT_ARGB4444;
 330             break;
 331     case MESA_FORMAT_B5G5R5A1_UNORM:
 332     case MESA_FORMAT_A1R5G5B5_UNORM:
 333             dst_format = RADEON_COLOR_FORMAT_ARGB1555;
 334             break;
 335     case MESA_FORMAT_A_UNORM8:
 336     case MESA_FORMAT_L_UNORM8:
 337     case MESA_FORMAT_I_UNORM8:
 338             dst_format = RADEON_COLOR_FORMAT_RGB8;
 339             break;
 340     default:
 341             break;
 342     }
 343
 344     if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 345         dst_pitch |= R200_COLOR_TILE_ENABLE;
 346     if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
 347         dst_pitch |= R200_COLOR_MICROTILE_ENABLE;
 348
 349     BEGIN_BATCH(22);
 350     OUT_BATCH_REGVAL(R200_RE_AUX_SCISSOR_CNTL, 0);
 351     OUT_BATCH_REGVAL(R200_RE_CNTL, 0);
 352     OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0);
 353     OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, (((width - 1) << RADEON_RE_WIDTH_SHIFT) |
 354                                               ((height - 1) << RADEON_RE_HEIGHT_SHIFT)));
 355     OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff);
 356     OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
 357     OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format);
 358
 359     OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1);
 360     OUT_BATCH_RELOC(bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
 361     OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1);
 362     OUT_BATCH_RELOC(bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
 363
 364     END_BATCH();
 365 }
 366
 367 static GLboolean validate_buffers(struct r200_context *r200,
 368                                   struct radeon_bo *src_bo,
 369                                   struct radeon_bo *dst_bo)
 370 {
 371     int ret;
 372
 373     radeon_cs_space_reset_bos(r200->radeon.cmdbuf.cs);
 374
 375     ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs,
 376                                         src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 377     if (ret)
 378         return GL_FALSE;
 379
 380     ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs,
 381                                         dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
 382     if (ret)
 383         return GL_FALSE;
 384
 385     return GL_TRUE;
 386 }
 387
 388 /**
 389  * Calculate texcoords for given image region.
 390  * Output values are [minx, maxx, miny, maxy]
 391  */
 392 static inline void calc_tex_coords(float img_width, float img_height,
 393                                    float x, float y,
 394                                    float reg_width, float reg_height,
 395                                    unsigned flip_y, float *buf)
 396 {
 397     buf[0] = x / img_width;
 398     buf[1] = buf[0] + reg_width / img_width;
 399     buf[2] = y / img_height;
 400     buf[3] = buf[2] + reg_height / img_height;
 401     if (flip_y)
 402     {
 403         buf[2] = 1.0 - buf[2];
 404         buf[3] = 1.0 - buf[3];
 405     }
 406 }
 407
 408 static inline void emit_draw_packet(struct r200_context *r200,
 409                                     unsigned src_width, unsigned src_height,
 410                                     unsigned src_x_offset, unsigned src_y_offset,
 411                                     unsigned dst_x_offset, unsigned dst_y_offset,
 412                                     unsigned reg_width, unsigned reg_height,
 413                                     unsigned flip_y)
 414 {
 415     float texcoords[4];
 416     float verts[12];
 417     BATCH_LOCALS(&r200->radeon);
 418
 419     calc_tex_coords(src_width, src_height,
 420                     src_x_offset, src_y_offset,
 421                     reg_width, reg_height,
 422                     flip_y, texcoords);
 423
 424     verts[0] = dst_x_offset;
 425     verts[1] = dst_y_offset + reg_height;
 426     verts[2] = texcoords[0];
 427     verts[3] = texcoords[3];
 428
 429     verts[4] = dst_x_offset + reg_width;
 430     verts[5] = dst_y_offset + reg_height;
 431     verts[6] = texcoords[1];
 432     verts[7] = texcoords[3];
 433
 434     verts[8] = dst_x_offset + reg_width;
 435     verts[9] = dst_y_offset;
 436     verts[10] = texcoords[1];
 437     verts[11] = texcoords[2];
 438
 439     BEGIN_BATCH(14);
 440     OUT_BATCH(R200_CP_CMD_3D_DRAW_IMMD_2 | (12 << 16));
 441     OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING |
 442               RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
 443               (3 << 16));
 444     OUT_BATCH_TABLE(verts, 12);
 445     END_BATCH();
 446 }
 447
 448 /**
 449  * Copy a region of [@a width x @a height] pixels from source buffer
 450  * to destination buffer.
 451  * @param[in] r200 r200 context
 452  * @param[in] src_bo source radeon buffer object
 453  * @param[in] src_offset offset of the source image in the @a src_bo
 454  * @param[in] src_mesaformat source image format
 455  * @param[in] src_pitch aligned source image width
 456  * @param[in] src_width source image width
 457  * @param[in] src_height source image height
 458  * @param[in] src_x_offset x offset in the source image
 459  * @param[in] src_y_offset y offset in the source image
 460  * @param[in] dst_bo destination radeon buffer object
 461  * @param[in] dst_offset offset of the destination image in the @a dst_bo
 462  * @param[in] dst_mesaformat destination image format
 463  * @param[in] dst_pitch aligned destination image width
 464  * @param[in] dst_width destination image width
 465  * @param[in] dst_height destination image height
 466  * @param[in] dst_x_offset x offset in the destination image
 467  * @param[in] dst_y_offset y offset in the destination image
 468  * @param[in] width region width
 469  * @param[in] height region height
 470  * @param[in] flip_y set if y coords of the source image need to be flipped
 471  */
 472 unsigned r200_blit(struct gl_context *ctx,
 473                    struct radeon_bo *src_bo,
 474                    intptr_t src_offset,
 475                    mesa_format src_mesaformat,
 476                    unsigned src_pitch,
 477                    unsigned src_width,
 478                    unsigned src_height,
 479                    unsigned src_x_offset,
 480                    unsigned src_y_offset,
 481                    struct radeon_bo *dst_bo,
 482                    intptr_t dst_offset,
 483                    mesa_format dst_mesaformat,
 484                    unsigned dst_pitch,
 485                    unsigned dst_width,
 486                    unsigned dst_height,
 487                    unsigned dst_x_offset,
 488                    unsigned dst_y_offset,
 489                    unsigned reg_width,
 490                    unsigned reg_height,
 491                    unsigned flip_y)
 492 {
 493     struct r200_context *r200 = R200_CONTEXT(ctx);
 494
 495     if (!r200_check_blit(dst_mesaformat, dst_pitch))
 496         return GL_FALSE;
 497
 498     /* Make sure that colorbuffer has even width - hw limitation */
 499     if (dst_pitch % 2 > 0)
 500         ++dst_pitch;
 501
 502     /* Need to clamp the region size to make sure
 503      * we don't read outside of the source buffer
 504      * or write outside of the destination buffer.
 505      */
 506     if (reg_width + src_x_offset > src_width)
 507         reg_width = src_width - src_x_offset;
 508     if (reg_height + src_y_offset > src_height)
 509         reg_height = src_height - src_y_offset;
 510     if (reg_width + dst_x_offset > dst_width)
 511         reg_width = dst_width - dst_x_offset;
 512     if (reg_height + dst_y_offset > dst_height)
 513         reg_height = dst_height - dst_y_offset;
 514
 515     if (src_bo == dst_bo) {
 516         return GL_FALSE;
 517     }
 518
 519     if (src_offset % 32 || dst_offset % 32) {
 520         return GL_FALSE;
 521     }
 522
 523     if (0) {
 524         fprintf(stderr, "src: size [%d x %d], pitch %d, "
 525                 "offset [%d x %d], format %s, bo %p\n",
 526                 src_width, src_height, src_pitch,
 527                 src_x_offset, src_y_offset,
 528                 _mesa_get_format_name(src_mesaformat),
 529                 src_bo);
 530         fprintf(stderr, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
 531                 dst_pitch, dst_x_offset, dst_y_offset,
 532                 _mesa_get_format_name(dst_mesaformat), dst_bo);
 533         fprintf(stderr, "region: %d x %d\n", reg_width, reg_height);
 534     }
 535
 536     /* Flush is needed to make sure that source buffer has correct data */
 537     radeonFlush(&r200->radeon.glCtx);
 538
 539     rcommonEnsureCmdBufSpace(&r200->radeon, 102, __func__);
 540
 541     if (!validate_buffers(r200, src_bo, dst_bo))
 542         return GL_FALSE;
 543
 544     /* 14 */
 545     emit_vtx_state(r200);
 546     /* 52 */
 547     emit_tx_setup(r200, src_mesaformat, dst_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
 548     /* 22 */
 549     emit_cb_setup(r200, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);
 550     /* 14 */
 551     emit_draw_packet(r200, src_width, src_height,
 552                      src_x_offset, src_y_offset,
 553                      dst_x_offset, dst_y_offset,
 554                      reg_width, reg_height,
 555                      flip_y);
 556
 557     radeonFlush(ctx);
 558
 559     /* We submitted those packets outside our state atom mechanism. Thus
 560      * make sure the atoms are resubmitted the next time. */
 561     r200->hw.cst.dirty = GL_TRUE;
 562     r200->hw.ctx.dirty = GL_TRUE;
 563     r200->hw.vap.dirty = GL_TRUE;
 564     r200->hw.msk.dirty = GL_TRUE;
 565     r200->hw.pix[0].dirty = GL_TRUE;
 566     r200->hw.pix[1].dirty = GL_TRUE;
 567     r200->hw.pix[2].dirty = GL_TRUE;
 568     r200->hw.pix[3].dirty = GL_TRUE;
 569     r200->hw.sci.dirty = GL_TRUE;
 570     r200->hw.set.dirty = GL_TRUE;
 571     r200->hw.tex[0].dirty = GL_TRUE;
 572     r200->hw.vte.dirty = GL_TRUE;
 573     r200->hw.vtx.dirty = GL_TRUE;
 574
 575     return GL_TRUE;
 576 }