src/mesa/drivers/dri/r200/r200_blit.c

   1 /*
   2  * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_common.h"
  29 #include "r200_context.h"
  30 #include "r200_blit.h"
  31
  32 static inline uint32_t cmdpacket0(struct radeon_screen *rscrn,
  33                                   int reg, int count)
  34 {
  35     if (count)
  36             return CP_PACKET0(reg, count - 1);
  37     return CP_PACKET2;
  38 }
  39
  40 /* common formats supported as both textures and render targets */
  41 unsigned r200_check_blit(gl_format mesa_format)
  42 {
  43     /* XXX others?  BE/LE? */
  44     switch (mesa_format) {
  45     case MESA_FORMAT_ARGB8888:
  46     case MESA_FORMAT_XRGB8888:
  47     case MESA_FORMAT_RGB565:
  48     case MESA_FORMAT_ARGB4444:
  49     case MESA_FORMAT_ARGB1555:
  50     case MESA_FORMAT_A8:
  51     case MESA_FORMAT_L8:
  52     case MESA_FORMAT_I8:
  53             break;
  54     default:
  55             return 0;
  56     }
  57
  58     /* ??? */
  59     if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0)
  60             return 0;
  61
  62     return 1;
  63 }
  64
  65 static inline void emit_vtx_state(struct r200_context *r200)
  66 {
  67     BATCH_LOCALS(&r200->radeon);
  68
  69     BEGIN_BATCH(14);
  70     if (r200->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
  71             OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, 0);
  72     } else {
  73             OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
  74     }
  75     OUT_BATCH_REGVAL(R200_SE_VAP_CNTL, (R200_VAP_FORCE_W_TO_ONE |
  76                                         (9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT)));
  77     OUT_BATCH_REGVAL(R200_SE_VTX_STATE_CNTL, 0);
  78     OUT_BATCH_REGVAL(R200_SE_VTE_CNTL, 0);
  79     OUT_BATCH_REGVAL(R200_SE_VTX_FMT_0, R200_VTX_XY);
  80     OUT_BATCH_REGVAL(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
  81     OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
  82                                       RADEON_BFACE_SOLID |
  83                                       RADEON_FFACE_SOLID |
  84                                       RADEON_VTX_PIX_CENTER_OGL |
  85                                       RADEON_ROUND_MODE_ROUND |
  86                                       RADEON_ROUND_PREC_4TH_PIX));
  87     END_BATCH();
  88 }
  89
  90 static void inline emit_tx_setup(struct r200_context *r200,
  91                                  gl_format mesa_format,
  92                                  struct radeon_bo *bo,
  93                                  intptr_t offset,
  94                                  unsigned width,
  95                                  unsigned height,
  96                                  unsigned pitch)
  97 {
  98     uint32_t txformat = R200_TXFORMAT_NON_POWER2;
  99     BATCH_LOCALS(&r200->radeon);
 100
 101     assert(width <= 2047);
 102     assert(height <= 2047);
 103     assert(offset % 32 == 0);
 104
 105     /* XXX others?  BE/LE? */
 106     switch (mesa_format) {
 107     case MESA_FORMAT_ARGB8888:
 108             txformat |= R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP;
 109             break;
 110     case MESA_FORMAT_RGBA8888:
 111             txformat |= R200_TXFORMAT_RGBA8888 | R200_TXFORMAT_ALPHA_IN_MAP;
 112             break;
 113     case MESA_FORMAT_RGBA8888_REV:
 114             txformat |= R200_TXFORMAT_ABGR8888 | R200_TXFORMAT_ALPHA_IN_MAP;
 115             break;
 116     case MESA_FORMAT_XRGB8888:
 117             txformat |= R200_TXFORMAT_ARGB8888;
 118             break;
 119     case MESA_FORMAT_RGB565:
 120             txformat |= R200_TXFORMAT_RGB565;
 121             break;
 122     case MESA_FORMAT_ARGB4444:
 123             txformat |= R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP;
 124             break;
 125     case MESA_FORMAT_ARGB1555:
 126             txformat |= R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP;
 127             break;
 128     case MESA_FORMAT_A8:
 129     case MESA_FORMAT_I8:
 130             txformat |= R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP;
 131             break;
 132     case MESA_FORMAT_L8:
 133             txformat |= R200_TXFORMAT_I8;
 134             break;
 135     case MESA_FORMAT_AL88:
 136             txformat |= R200_TXFORMAT_AI88 | R200_TXFORMAT_ALPHA_IN_MAP;
 137             break;
 138     default:
 139             break;
 140     }
 141
 142     BEGIN_BATCH(28);
 143     OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
 144     OUT_BATCH_REGVAL(R200_PP_CNTL_X, 0);
 145     OUT_BATCH_REGVAL(R200_PP_TXMULTI_CTL_0, 0);
 146     OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
 147                                           R200_TXC_ARG_B_ZERO |
 148                                           R200_TXC_ARG_C_R0_COLOR |
 149                                           R200_TXC_OP_MADD));
 150     OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
 151     OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO |
 152                                           R200_TXA_ARG_B_ZERO |
 153                                           R200_TXA_ARG_C_R0_ALPHA |
 154                                           R200_TXA_OP_MADD));
 155     OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
 156     OUT_BATCH_REGVAL(R200_PP_TXFILTER_0, (R200_CLAMP_S_CLAMP_LAST |
 157                                           R200_CLAMP_T_CLAMP_LAST |
 158                                           R200_MAG_FILTER_NEAREST |
 159                                           R200_MIN_FILTER_NEAREST));
 160     OUT_BATCH_REGVAL(R200_PP_TXFORMAT_0, txformat);
 161     OUT_BATCH_REGVAL(R200_PP_TXFORMAT_X_0, 0);
 162     OUT_BATCH_REGVAL(R200_PP_TXSIZE_0, ((width - 1) |
 163                                         ((height - 1) << RADEON_TEX_VSIZE_SHIFT)));
 164     OUT_BATCH_REGVAL(R200_PP_TXPITCH_0, pitch * _mesa_get_format_bytes(mesa_format) - 32);
 165
 166     OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1);
 167     OUT_BATCH_RELOC(0, bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 168
 169     END_BATCH();
 170 }
 171
 172 static inline void emit_cb_setup(struct r200_context *r200,
 173                                  struct radeon_bo *bo,
 174                                  intptr_t offset,
 175                                  gl_format mesa_format,
 176                                  unsigned pitch,
 177                                  unsigned width,
 178                                  unsigned height)
 179 {
 180     uint32_t dst_pitch = pitch;
 181     uint32_t dst_format = 0;
 182     BATCH_LOCALS(&r200->radeon);
 183
 184     /* XXX others?  BE/LE? */
 185     switch (mesa_format) {
 186     case MESA_FORMAT_ARGB8888:
 187     case MESA_FORMAT_XRGB8888:
 188             dst_format = RADEON_COLOR_FORMAT_ARGB8888;
 189             break;
 190     case MESA_FORMAT_RGB565:
 191             dst_format = RADEON_COLOR_FORMAT_RGB565;
 192             break;
 193     case MESA_FORMAT_ARGB4444:
 194             dst_format = RADEON_COLOR_FORMAT_ARGB4444;
 195             break;
 196     case MESA_FORMAT_ARGB1555:
 197             dst_format = RADEON_COLOR_FORMAT_ARGB1555;
 198             break;
 199     case MESA_FORMAT_A8:
 200     case MESA_FORMAT_L8:
 201     case MESA_FORMAT_I8:
 202             dst_format = RADEON_COLOR_FORMAT_RGB8;
 203             break;
 204     default:
 205             break;
 206     }
 207
 208     BEGIN_BATCH_NO_AUTOSTATE(22);
 209     OUT_BATCH_REGVAL(R200_RE_AUX_SCISSOR_CNTL, 0);
 210     OUT_BATCH_REGVAL(R200_RE_CNTL, 0);
 211     OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0);
 212     OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, ((width << RADEON_RE_WIDTH_SHIFT) |
 213                                               (height << RADEON_RE_HEIGHT_SHIFT)));
 214     OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff);
 215     OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
 216     OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format);
 217
 218     OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1);
 219     OUT_BATCH_RELOC(0, bo, 0, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
 220     OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1);
 221     OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
 222
 223     END_BATCH();
 224 }
 225
 226 static GLboolean validate_buffers(struct r200_context *r200,
 227                                   struct radeon_bo *src_bo,
 228                                   struct radeon_bo *dst_bo)
 229 {
 230     int ret;
 231
 232     radeon_cs_space_reset_bos(r200->radeon.cmdbuf.cs);
 233
 234     ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs,
 235                                         src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 236     if (ret)
 237         return GL_FALSE;
 238
 239     ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs,
 240                                         dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
 241     if (ret)
 242         return GL_FALSE;
 243
 244     return GL_TRUE;
 245 }
 246
 247 /**
 248  * Calculate texcoords for given image region.
 249  * Output values are [minx, maxx, miny, maxy]
 250  */
 251 static inline void calc_tex_coords(float img_width, float img_height,
 252                                    float x, float y,
 253                                    float reg_width, float reg_height,
 254                                    unsigned flip_y, float *buf)
 255 {
 256     buf[0] = x / img_width;
 257     buf[1] = buf[0] + reg_width / img_width;
 258     buf[2] = y / img_height;
 259     buf[3] = buf[2] + reg_height / img_height;
 260     if (flip_y)
 261     {
 262         buf[2] = 1.0 - buf[2];
 263         buf[3] = 1.0 - buf[3];
 264     }
 265 }
 266
 267 static inline void emit_draw_packet(struct r200_context *r200,
 268                                     unsigned src_width, unsigned src_height,
 269                                     unsigned src_x_offset, unsigned src_y_offset,
 270                                     unsigned dst_x_offset, unsigned dst_y_offset,
 271                                     unsigned reg_width, unsigned reg_height,
 272                                     unsigned flip_y)
 273 {
 274     float texcoords[4];
 275     float verts[12];
 276     BATCH_LOCALS(&r200->radeon);
 277
 278     calc_tex_coords(src_width, src_height,
 279                     src_x_offset, src_y_offset,
 280                     reg_width, reg_height,
 281                     flip_y, texcoords);
 282
 283     verts[0] = dst_x_offset;
 284     verts[1] = dst_y_offset + reg_height;
 285     verts[2] = texcoords[0];
 286     verts[3] = texcoords[3];
 287
 288     verts[4] = dst_x_offset + reg_width;
 289     verts[5] = dst_y_offset + reg_height;
 290     verts[6] = texcoords[1];
 291     verts[7] = texcoords[3];
 292
 293     verts[8] = dst_x_offset + reg_width;
 294     verts[9] = dst_y_offset;
 295     verts[10] = texcoords[1];
 296     verts[11] = texcoords[2];
 297
 298     BEGIN_BATCH(14);
 299     OUT_BATCH(R200_CP_CMD_3D_DRAW_IMMD_2 | (12 << 16));
 300     OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING |
 301               RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
 302               (3 << 16));
 303     OUT_BATCH_TABLE(verts, 12);
 304     END_BATCH();
 305 }
 306
 307 /**
 308  * Copy a region of [@a width x @a height] pixels from source buffer
 309  * to destination buffer.
 310  * @param[in] r200 r200 context
 311  * @param[in] src_bo source radeon buffer object
 312  * @param[in] src_offset offset of the source image in the @a src_bo
 313  * @param[in] src_mesaformat source image format
 314  * @param[in] src_pitch aligned source image width
 315  * @param[in] src_width source image width
 316  * @param[in] src_height source image height
 317  * @param[in] src_x_offset x offset in the source image
 318  * @param[in] src_y_offset y offset in the source image
 319  * @param[in] dst_bo destination radeon buffer object
 320  * @param[in] dst_offset offset of the destination image in the @a dst_bo
 321  * @param[in] dst_mesaformat destination image format
 322  * @param[in] dst_pitch aligned destination image width
 323  * @param[in] dst_width destination image width
 324  * @param[in] dst_height destination image height
 325  * @param[in] dst_x_offset x offset in the destination image
 326  * @param[in] dst_y_offset y offset in the destination image
 327  * @param[in] width region width
 328  * @param[in] height region height
 329  * @param[in] flip_y set if y coords of the source image need to be flipped
 330  */
 331 unsigned r200_blit(GLcontext *ctx,
 332                    struct radeon_bo *src_bo,
 333                    intptr_t src_offset,
 334                    gl_format src_mesaformat,
 335                    unsigned src_pitch,
 336                    unsigned src_width,
 337                    unsigned src_height,
 338                    unsigned src_x_offset,
 339                    unsigned src_y_offset,
 340                    struct radeon_bo *dst_bo,
 341                    intptr_t dst_offset,
 342                    gl_format dst_mesaformat,
 343                    unsigned dst_pitch,
 344                    unsigned dst_width,
 345                    unsigned dst_height,
 346                    unsigned dst_x_offset,
 347                    unsigned dst_y_offset,
 348                    unsigned reg_width,
 349                    unsigned reg_height,
 350                    unsigned flip_y)
 351 {
 352     struct r200_context *r200 = R200_CONTEXT(ctx);
 353
 354     if (!r200_check_blit(dst_mesaformat))
 355         return GL_FALSE;
 356
 357     /* Make sure that colorbuffer has even width - hw limitation */
 358     if (dst_pitch % 2 > 0)
 359         ++dst_pitch;
 360
 361     /* Rendering to small buffer doesn't work.
 362      * Looks like a hw limitation.
 363      */
 364     if (dst_pitch < 32)
 365         return GL_FALSE;
 366
 367     /* Need to clamp the region size to make sure
 368      * we don't read outside of the source buffer
 369      * or write outside of the destination buffer.
 370      */
 371     if (reg_width + src_x_offset > src_width)
 372         reg_width = src_width - src_x_offset;
 373     if (reg_height + src_y_offset > src_height)
 374         reg_height = src_height - src_y_offset;
 375     if (reg_width + dst_x_offset > dst_width)
 376         reg_width = dst_width - dst_x_offset;
 377     if (reg_height + dst_y_offset > dst_height)
 378         reg_height = dst_height - dst_y_offset;
 379
 380     if (src_bo == dst_bo) {
 381         return GL_FALSE;
 382     }
 383
 384     if (src_offset % 32 || dst_offset % 32) {
 385         return GL_FALSE;
 386     }
 387
 388     if (0) {
 389         fprintf(stderr, "src: size [%d x %d], pitch %d, "
 390                 "offset [%d x %d], format %s, bo %p\n",
 391                 src_width, src_height, src_pitch,
 392                 src_x_offset, src_y_offset,
 393                 _mesa_get_format_name(src_mesaformat),
 394                 src_bo);
 395         fprintf(stderr, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
 396                 dst_pitch, dst_x_offset, dst_y_offset,
 397                 _mesa_get_format_name(dst_mesaformat), dst_bo);
 398         fprintf(stderr, "region: %d x %d\n", reg_width, reg_height);
 399     }
 400
 401     /* Flush is needed to make sure that source buffer has correct data */
 402     radeonFlush(r200->radeon.glCtx);
 403
 404     rcommonEnsureCmdBufSpace(&r200->radeon, 78, __FUNCTION__);
 405
 406     if (!validate_buffers(r200, src_bo, dst_bo))
 407         return GL_FALSE;
 408
 409     /* 14 */
 410     emit_vtx_state(r200);
 411     /* 28 */
 412     emit_tx_setup(r200, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
 413     /* 22 */
 414     emit_cb_setup(r200, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);
 415     /* 14 */
 416     emit_draw_packet(r200, src_width, src_height,
 417                      src_x_offset, src_y_offset,
 418                      dst_x_offset, dst_y_offset,
 419                      reg_width, reg_height,
 420                      flip_y);
 421
 422     radeonFlush(ctx);
 423
 424     return GL_TRUE;
 425 }