src/mesa/drivers/dri/r200/r200_cmdbuf.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_cmdbuf.c,v 1.1 2002/10/30 12:51:51 alanh Exp $ */
   2 /*
   3 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4
   5 The Weather Channel (TM) funded Tungsten Graphics to develop the
   6 initial release of the Radeon 8500 driver under the XFree86 license.
   7 This notice must be preserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28 */
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "glheader.h"
  36 #include "imports.h"
  37 #include "macros.h"
  38 #include "context.h"
  39 #include "swrast/swrast.h"
  40 #include "simple_list.h"
  41
  42 #include "r200_context.h"
  43 #include "r200_state.h"
  44 #include "r200_ioctl.h"
  45 #include "r200_tcl.h"
  46 #include "r200_sanity.h"
  47 #include "radeon_reg.h"
  48
  49 static void print_state_atom( struct r200_state_atom *state )
  50 {
  51    int i;
  52
  53    fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size);
  54
  55    if (0 & R200_DEBUG & DEBUG_VERBOSE)
  56       for (i = 0 ; i < state->cmd_size ; i++)
  57          fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]);
  58
  59 }
  60
  61 static void r200_emit_state_list( r200ContextPtr rmesa,
  62                                     struct r200_state_atom *list )
  63 {
  64    struct r200_state_atom *state, *tmp;
  65    char *dest;
  66
  67    foreach_s( state, tmp, list ) {
  68       if (state->check( rmesa->glCtx, state->idx )) {
  69          dest = r200AllocCmdBuf( rmesa, state->cmd_size * 4, __FUNCTION__);
  70          memcpy( dest, state->cmd, state->cmd_size * 4);
  71          move_to_head( &(rmesa->hw.clean), state );
  72          if (R200_DEBUG & DEBUG_STATE)
  73             print_state_atom( state );
  74       }
  75       else if (R200_DEBUG & DEBUG_STATE)
  76          fprintf(stderr, "skip state %s\n", state->name);
  77    }
  78 }
  79
  80
  81 void r200EmitState( r200ContextPtr rmesa )
  82 {
  83    struct r200_state_atom *state, *tmp;
  84
  85    if (R200_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
  86       fprintf(stderr, "%s\n", __FUNCTION__);
  87
  88    /* Somewhat overkill:
  89     */
  90    if ( rmesa->lost_context) {
  91       if (R200_DEBUG & (DEBUG_STATE|DEBUG_PRIMS|DEBUG_IOCTL))
  92          fprintf(stderr, "%s - lost context\n", __FUNCTION__);
  93
  94       foreach_s( state, tmp, &(rmesa->hw.clean) )
  95          move_to_tail(&(rmesa->hw.dirty), state );
  96
  97       rmesa->lost_context = 0;
  98    }
  99    else {
 100       move_to_tail( &rmesa->hw.dirty, &rmesa->hw.mtl[0] );
 101       /* odd bug? -- isosurf, cycle between reflect & lit */
 102    }
 103
 104    r200_emit_state_list( rmesa, &rmesa->hw.dirty );
 105 }
 106
 107
 108
 109 /* Fire a section of the retained (indexed_verts) buffer as a regular
 110  * primtive.
 111  */
 112 extern void r200EmitVbufPrim( r200ContextPtr rmesa,
 113                                 GLuint primitive,
 114                                 GLuint vertex_nr )
 115 {
 116    drmRadeonCmdHeader *cmd;
 117
 118    assert(!(primitive & R200_VF_PRIM_WALK_IND));
 119
 120    r200EmitState( rmesa );
 121
 122    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 123       fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__,
 124               rmesa->store.cmd_used/4, primitive, vertex_nr);
 125
 126    cmd = (drmRadeonCmdHeader *)r200AllocCmdBuf( rmesa, 3 * sizeof(*cmd),
 127                                                   __FUNCTION__ );
 128    cmd[0].i = 0;
 129    cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
 130    cmd[1].i = R200_CP_CMD_3D_DRAW_VBUF_2;
 131    cmd[2].i = (primitive |
 132                R200_VF_PRIM_WALK_LIST |
 133                R200_VF_COLOR_ORDER_RGBA |
 134                (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT));
 135 }
 136
 137
 138 void r200FlushElts( r200ContextPtr rmesa )
 139 {
 140    int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start);
 141    int dwords;
 142    int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 12)) / 2;
 143
 144    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 145       fprintf(stderr, "%s\n", __FUNCTION__);
 146
 147    assert( rmesa->dma.flush == r200FlushElts );
 148    rmesa->dma.flush = 0;
 149
 150    /* Cope with odd number of elts:
 151     */
 152    rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2;
 153    dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4;
 154
 155    cmd[1] |= (dwords - 3) << 16;
 156    cmd[2] |= nr << R200_VF_VERTEX_NUMBER_SHIFT;
 157
 158    if (R200_DEBUG & DEBUG_SYNC) {
 159       fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
 160       r200Finish( rmesa->glCtx );
 161    }
 162 }
 163
 164
 165 GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
 166                                     GLuint primitive,
 167                                     GLuint min_nr )
 168 {
 169    drmRadeonCmdHeader *cmd;
 170    GLushort *retval;
 171
 172    if (R200_DEBUG & DEBUG_IOCTL)
 173       fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
 174
 175    assert((primitive & R200_VF_PRIM_WALK_IND));
 176
 177    r200EmitState( rmesa );
 178
 179    cmd = (drmRadeonCmdHeader *)r200AllocCmdBuf( rmesa,
 180                                                 12 + min_nr*2,
 181                                                 __FUNCTION__ );
 182    cmd[0].i = 0;
 183    cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
 184    cmd[1].i = R200_CP_CMD_3D_DRAW_INDX_2;
 185    cmd[2].i = (primitive |
 186                R200_VF_PRIM_WALK_IND |
 187                R200_VF_COLOR_ORDER_RGBA);
 188
 189
 190    retval = (GLushort *)(cmd+3);
 191
 192    if (R200_DEBUG & DEBUG_PRIMS)
 193       fprintf(stderr, "%s: header 0x%x prim %x \n",
 194               __FUNCTION__,
 195               cmd[1].i, primitive);
 196
 197    assert(!rmesa->dma.flush);
 198    rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
 199    rmesa->dma.flush = r200FlushElts;
 200
 201    rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf;
 202
 203    return retval;
 204 }
 205
 206
 207
 208 void r200EmitVertexAOS( r200ContextPtr rmesa,
 209                           GLuint vertex_size,
 210                           GLuint offset )
 211 {
 212    drmRadeonCmdHeader *cmd;
 213
 214    if (R200_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
 215       fprintf(stderr, "%s:  vertex_size 0x%x offset 0x%x \n",
 216               __FUNCTION__, vertex_size, offset);
 217
 218    cmd = (drmRadeonCmdHeader *)r200AllocCmdBuf( rmesa, 5 * sizeof(int),
 219                                                   __FUNCTION__ );
 220
 221    cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
 222    cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | (2 << 16);
 223    cmd[2].i = 1;
 224    cmd[3].i = vertex_size | (vertex_size << 8);
 225    cmd[4].i = offset;
 226 }
 227
 228
 229 void r200EmitAOS( r200ContextPtr rmesa,
 230                     struct r200_dma_region **component,
 231                     GLuint nr,
 232                     GLuint offset )
 233 {
 234    drmRadeonCmdHeader *cmd;
 235    int sz = 3 + ((nr/2)*3) + ((nr&1)*2);
 236    int i;
 237    int *tmp;
 238
 239    if (R200_DEBUG & DEBUG_IOCTL)
 240       fprintf(stderr, "%s nr arrays: %d\n", __FUNCTION__, nr);
 241
 242    cmd = (drmRadeonCmdHeader *)r200AllocCmdBuf( rmesa, sz * sizeof(int),
 243                                                   __FUNCTION__ );
 244    cmd[0].i = 0;
 245    cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
 246    cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | ((sz-3) << 16);
 247    cmd[2].i = nr;
 248    tmp = &cmd[0].i;
 249    cmd += 3;
 250
 251    for (i = 0 ; i < nr ; i++) {
 252       if (i & 1) {
 253          cmd[0].i |= ((component[i]->aos_stride << 24) |
 254                       (component[i]->aos_size << 16));
 255          cmd[2].i = (component[i]->aos_start +
 256                      offset * component[i]->aos_stride * 4);
 257          cmd += 3;
 258       }
 259       else {
 260          cmd[0].i = ((component[i]->aos_stride << 8) |
 261                      (component[i]->aos_size << 0));
 262          cmd[1].i = (component[i]->aos_start +
 263                      offset * component[i]->aos_stride * 4);
 264       }
 265    }
 266
 267    if (R200_DEBUG & DEBUG_VERTS) {
 268       fprintf(stderr, "%s:\n", __FUNCTION__);
 269       for (i = 0 ; i < sz ; i++)
 270          fprintf(stderr, "   %d: %x\n", i, tmp[i]);
 271    }
 272 }
 273
 274 void r200EmitBlit( r200ContextPtr rmesa,
 275                    GLuint color_fmt,
 276                    GLuint src_pitch,
 277                    GLuint src_offset,
 278                    GLuint dst_pitch,
 279                    GLuint dst_offset,
 280                    GLint srcx, GLint srcy,
 281                    GLint dstx, GLint dsty,
 282                    GLuint w, GLuint h )
 283 {
 284    drmRadeonCmdHeader *cmd;
 285
 286    if (R200_DEBUG & DEBUG_IOCTL)
 287       fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
 288               __FUNCTION__,
 289               src_pitch, src_offset, srcx, srcy,
 290               dst_pitch, dst_offset, dstx, dsty,
 291               w, h);
 292
 293    assert( (src_pitch & 63) == 0 );
 294    assert( (dst_pitch & 63) == 0 );
 295    assert( (src_offset & 1023) == 0 );
 296    assert( (dst_offset & 1023) == 0 );
 297    assert( w < (1<<16) );
 298    assert( h < (1<<16) );
 299
 300    cmd = (drmRadeonCmdHeader *)r200AllocCmdBuf( rmesa, 8 * sizeof(int),
 301                                                   __FUNCTION__ );
 302
 303
 304    cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
 305    cmd[1].i = R200_CP_CMD_BITBLT_MULTI | (5 << 16);
 306    cmd[2].i = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 307                RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 308                RADEON_GMC_BRUSH_NONE |
 309                (color_fmt << 8) |
 310                RADEON_GMC_SRC_DATATYPE_COLOR |
 311                RADEON_ROP3_S |
 312                RADEON_DP_SRC_SOURCE_MEMORY |
 313                RADEON_GMC_CLR_CMP_CNTL_DIS |
 314                RADEON_GMC_WR_MSK_DIS );
 315
 316    cmd[3].i = ((src_pitch/64)<<22) | (src_offset >> 10);
 317    cmd[4].i = ((dst_pitch/64)<<22) | (dst_offset >> 10);
 318    cmd[5].i = (srcx << 16) | srcy;
 319    cmd[6].i = (dstx << 16) | dsty; /* dst */
 320    cmd[7].i = (w << 16) | h;
 321 }
 322
 323
 324 void r200EmitWait( r200ContextPtr rmesa, GLuint flags )
 325 {
 326    if (rmesa->dri.drmMinor >= 6) {
 327       drmRadeonCmdHeader *cmd;
 328
 329       assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) );
 330
 331       cmd = (drmRadeonCmdHeader *)r200AllocCmdBuf( rmesa, 1 * sizeof(int),
 332                                                    __FUNCTION__ );
 333       cmd[0].i = 0;
 334       cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
 335       cmd[0].wait.flags = flags;
 336    }
 337 }