src/mesa/drivers/dri/r200/r200_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27 */
  28
  29 /*
  30  * Authors:
  31  *   Keith Whitwell <keith@tungstengraphics.com>
  32  */
  33
  34 #include "glheader.h"
  35 #include "imports.h"
  36 #include "macros.h"
  37 #include "context.h"
  38 #include "swrast/swrast.h"
  39 #include "simple_list.h"
  40
  41 #include "r200_context.h"
  42 #include "r200_state.h"
  43 #include "r200_ioctl.h"
  44 #include "r200_tcl.h"
  45 #include "r200_sanity.h"
  46 #include "radeon_reg.h"
  47
  48 static void print_state_atom( struct r200_state_atom *state )
  49 {
  50    int i;
  51
  52    fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size);
  53
  54    if (0 & R200_DEBUG & DEBUG_VERBOSE)
  55       for (i = 0 ; i < state->cmd_size ; i++)
  56          fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]);
  57
  58 }
  59
  60 /* The state atoms will be emitted in the order they appear in the atom list,
  61  * so this step is important.
  62  */
  63 void r200SetUpAtomList( r200ContextPtr rmesa )
  64 {
  65    int i, mtu;
  66
  67    mtu = rmesa->glCtx->Const.MaxTextureUnits;
  68
  69    make_empty_list(&rmesa->hw.atomlist);
  70    rmesa->hw.atomlist.name = "atom-list";
  71
  72    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ctx );
  73    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.set );
  74    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.lin );
  75    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msk );
  76    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpt );
  77    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vtx );
  78    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vap );
  79    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vte );
  80    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msc );
  81    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.cst );
  82    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.zbs );
  83    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tcl );
  84    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msl );
  85    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tcg );
  86    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.grd );
  87    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.fog );
  88    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tam );
  89    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tf );
  90    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.atf );
  91    for (i = 0; i < mtu; ++i)
  92        insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tex[i] );
  93    for (i = 0; i < mtu; ++i)
  94        insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.cube[i] );
  95    for (i = 0; i < 6; ++i)
  96        insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.pix[i] );
  97    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.afs[0] );
  98    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.afs[1] );
  99    for (i = 0; i < 8; ++i)
 100        insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.lit[i] );
 101    for (i = 0; i < 3 + mtu; ++i)
 102        insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.mat[i] );
 103    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.eye );
 104    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.glt );
 105    for (i = 0; i < 2; ++i)
 106       insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.mtl[i] );
 107    for (i = 0; i < 6; ++i)
 108        insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ucp[i] );
 109    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.spr );
 110    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ptp );
 111    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.prf );
 112    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.pvs );
 113    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpp[0] );
 114    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpp[1] );
 115    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpi[0] );
 116    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpi[1] );
 117 }
 118
 119 static void r200SaveHwState( r200ContextPtr rmesa )
 120 {
 121    struct r200_state_atom *atom;
 122    char * dest = rmesa->backup_store.cmd_buf;
 123
 124    if (R200_DEBUG & DEBUG_STATE)
 125       fprintf(stderr, "%s\n", __FUNCTION__);
 126
 127    rmesa->backup_store.cmd_used = 0;
 128
 129    foreach( atom, &rmesa->hw.atomlist ) {
 130       if ( atom->check( rmesa->glCtx, atom->idx ) ) {
 131          int size = atom->cmd_size * 4;
 132          memcpy( dest, atom->cmd, size);
 133          dest += size;
 134          rmesa->backup_store.cmd_used += size;
 135          if (R200_DEBUG & DEBUG_STATE)
 136             print_state_atom( atom );
 137       }
 138    }
 139
 140    assert( rmesa->backup_store.cmd_used <= R200_CMD_BUF_SZ );
 141    if (R200_DEBUG & DEBUG_STATE)
 142       fprintf(stderr, "Returning to r200EmitState\n");
 143 }
 144
 145 void r200EmitState( r200ContextPtr rmesa )
 146 {
 147    char *dest;
 148    int mtu;
 149    struct r200_state_atom *atom;
 150
 151    if (R200_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
 152       fprintf(stderr, "%s\n", __FUNCTION__);
 153
 154    if (rmesa->save_on_next_emit) {
 155       r200SaveHwState(rmesa);
 156       rmesa->save_on_next_emit = GL_FALSE;
 157    }
 158
 159    if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty)
 160       return;
 161
 162    mtu = rmesa->glCtx->Const.MaxTextureUnits;
 163
 164    /* To avoid going across the entire set of states multiple times, just check
 165     * for enough space for the case of emitting all state, and inline the
 166     * r200AllocCmdBuf code here without all the checks.
 167     */
 168    r200EnsureCmdBufSpace( rmesa, rmesa->hw.max_state_size );
 169
 170    /* we need to calculate dest after EnsureCmdBufSpace
 171       as we may flush the buffer - airlied */
 172    dest = rmesa->store.cmd_buf + rmesa->store.cmd_used;
 173    if (R200_DEBUG & DEBUG_STATE) {
 174       foreach( atom, &rmesa->hw.atomlist ) {
 175          if ( atom->dirty || rmesa->hw.all_dirty ) {
 176             if ( atom->check( rmesa->glCtx, atom->idx ) )
 177                print_state_atom( atom );
 178             else
 179                fprintf(stderr, "skip state %s\n", atom->name);
 180          }
 181       }
 182    }
 183
 184    foreach( atom, &rmesa->hw.atomlist ) {
 185       if ( rmesa->hw.all_dirty )
 186          atom->dirty = GL_TRUE;
 187       if ( atom->dirty ) {
 188          if ( atom->check( rmesa->glCtx, atom->idx ) ) {
 189             int size = atom->cmd_size * 4;
 190             memcpy( dest, atom->cmd, size);
 191             dest += size;
 192             rmesa->store.cmd_used += size;
 193             atom->dirty = GL_FALSE;
 194          }
 195       }
 196    }
 197
 198    assert( rmesa->store.cmd_used <= R200_CMD_BUF_SZ );
 199
 200    rmesa->hw.is_dirty = GL_FALSE;
 201    rmesa->hw.all_dirty = GL_FALSE;
 202 }
 203
 204 /* Fire a section of the retained (indexed_verts) buffer as a regular
 205  * primtive.
 206  */
 207 void r200EmitVbufPrim( r200ContextPtr rmesa,
 208                        GLuint primitive,
 209                        GLuint vertex_nr )
 210 {
 211    drm_radeon_cmd_header_t *cmd;
 212
 213    assert(!(primitive & R200_VF_PRIM_WALK_IND));
 214
 215    r200EmitState( rmesa );
 216
 217    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 218       fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__,
 219               rmesa->store.cmd_used/4, primitive, vertex_nr);
 220
 221    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VBUF_BUFSZ,
 222                                                   __FUNCTION__ );
 223    cmd[0].i = 0;
 224    cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
 225    cmd[1].i = R200_CP_CMD_3D_DRAW_VBUF_2;
 226    cmd[2].i = (primitive |
 227                R200_VF_PRIM_WALK_LIST |
 228                R200_VF_COLOR_ORDER_RGBA |
 229                (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT));
 230 }
 231
 232
 233 void r200FlushElts( r200ContextPtr rmesa )
 234 {
 235    int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start);
 236    int dwords;
 237    int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 12)) / 2;
 238
 239    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 240       fprintf(stderr, "%s\n", __FUNCTION__);
 241
 242    assert( rmesa->dma.flush == r200FlushElts );
 243    rmesa->dma.flush = NULL;
 244
 245    /* Cope with odd number of elts:
 246     */
 247    rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2;
 248    dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4;
 249
 250    cmd[1] |= (dwords - 3) << 16;
 251    cmd[2] |= nr << R200_VF_VERTEX_NUMBER_SHIFT;
 252
 253    if (R200_DEBUG & DEBUG_SYNC) {
 254       fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
 255       r200Finish( rmesa->glCtx );
 256    }
 257 }
 258
 259
 260 GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
 261                                     GLuint primitive,
 262                                     GLuint min_nr )
 263 {
 264    drm_radeon_cmd_header_t *cmd;
 265    GLushort *retval;
 266
 267    if (R200_DEBUG & DEBUG_IOCTL)
 268       fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
 269
 270    assert((primitive & R200_VF_PRIM_WALK_IND));
 271
 272    r200EmitState( rmesa );
 273
 274    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, ELTS_BUFSZ(min_nr),
 275                                                 __FUNCTION__ );
 276    cmd[0].i = 0;
 277    cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
 278    cmd[1].i = R200_CP_CMD_3D_DRAW_INDX_2;
 279    cmd[2].i = (primitive |
 280                R200_VF_PRIM_WALK_IND |
 281                R200_VF_COLOR_ORDER_RGBA);
 282
 283
 284    retval = (GLushort *)(cmd+3);
 285
 286    if (R200_DEBUG & DEBUG_PRIMS)
 287       fprintf(stderr, "%s: header 0x%x prim %x \n",
 288               __FUNCTION__,
 289               cmd[1].i, primitive);
 290
 291    assert(!rmesa->dma.flush);
 292    rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
 293    rmesa->dma.flush = r200FlushElts;
 294
 295    rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf;
 296
 297    return retval;
 298 }
 299
 300
 301
 302 void r200EmitVertexAOS( r200ContextPtr rmesa,
 303                           GLuint vertex_size,
 304                           GLuint offset )
 305 {
 306    drm_radeon_cmd_header_t *cmd;
 307
 308    if (R200_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
 309       fprintf(stderr, "%s:  vertex_size 0x%x offset 0x%x \n",
 310               __FUNCTION__, vertex_size, offset);
 311
 312    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VERT_AOS_BUFSZ,
 313                                                   __FUNCTION__ );
 314
 315    cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
 316    cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | (2 << 16);
 317    cmd[2].i = 1;
 318    cmd[3].i = vertex_size | (vertex_size << 8);
 319    cmd[4].i = offset;
 320 }
 321
 322
 323 void r200EmitAOS( r200ContextPtr rmesa,
 324                     struct r200_dma_region **component,
 325                     GLuint nr,
 326                     GLuint offset )
 327 {
 328    drm_radeon_cmd_header_t *cmd;
 329    int sz = AOS_BUFSZ(nr);
 330    int i;
 331    int *tmp;
 332
 333    if (R200_DEBUG & DEBUG_IOCTL)
 334       fprintf(stderr, "%s nr arrays: %d\n", __FUNCTION__, nr);
 335
 336    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, sz, __FUNCTION__ );
 337    cmd[0].i = 0;
 338    cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
 339    cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | (((sz / sizeof(int)) - 3) << 16);
 340    cmd[2].i = nr;
 341    tmp = &cmd[0].i;
 342    cmd += 3;
 343
 344    for (i = 0 ; i < nr ; i++) {
 345       if (i & 1) {
 346          cmd[0].i |= ((component[i]->aos_stride << 24) |
 347                       (component[i]->aos_size << 16));
 348          cmd[2].i = (component[i]->aos_start +
 349                      offset * component[i]->aos_stride * 4);
 350          cmd += 3;
 351       }
 352       else {
 353          cmd[0].i = ((component[i]->aos_stride << 8) |
 354                      (component[i]->aos_size << 0));
 355          cmd[1].i = (component[i]->aos_start +
 356                      offset * component[i]->aos_stride * 4);
 357       }
 358    }
 359
 360    if (R200_DEBUG & DEBUG_VERTS) {
 361       fprintf(stderr, "%s:\n", __FUNCTION__);
 362       for (i = 0 ; i < sz ; i++)
 363          fprintf(stderr, "   %d: %x\n", i, tmp[i]);
 364    }
 365 }
 366
 367 void r200EmitBlit( r200ContextPtr rmesa,
 368                    GLuint color_fmt,
 369                    GLuint src_pitch,
 370                    GLuint src_offset,
 371                    GLuint dst_pitch,
 372                    GLuint dst_offset,
 373                    GLint srcx, GLint srcy,
 374                    GLint dstx, GLint dsty,
 375                    GLuint w, GLuint h )
 376 {
 377    drm_radeon_cmd_header_t *cmd;
 378
 379    if (R200_DEBUG & DEBUG_IOCTL)
 380       fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
 381               __FUNCTION__,
 382               src_pitch, src_offset, srcx, srcy,
 383               dst_pitch, dst_offset, dstx, dsty,
 384               w, h);
 385
 386    assert( (src_pitch & 63) == 0 );
 387    assert( (dst_pitch & 63) == 0 );
 388    assert( (src_offset & 1023) == 0 );
 389    assert( (dst_offset & 1023) == 0 );
 390    assert( w < (1<<16) );
 391    assert( h < (1<<16) );
 392
 393    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int),
 394                                                   __FUNCTION__ );
 395
 396
 397    cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
 398    cmd[1].i = R200_CP_CMD_BITBLT_MULTI | (5 << 16);
 399    cmd[2].i = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 400                RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 401                RADEON_GMC_BRUSH_NONE |
 402                (color_fmt << 8) |
 403                RADEON_GMC_SRC_DATATYPE_COLOR |
 404                RADEON_ROP3_S |
 405                RADEON_DP_SRC_SOURCE_MEMORY |
 406                RADEON_GMC_CLR_CMP_CNTL_DIS |
 407                RADEON_GMC_WR_MSK_DIS );
 408
 409    cmd[3].i = ((src_pitch/64)<<22) | (src_offset >> 10);
 410    cmd[4].i = ((dst_pitch/64)<<22) | (dst_offset >> 10);
 411    cmd[5].i = (srcx << 16) | srcy;
 412    cmd[6].i = (dstx << 16) | dsty; /* dst */
 413    cmd[7].i = (w << 16) | h;
 414 }
 415
 416
 417 void r200EmitWait( r200ContextPtr rmesa, GLuint flags )
 418 {
 419    drm_radeon_cmd_header_t *cmd;
 420
 421    assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) );
 422
 423    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int),
 424                                            __FUNCTION__ );
 425    cmd[0].i = 0;
 426    cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
 427    cmd[0].wait.flags = flags;
 428 }