src/mesa/drivers/dri/r200/r200_cmdbuf.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_cmdbuf.c,v 1.1 2002/10/30 12:51:51 alanh Exp $ */
   2 /*
   3 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4
   5 The Weather Channel (TM) funded Tungsten Graphics to develop the
   6 initial release of the Radeon 8500 driver under the XFree86 license.
   7 This notice must be preserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28 */
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "glheader.h"
  36 #include "imports.h"
  37 #include "macros.h"
  38 #include "context.h"
  39 #include "swrast/swrast.h"
  40 #include "simple_list.h"
  41
  42 #include "r200_context.h"
  43 #include "r200_state.h"
  44 #include "r200_ioctl.h"
  45 #include "r200_tcl.h"
  46 #include "r200_sanity.h"
  47 #include "radeon_reg.h"
  48
  49 static void print_state_atom( struct r200_state_atom *state )
  50 {
  51    int i;
  52
  53    fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size);
  54
  55    if (0 & R200_DEBUG & DEBUG_VERBOSE)
  56       for (i = 0 ; i < state->cmd_size ; i++)
  57          fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]);
  58
  59 }
  60
  61 /* The state atoms will be emitted in the order they appear in the atom list,
  62  * so this step is important.
  63  */
  64 void r200SetUpAtomList( r200ContextPtr rmesa )
  65 {
  66    int i, mtu;
  67
  68    mtu = rmesa->glCtx->Const.MaxTextureUnits;
  69
  70    make_empty_list(&rmesa->hw.atomlist);
  71    rmesa->hw.atomlist.name = "atom-list";
  72
  73    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ctx );
  74    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.set );
  75    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.lin );
  76    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msk );
  77    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpt );
  78    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vtx );
  79    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vap );
  80    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vte );
  81    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msc );
  82    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.cst );
  83    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.zbs );
  84    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tcl );
  85    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msl );
  86    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tcg );
  87    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.grd );
  88    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.fog );
  89    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tam );
  90    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tf );
  91    for (i = 0; i < mtu; ++i)
  92        insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tex[i] );
  93    for (i = 0; i < mtu; ++i)
  94        insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.cube[i] );
  95    for (i = 0; i < 3 + mtu; ++i)
  96        insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.mat[i] );
  97    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.eye );
  98    insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.glt );
  99    for (i = 0; i < 2; ++i)
 100       insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.mtl[i] );
 101    for (i = 0; i < 8; ++i)
 102        insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.lit[i] );
 103    for (i = 0; i < 6; ++i)
 104        insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ucp[i] );
 105    for (i = 0; i < 6; ++i)
 106        insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.pix[i] );
 107 }
 108
 109 void r200EmitState( r200ContextPtr rmesa )
 110 {
 111    char *dest;
 112    int i, mtu;
 113    struct r200_state_atom *atom;
 114
 115    if (R200_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
 116       fprintf(stderr, "%s\n", __FUNCTION__);
 117
 118    if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty)
 119       return;
 120
 121    mtu = rmesa->glCtx->Const.MaxTextureUnits;
 122
 123    /* To avoid going across the entire set of states multiple times, just check
 124     * for enough space for the case of emitting all state, and inline the
 125     * r200AllocCmdBuf code here without all the checks.
 126     */
 127    dest = rmesa->store.cmd_buf + rmesa->store.cmd_used;
 128    r200EnsureCmdBufSpace( rmesa, rmesa->hw.max_state_size );
 129
 130    if (R200_DEBUG & DEBUG_STATE) {
 131       foreach( atom, &rmesa->hw.atomlist ) {
 132          if ( atom->dirty || rmesa->hw.all_dirty ) {
 133             if ( atom->check( rmesa->glCtx, atom->idx ) )
 134                print_state_atom( atom );
 135             else
 136                fprintf(stderr, "skip state %s\n", atom->name);
 137          }
 138       }
 139    }
 140
 141    foreach( atom, &rmesa->hw.atomlist ) {
 142       if ( rmesa->hw.all_dirty )
 143          atom->dirty = GL_TRUE;
 144       if ( atom->dirty ) {
 145          if ( atom->check( rmesa->glCtx, atom->idx ) ) {
 146             int size = atom->cmd_size * 4;
 147             memcpy( dest, atom->cmd, size);
 148             dest += size;
 149             rmesa->store.cmd_used += size;
 150             atom->dirty = GL_FALSE;
 151          }
 152       }
 153    }
 154
 155    assert( rmesa->store.cmd_used <= R200_CMD_BUF_SZ );
 156
 157    rmesa->hw.is_dirty = GL_FALSE;
 158    rmesa->hw.all_dirty = GL_FALSE;
 159 }
 160
 161 /* Fire a section of the retained (indexed_verts) buffer as a regular
 162  * primtive.
 163  */
 164 extern void r200EmitVbufPrim( r200ContextPtr rmesa,
 165                                 GLuint primitive,
 166                                 GLuint vertex_nr )
 167 {
 168    drm_radeon_cmd_header_t *cmd;
 169
 170    assert(!(primitive & R200_VF_PRIM_WALK_IND));
 171
 172    r200EmitState( rmesa );
 173
 174    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 175       fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__,
 176               rmesa->store.cmd_used/4, primitive, vertex_nr);
 177
 178    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VBUF_BUFSZ,
 179                                                   __FUNCTION__ );
 180    cmd[0].i = 0;
 181    cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
 182    cmd[1].i = R200_CP_CMD_3D_DRAW_VBUF_2;
 183    cmd[2].i = (primitive |
 184                R200_VF_PRIM_WALK_LIST |
 185                R200_VF_COLOR_ORDER_RGBA |
 186                (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT));
 187 }
 188
 189
 190 void r200FlushElts( r200ContextPtr rmesa )
 191 {
 192    int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start);
 193    int dwords;
 194    int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 12)) / 2;
 195
 196    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 197       fprintf(stderr, "%s\n", __FUNCTION__);
 198
 199    assert( rmesa->dma.flush == r200FlushElts );
 200    rmesa->dma.flush = 0;
 201
 202    /* Cope with odd number of elts:
 203     */
 204    rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2;
 205    dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4;
 206
 207    cmd[1] |= (dwords - 3) << 16;
 208    cmd[2] |= nr << R200_VF_VERTEX_NUMBER_SHIFT;
 209
 210    if (R200_DEBUG & DEBUG_SYNC) {
 211       fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
 212       r200Finish( rmesa->glCtx );
 213    }
 214 }
 215
 216
 217 GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
 218                                     GLuint primitive,
 219                                     GLuint min_nr )
 220 {
 221    drm_radeon_cmd_header_t *cmd;
 222    GLushort *retval;
 223
 224    if (R200_DEBUG & DEBUG_IOCTL)
 225       fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
 226
 227    assert((primitive & R200_VF_PRIM_WALK_IND));
 228
 229    r200EmitState( rmesa );
 230
 231    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, ELTS_BUFSZ(min_nr),
 232                                                 __FUNCTION__ );
 233    cmd[0].i = 0;
 234    cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
 235    cmd[1].i = R200_CP_CMD_3D_DRAW_INDX_2;
 236    cmd[2].i = (primitive |
 237                R200_VF_PRIM_WALK_IND |
 238                R200_VF_COLOR_ORDER_RGBA);
 239
 240
 241    retval = (GLushort *)(cmd+3);
 242
 243    if (R200_DEBUG & DEBUG_PRIMS)
 244       fprintf(stderr, "%s: header 0x%x prim %x \n",
 245               __FUNCTION__,
 246               cmd[1].i, primitive);
 247
 248    assert(!rmesa->dma.flush);
 249    rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
 250    rmesa->dma.flush = r200FlushElts;
 251
 252    rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf;
 253
 254    return retval;
 255 }
 256
 257
 258
 259 void r200EmitVertexAOS( r200ContextPtr rmesa,
 260                           GLuint vertex_size,
 261                           GLuint offset )
 262 {
 263    drm_radeon_cmd_header_t *cmd;
 264
 265    if (R200_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
 266       fprintf(stderr, "%s:  vertex_size 0x%x offset 0x%x \n",
 267               __FUNCTION__, vertex_size, offset);
 268
 269    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VERT_AOS_BUFSZ,
 270                                                   __FUNCTION__ );
 271
 272    cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
 273    cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | (2 << 16);
 274    cmd[2].i = 1;
 275    cmd[3].i = vertex_size | (vertex_size << 8);
 276    cmd[4].i = offset;
 277 }
 278
 279
 280 void r200EmitAOS( r200ContextPtr rmesa,
 281                     struct r200_dma_region **component,
 282                     GLuint nr,
 283                     GLuint offset )
 284 {
 285    drm_radeon_cmd_header_t *cmd;
 286    int sz = AOS_BUFSZ(nr);
 287    int i;
 288    int *tmp;
 289
 290    if (R200_DEBUG & DEBUG_IOCTL)
 291       fprintf(stderr, "%s nr arrays: %d\n", __FUNCTION__, nr);
 292
 293    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, sz, __FUNCTION__ );
 294    cmd[0].i = 0;
 295    cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
 296    cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | (((sz / sizeof(int)) - 3) << 16);
 297    cmd[2].i = nr;
 298    tmp = &cmd[0].i;
 299    cmd += 3;
 300
 301    for (i = 0 ; i < nr ; i++) {
 302       if (i & 1) {
 303          cmd[0].i |= ((component[i]->aos_stride << 24) |
 304                       (component[i]->aos_size << 16));
 305          cmd[2].i = (component[i]->aos_start +
 306                      offset * component[i]->aos_stride * 4);
 307          cmd += 3;
 308       }
 309       else {
 310          cmd[0].i = ((component[i]->aos_stride << 8) |
 311                      (component[i]->aos_size << 0));
 312          cmd[1].i = (component[i]->aos_start +
 313                      offset * component[i]->aos_stride * 4);
 314       }
 315    }
 316
 317    if (R200_DEBUG & DEBUG_VERTS) {
 318       fprintf(stderr, "%s:\n", __FUNCTION__);
 319       for (i = 0 ; i < sz ; i++)
 320          fprintf(stderr, "   %d: %x\n", i, tmp[i]);
 321    }
 322 }
 323
 324 void r200EmitBlit( r200ContextPtr rmesa,
 325                    GLuint color_fmt,
 326                    GLuint src_pitch,
 327                    GLuint src_offset,
 328                    GLuint dst_pitch,
 329                    GLuint dst_offset,
 330                    GLint srcx, GLint srcy,
 331                    GLint dstx, GLint dsty,
 332                    GLuint w, GLuint h )
 333 {
 334    drm_radeon_cmd_header_t *cmd;
 335
 336    if (R200_DEBUG & DEBUG_IOCTL)
 337       fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
 338               __FUNCTION__,
 339               src_pitch, src_offset, srcx, srcy,
 340               dst_pitch, dst_offset, dstx, dsty,
 341               w, h);
 342
 343    assert( (src_pitch & 63) == 0 );
 344    assert( (dst_pitch & 63) == 0 );
 345    assert( (src_offset & 1023) == 0 );
 346    assert( (dst_offset & 1023) == 0 );
 347    assert( w < (1<<16) );
 348    assert( h < (1<<16) );
 349
 350    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int),
 351                                                   __FUNCTION__ );
 352
 353
 354    cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
 355    cmd[1].i = R200_CP_CMD_BITBLT_MULTI | (5 << 16);
 356    cmd[2].i = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 357                RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 358                RADEON_GMC_BRUSH_NONE |
 359                (color_fmt << 8) |
 360                RADEON_GMC_SRC_DATATYPE_COLOR |
 361                RADEON_ROP3_S |
 362                RADEON_DP_SRC_SOURCE_MEMORY |
 363                RADEON_GMC_CLR_CMP_CNTL_DIS |
 364                RADEON_GMC_WR_MSK_DIS );
 365
 366    cmd[3].i = ((src_pitch/64)<<22) | (src_offset >> 10);
 367    cmd[4].i = ((dst_pitch/64)<<22) | (dst_offset >> 10);
 368    cmd[5].i = (srcx << 16) | srcy;
 369    cmd[6].i = (dstx << 16) | dsty; /* dst */
 370    cmd[7].i = (w << 16) | h;
 371 }
 372
 373
 374 void r200EmitWait( r200ContextPtr rmesa, GLuint flags )
 375 {
 376    if (rmesa->dri.drmMinor >= 6) {
 377       drm_radeon_cmd_header_t *cmd;
 378
 379       assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) );
 380
 381       cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int),
 382                                                    __FUNCTION__ );
 383       cmd[0].i = 0;
 384       cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
 385       cmd[0].wait.flags = flags;
 386    }
 387 }