src/mesa/drivers/dri/r200/r200_cmdbuf.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_cmdbuf.c,v 1.1 2002/10/30 12:51:51 alanh Exp $ */
   2 /*
   3 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4
   5 The Weather Channel (TM) funded Tungsten Graphics to develop the
   6 initial release of the Radeon 8500 driver under the XFree86 license.
   7 This notice must be preserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28 */
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "glheader.h"
  36 #include "imports.h"
  37 #include "macros.h"
  38 #include "context.h"
  39 #include "swrast/swrast.h"
  40 #include "simple_list.h"
  41
  42 #include "r200_context.h"
  43 #include "r200_state.h"
  44 #include "r200_ioctl.h"
  45 #include "r200_tcl.h"
  46 #include "r200_sanity.h"
  47 #include "radeon_reg.h"
  48
  49 static void print_state_atom( struct r200_state_atom *state )
  50 {
  51    int i;
  52
  53    fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size);
  54
  55    if (0 & R200_DEBUG & DEBUG_VERBOSE)
  56       for (i = 0 ; i < state->cmd_size ; i++)
  57          fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]);
  58
  59 }
  60
  61 static void r200_emit_state_list( r200ContextPtr rmesa,
  62                                     struct r200_state_atom *list )
  63 {
  64    struct r200_state_atom *state, *tmp;
  65    char *dest;
  66    int i, size, mtu;
  67
  68    size = 0;
  69    foreach_s( state, tmp, list ) {
  70       if (state->check( rmesa->glCtx, state->idx )) {
  71 /*       dest = r200AllocCmdBuf( rmesa, state->cmd_size * 4, __FUNCTION__);
  72          memcpy( dest, state->cmd, state->cmd_size * 4);*/
  73          size += state->cmd_size;
  74          state->dirty = GL_TRUE;
  75          move_to_head( &(rmesa->hw.clean), state );
  76          if (R200_DEBUG & DEBUG_STATE)
  77             print_state_atom( state );
  78       }
  79       else if (R200_DEBUG & DEBUG_STATE)
  80          fprintf(stderr, "skip state %s\n", state->name);
  81    }
  82
  83    if (!size)
  84       return;
  85
  86    dest = r200AllocCmdBuf( rmesa, size * 4, __FUNCTION__);
  87    mtu = rmesa->glCtx->Const.MaxTextureUnits;
  88
  89 #define EMIT_ATOM(ATOM) \
  90 do { \
  91    if (rmesa->hw.ATOM.dirty) { \
  92       rmesa->hw.ATOM.dirty = GL_FALSE; \
  93       memcpy( dest, rmesa->hw.ATOM.cmd, rmesa->hw.ATOM.cmd_size * 4); \
  94       dest += rmesa->hw.ATOM.cmd_size * 4; \
  95    } \
  96 } while (0)
  97
  98    EMIT_ATOM (ctx);
  99    EMIT_ATOM (set);
 100    EMIT_ATOM (lin);
 101    EMIT_ATOM (msk);
 102    EMIT_ATOM (vpt);
 103    EMIT_ATOM (vtx);
 104    EMIT_ATOM (vap);
 105    EMIT_ATOM (vte);
 106    EMIT_ATOM (msc);
 107    EMIT_ATOM (cst);
 108    EMIT_ATOM (zbs);
 109    EMIT_ATOM (tcl);
 110    EMIT_ATOM (msl);
 111    EMIT_ATOM (tcg);
 112    EMIT_ATOM (grd);
 113    EMIT_ATOM (fog);
 114    EMIT_ATOM (tam);
 115    EMIT_ATOM (tf);
 116    for (i = 0; i < mtu; ++i) {
 117        EMIT_ATOM (tex[i]);
 118    }
 119    for (i = 0; i < mtu; ++i) {
 120        EMIT_ATOM (cube[i]);
 121    }
 122    for (i = 0; i < 3 + mtu; ++i)
 123        EMIT_ATOM (mat[i]);
 124    EMIT_ATOM (eye);
 125    EMIT_ATOM (glt);
 126    for (i = 0; i < 2; ++i) {
 127       EMIT_ATOM (mtl[i]);
 128    }
 129    for (i = 0; i < 8; ++i)
 130        EMIT_ATOM (lit[i]);
 131    for (i = 0; i < 6; ++i)
 132        EMIT_ATOM (ucp[i]);
 133    for (i = 0; i < 6; ++i)
 134        EMIT_ATOM (pix[i]);
 135
 136 #undef EMIT_ATOM
 137
 138 }
 139
 140
 141 void r200EmitState( r200ContextPtr rmesa )
 142 {
 143    struct r200_state_atom *state, *tmp;
 144
 145    if (R200_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
 146       fprintf(stderr, "%s\n", __FUNCTION__);
 147
 148    /* Somewhat overkill:
 149     */
 150    if ( rmesa->lost_context) {
 151       if (R200_DEBUG & (DEBUG_STATE|DEBUG_PRIMS|DEBUG_IOCTL))
 152          fprintf(stderr, "%s - lost context\n", __FUNCTION__);
 153
 154       foreach_s( state, tmp, &(rmesa->hw.clean) )
 155          move_to_tail(&(rmesa->hw.dirty), state );
 156
 157       rmesa->lost_context = 0;
 158    }
 159 /*   else {
 160       move_to_tail( &rmesa->hw.dirty, &rmesa->hw.mtl[0] );*/
 161       /* odd bug? -- isosurf, cycle between reflect & lit */
 162 /*   }*/
 163
 164    r200_emit_state_list( rmesa, &rmesa->hw.dirty );
 165 }
 166
 167
 168
 169 /* Fire a section of the retained (indexed_verts) buffer as a regular
 170  * primtive.
 171  */
 172 extern void r200EmitVbufPrim( r200ContextPtr rmesa,
 173                                 GLuint primitive,
 174                                 GLuint vertex_nr )
 175 {
 176    drm_radeon_cmd_header_t *cmd;
 177
 178    assert(!(primitive & R200_VF_PRIM_WALK_IND));
 179
 180    r200EmitState( rmesa );
 181
 182    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 183       fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__,
 184               rmesa->store.cmd_used/4, primitive, vertex_nr);
 185
 186    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VBUF_BUFSZ,
 187                                                   __FUNCTION__ );
 188    cmd[0].i = 0;
 189    cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
 190    cmd[1].i = R200_CP_CMD_3D_DRAW_VBUF_2;
 191    cmd[2].i = (primitive |
 192                R200_VF_PRIM_WALK_LIST |
 193                R200_VF_COLOR_ORDER_RGBA |
 194                (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT));
 195 }
 196
 197
 198 void r200FlushElts( r200ContextPtr rmesa )
 199 {
 200    int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start);
 201    int dwords;
 202    int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 12)) / 2;
 203
 204    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 205       fprintf(stderr, "%s\n", __FUNCTION__);
 206
 207    assert( rmesa->dma.flush == r200FlushElts );
 208    rmesa->dma.flush = 0;
 209
 210    /* Cope with odd number of elts:
 211     */
 212    rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2;
 213    dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4;
 214
 215    cmd[1] |= (dwords - 3) << 16;
 216    cmd[2] |= nr << R200_VF_VERTEX_NUMBER_SHIFT;
 217
 218    if (R200_DEBUG & DEBUG_SYNC) {
 219       fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
 220       r200Finish( rmesa->glCtx );
 221    }
 222 }
 223
 224
 225 GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
 226                                     GLuint primitive,
 227                                     GLuint min_nr )
 228 {
 229    drm_radeon_cmd_header_t *cmd;
 230    GLushort *retval;
 231
 232    if (R200_DEBUG & DEBUG_IOCTL)
 233       fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
 234
 235    assert((primitive & R200_VF_PRIM_WALK_IND));
 236
 237    r200EmitState( rmesa );
 238
 239    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, ELTS_BUFSZ(min_nr),
 240                                                 __FUNCTION__ );
 241    cmd[0].i = 0;
 242    cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
 243    cmd[1].i = R200_CP_CMD_3D_DRAW_INDX_2;
 244    cmd[2].i = (primitive |
 245                R200_VF_PRIM_WALK_IND |
 246                R200_VF_COLOR_ORDER_RGBA);
 247
 248
 249    retval = (GLushort *)(cmd+3);
 250
 251    if (R200_DEBUG & DEBUG_PRIMS)
 252       fprintf(stderr, "%s: header 0x%x prim %x \n",
 253               __FUNCTION__,
 254               cmd[1].i, primitive);
 255
 256    assert(!rmesa->dma.flush);
 257    rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
 258    rmesa->dma.flush = r200FlushElts;
 259
 260    rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf;
 261
 262    return retval;
 263 }
 264
 265
 266
 267 void r200EmitVertexAOS( r200ContextPtr rmesa,
 268                           GLuint vertex_size,
 269                           GLuint offset )
 270 {
 271    drm_radeon_cmd_header_t *cmd;
 272
 273    if (R200_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
 274       fprintf(stderr, "%s:  vertex_size 0x%x offset 0x%x \n",
 275               __FUNCTION__, vertex_size, offset);
 276
 277    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VERT_AOS_BUFSZ,
 278                                                   __FUNCTION__ );
 279
 280    cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
 281    cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | (2 << 16);
 282    cmd[2].i = 1;
 283    cmd[3].i = vertex_size | (vertex_size << 8);
 284    cmd[4].i = offset;
 285 }
 286
 287
 288 void r200EmitAOS( r200ContextPtr rmesa,
 289                     struct r200_dma_region **component,
 290                     GLuint nr,
 291                     GLuint offset )
 292 {
 293    drm_radeon_cmd_header_t *cmd;
 294    int sz = AOS_BUFSZ(nr);
 295    int i;
 296    int *tmp;
 297
 298    if (R200_DEBUG & DEBUG_IOCTL)
 299       fprintf(stderr, "%s nr arrays: %d\n", __FUNCTION__, nr);
 300
 301    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, sz, __FUNCTION__ );
 302    cmd[0].i = 0;
 303    cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
 304    cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | (((sz / sizeof(int)) - 3) << 16);
 305    cmd[2].i = nr;
 306    tmp = &cmd[0].i;
 307    cmd += 3;
 308
 309    for (i = 0 ; i < nr ; i++) {
 310       if (i & 1) {
 311          cmd[0].i |= ((component[i]->aos_stride << 24) |
 312                       (component[i]->aos_size << 16));
 313          cmd[2].i = (component[i]->aos_start +
 314                      offset * component[i]->aos_stride * 4);
 315          cmd += 3;
 316       }
 317       else {
 318          cmd[0].i = ((component[i]->aos_stride << 8) |
 319                      (component[i]->aos_size << 0));
 320          cmd[1].i = (component[i]->aos_start +
 321                      offset * component[i]->aos_stride * 4);
 322       }
 323    }
 324
 325    if (R200_DEBUG & DEBUG_VERTS) {
 326       fprintf(stderr, "%s:\n", __FUNCTION__);
 327       for (i = 0 ; i < sz ; i++)
 328          fprintf(stderr, "   %d: %x\n", i, tmp[i]);
 329    }
 330 }
 331
 332 void r200EmitBlit( r200ContextPtr rmesa,
 333                    GLuint color_fmt,
 334                    GLuint src_pitch,
 335                    GLuint src_offset,
 336                    GLuint dst_pitch,
 337                    GLuint dst_offset,
 338                    GLint srcx, GLint srcy,
 339                    GLint dstx, GLint dsty,
 340                    GLuint w, GLuint h )
 341 {
 342    drm_radeon_cmd_header_t *cmd;
 343
 344    if (R200_DEBUG & DEBUG_IOCTL)
 345       fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
 346               __FUNCTION__,
 347               src_pitch, src_offset, srcx, srcy,
 348               dst_pitch, dst_offset, dstx, dsty,
 349               w, h);
 350
 351    assert( (src_pitch & 63) == 0 );
 352    assert( (dst_pitch & 63) == 0 );
 353    assert( (src_offset & 1023) == 0 );
 354    assert( (dst_offset & 1023) == 0 );
 355    assert( w < (1<<16) );
 356    assert( h < (1<<16) );
 357
 358    cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int),
 359                                                   __FUNCTION__ );
 360
 361
 362    cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
 363    cmd[1].i = R200_CP_CMD_BITBLT_MULTI | (5 << 16);
 364    cmd[2].i = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 365                RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 366                RADEON_GMC_BRUSH_NONE |
 367                (color_fmt << 8) |
 368                RADEON_GMC_SRC_DATATYPE_COLOR |
 369                RADEON_ROP3_S |
 370                RADEON_DP_SRC_SOURCE_MEMORY |
 371                RADEON_GMC_CLR_CMP_CNTL_DIS |
 372                RADEON_GMC_WR_MSK_DIS );
 373
 374    cmd[3].i = ((src_pitch/64)<<22) | (src_offset >> 10);
 375    cmd[4].i = ((dst_pitch/64)<<22) | (dst_offset >> 10);
 376    cmd[5].i = (srcx << 16) | srcy;
 377    cmd[6].i = (dstx << 16) | dsty; /* dst */
 378    cmd[7].i = (w << 16) | h;
 379 }
 380
 381
 382 void r200EmitWait( r200ContextPtr rmesa, GLuint flags )
 383 {
 384    if (rmesa->dri.drmMinor >= 6) {
 385       drm_radeon_cmd_header_t *cmd;
 386
 387       assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) );
 388
 389       cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int),
 390                                                    __FUNCTION__ );
 391       cmd[0].i = 0;
 392       cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
 393       cmd[0].wait.flags = flags;
 394    }
 395 }