2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/macros.h"
37 #include "main/context.h"
38 #include "swrast/swrast.h"
39 #include "main/simple_list.h"
41 #include "radeon_common.h"
42 #include "r200_context.h"
43 #include "r200_state.h"
44 #include "r200_ioctl.h"
46 #include "r200_sanity.h"
47 #include "radeon_reg.h"
49 /* The state atoms will be emitted in the order they appear in the atom list,
50 * so this step is important.
52 #define insert_at_tail_if(atom_list, atom) \
54 struct radeon_state_atom* __atom = (atom); \
56 insert_at_tail((atom_list), __atom); \
59 void r200SetUpAtomList( r200ContextPtr rmesa
)
63 mtu
= rmesa
->radeon
.glCtx
->Const
.MaxTextureUnits
;
65 make_empty_list(&rmesa
->radeon
.hw
.atomlist
);
66 rmesa
->radeon
.hw
.atomlist
.name
= "atom-list";
68 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.ctx
);
69 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.set
);
70 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.lin
);
71 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.msk
);
72 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vpt
);
73 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vtx
);
74 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vap
);
75 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vte
);
76 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.msc
);
77 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.cst
);
78 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.zbs
);
79 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.tcl
);
80 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.msl
);
81 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.tcg
);
82 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.grd
);
83 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.fog
);
84 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.tam
);
85 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.tf
);
86 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.atf
);
87 for (i
= 0; i
< mtu
; ++i
)
88 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.tex
[i
] );
89 for (i
= 0; i
< mtu
; ++i
)
90 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.cube
[i
] );
91 for (i
= 0; i
< 6; ++i
)
92 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.pix
[i
] );
93 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.afs
[0] );
94 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.afs
[1] );
95 for (i
= 0; i
< 8; ++i
)
96 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.lit
[i
] );
97 for (i
= 0; i
< 3 + mtu
; ++i
)
98 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.mat
[i
] );
99 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.eye
);
100 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.glt
);
101 for (i
= 0; i
< 2; ++i
)
102 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.mtl
[i
] );
103 for (i
= 0; i
< 6; ++i
)
104 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.ucp
[i
] );
105 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.spr
);
106 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.ptp
);
107 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.prf
);
108 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.pvs
);
109 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vpp
[0] );
110 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vpp
[1] );
111 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vpi
[0] );
112 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vpi
[1] );
113 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.sci
);
116 /* Fire a section of the retained (indexed_verts) buffer as a regular
119 void r200EmitVbufPrim( r200ContextPtr rmesa
,
123 BATCH_LOCALS(&rmesa
->radeon
);
125 assert(!(primitive
& R200_VF_PRIM_WALK_IND
));
127 radeonEmitState(&rmesa
->radeon
);
129 radeon_print(RADEON_RENDER
|RADEON_SWRENDER
,RADEON_VERBOSE
,
130 "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__
,
131 rmesa
->store
.cmd_used
/4, primitive
, vertex_nr
);
134 OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2
, 0);
135 OUT_BATCH(primitive
| R200_VF_PRIM_WALK_LIST
| R200_VF_COLOR_ORDER_RGBA
|
136 (vertex_nr
<< R200_VF_VERTEX_NUMBER_SHIFT
));
140 static void r200FireEB(r200ContextPtr rmesa
, int vertex_count
, int type
)
142 BATCH_LOCALS(&rmesa
->radeon
);
144 if (vertex_count
> 0) {
146 OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_INDX_2
, 0);
147 OUT_BATCH(R200_VF_PRIM_WALK_IND
|
148 R200_VF_COLOR_ORDER_RGBA
|
149 ((vertex_count
+ 0) << 16) |
152 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
153 OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER
, 2);
154 OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
155 OUT_BATCH_RELOC(rmesa
->radeon
.tcl
.elt_dma_offset
,
156 rmesa
->radeon
.tcl
.elt_dma_bo
,
157 rmesa
->radeon
.tcl
.elt_dma_offset
,
158 RADEON_GEM_DOMAIN_GTT
, 0, 0);
159 OUT_BATCH((vertex_count
+ 1)/2);
161 OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER
, 2);
162 OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
163 OUT_BATCH(rmesa
->radeon
.tcl
.elt_dma_offset
);
164 OUT_BATCH((vertex_count
+ 1)/2);
165 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
166 rmesa
->radeon
.tcl
.elt_dma_bo
,
167 RADEON_GEM_DOMAIN_GTT
, 0, 0);
173 void r200FlushElts(GLcontext
*ctx
)
175 r200ContextPtr rmesa
= R200_CONTEXT(ctx
);
176 int nr
, elt_used
= rmesa
->tcl
.elt_used
;
178 radeon_print(RADEON_RENDER
, RADEON_VERBOSE
, "%s %x %d\n", __FUNCTION__
, rmesa
->tcl
.hw_primitive
, elt_used
);
180 assert( rmesa
->radeon
.dma
.flush
== r200FlushElts
);
181 rmesa
->radeon
.dma
.flush
= NULL
;
185 radeon_bo_unmap(rmesa
->radeon
.tcl
.elt_dma_bo
);
187 r200FireEB(rmesa
, nr
, rmesa
->tcl
.hw_primitive
);
189 radeon_bo_unref(rmesa
->radeon
.tcl
.elt_dma_bo
);
190 rmesa
->radeon
.tcl
.elt_dma_bo
= NULL
;
192 if (R200_ELT_BUF_SZ
> elt_used
)
193 radeonReturnDmaRegion(&rmesa
->radeon
, R200_ELT_BUF_SZ
- elt_used
);
195 if (radeon_is_debug_enabled(RADEON_SYNC
, RADEON_CRITICAL
)) {
196 radeon_print(RADEON_SYNC
, RADEON_NORMAL
, "%s: Syncing\n", __FUNCTION__
);
197 radeonFinish( rmesa
->radeon
.glCtx
);
202 GLushort
*r200AllocEltsOpenEnded( r200ContextPtr rmesa
,
208 radeon_print(RADEON_RENDER
, RADEON_VERBOSE
, "%s %d prim %x\n", __FUNCTION__
, min_nr
, primitive
);
210 assert((primitive
& R200_VF_PRIM_WALK_IND
));
212 radeonEmitState(&rmesa
->radeon
);
214 radeonAllocDmaRegion(&rmesa
->radeon
, &rmesa
->radeon
.tcl
.elt_dma_bo
,
215 &rmesa
->radeon
.tcl
.elt_dma_offset
, R200_ELT_BUF_SZ
, 4);
216 rmesa
->tcl
.elt_used
= min_nr
* 2;
218 radeon_bo_map(rmesa
->radeon
.tcl
.elt_dma_bo
, 1);
219 retval
= rmesa
->radeon
.tcl
.elt_dma_bo
->ptr
+ rmesa
->radeon
.tcl
.elt_dma_offset
;
221 assert(!rmesa
->radeon
.dma
.flush
);
222 rmesa
->radeon
.glCtx
->Driver
.NeedFlush
|= FLUSH_STORED_VERTICES
;
223 rmesa
->radeon
.dma
.flush
= r200FlushElts
;
228 void r200EmitMaxVtxIndex(r200ContextPtr rmesa
, int count
)
230 BATCH_LOCALS(&rmesa
->radeon
);
232 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
233 BEGIN_BATCH_NO_AUTOSTATE(2);
234 OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX
, 0));
240 void r200EmitVertexAOS( r200ContextPtr rmesa
,
242 struct radeon_bo
*bo
,
245 BATCH_LOCALS(&rmesa
->radeon
);
247 radeon_print(RADEON_SWRENDER
, RADEON_VERBOSE
, "%s: vertex_size 0x%x offset 0x%x \n",
248 __FUNCTION__
, vertex_size
, offset
);
252 OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR
, 2);
254 OUT_BATCH(vertex_size
| (vertex_size
<< 8));
255 OUT_BATCH_RELOC(offset
, bo
, offset
, RADEON_GEM_DOMAIN_GTT
, 0, 0);
259 void r200EmitAOS(r200ContextPtr rmesa
, GLuint nr
, GLuint offset
)
261 BATCH_LOCALS(&rmesa
->radeon
);
263 int sz
= 1 + (nr
>> 1) * 3 + (nr
& 1) * 2;
266 radeon_print(RADEON_RENDER
, RADEON_VERBOSE
,
267 "%s: nr=%d, ofs=0x%08x\n",
268 __FUNCTION__
, nr
, offset
);
270 BEGIN_BATCH(sz
+2+ (nr
*2));
271 OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR
, sz
- 1);
275 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
276 for (i
= 0; i
+ 1 < nr
; i
+= 2) {
277 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[i
].components
<< 0) |
278 (rmesa
->radeon
.tcl
.aos
[i
].stride
<< 8) |
279 (rmesa
->radeon
.tcl
.aos
[i
+ 1].components
<< 16) |
280 (rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
<< 24));
282 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 0].offset
+
283 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 0].stride
;
284 OUT_BATCH_RELOC(voffset
,
285 rmesa
->radeon
.tcl
.aos
[i
].bo
,
287 RADEON_GEM_DOMAIN_GTT
,
289 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 1].offset
+
290 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
;
291 OUT_BATCH_RELOC(voffset
,
292 rmesa
->radeon
.tcl
.aos
[i
+1].bo
,
294 RADEON_GEM_DOMAIN_GTT
,
299 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[nr
- 1].components
<< 0) |
300 (rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
<< 8));
301 voffset
= rmesa
->radeon
.tcl
.aos
[nr
- 1].offset
+
302 offset
* 4 * rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
;
303 OUT_BATCH_RELOC(voffset
,
304 rmesa
->radeon
.tcl
.aos
[nr
- 1].bo
,
306 RADEON_GEM_DOMAIN_GTT
,
310 for (i
= 0; i
+ 1 < nr
; i
+= 2) {
311 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[i
].components
<< 0) |
312 (rmesa
->radeon
.tcl
.aos
[i
].stride
<< 8) |
313 (rmesa
->radeon
.tcl
.aos
[i
+ 1].components
<< 16) |
314 (rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
<< 24));
316 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 0].offset
+
317 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 0].stride
;
319 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 1].offset
+
320 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
;
325 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[nr
- 1].components
<< 0) |
326 (rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
<< 8));
327 voffset
= rmesa
->radeon
.tcl
.aos
[nr
- 1].offset
+
328 offset
* 4 * rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
;
331 for (i
= 0; i
+ 1 < nr
; i
+= 2) {
332 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 0].offset
+
333 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 0].stride
;
334 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
335 rmesa
->radeon
.tcl
.aos
[i
+0].bo
,
336 RADEON_GEM_DOMAIN_GTT
,
338 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 1].offset
+
339 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
;
340 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
341 rmesa
->radeon
.tcl
.aos
[i
+1].bo
,
342 RADEON_GEM_DOMAIN_GTT
,
346 voffset
= rmesa
->radeon
.tcl
.aos
[nr
- 1].offset
+
347 offset
* 4 * rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
;
348 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
349 rmesa
->radeon
.tcl
.aos
[nr
-1].bo
,
350 RADEON_GEM_DOMAIN_GTT
,