2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/macros.h"
37 #include "main/context.h"
38 #include "swrast/swrast.h"
39 #include "main/simple_list.h"
41 #include "radeon_common.h"
42 #include "r200_context.h"
43 #include "r200_state.h"
44 #include "r200_ioctl.h"
46 #include "r200_sanity.h"
47 #include "radeon_reg.h"
49 /* The state atoms will be emitted in the order they appear in the atom list,
50 * so this step is important.
52 #define insert_at_tail_if(atom_list, atom) \
54 struct radeon_state_atom* __atom = (atom); \
56 insert_at_tail((atom_list), __atom); \
59 void r200SetUpAtomList( r200ContextPtr rmesa
)
63 mtu
= rmesa
->radeon
.glCtx
->Const
.MaxTextureUnits
;
65 make_empty_list(&rmesa
->radeon
.hw
.atomlist
);
66 rmesa
->radeon
.hw
.atomlist
.name
= "atom-list";
68 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.ctx
);
69 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.set
);
70 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.lin
);
71 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.msk
);
72 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vpt
);
73 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vtx
);
74 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vap
);
75 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vte
);
76 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.msc
);
77 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.cst
);
78 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.zbs
);
79 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.tcl
);
80 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.msl
);
81 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.tcg
);
82 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.grd
);
83 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.fog
);
84 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.tam
);
85 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.tf
);
86 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.atf
);
87 for (i
= 0; i
< mtu
; ++i
)
88 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.tex
[i
] );
89 for (i
= 0; i
< mtu
; ++i
)
90 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.cube
[i
] );
91 for (i
= 0; i
< 6; ++i
)
92 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.pix
[i
] );
93 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.afs
[0] );
94 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.afs
[1] );
95 for (i
= 0; i
< 8; ++i
)
96 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.lit
[i
] );
97 for (i
= 0; i
< 3 + mtu
; ++i
)
98 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.mat
[i
] );
99 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.eye
);
100 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.glt
);
101 for (i
= 0; i
< 2; ++i
)
102 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.mtl
[i
] );
103 for (i
= 0; i
< 6; ++i
)
104 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.ucp
[i
] );
105 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.spr
);
106 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.ptp
);
107 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.prf
);
108 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.pvs
);
109 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vpp
[0] );
110 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vpp
[1] );
111 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vpi
[0] );
112 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vpi
[1] );
113 insert_at_tail_if( &rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.sci
);
116 /* Fire a section of the retained (indexed_verts) buffer as a regular
119 void r200EmitVbufPrim( r200ContextPtr rmesa
,
123 BATCH_LOCALS(&rmesa
->radeon
);
125 assert(!(primitive
& R200_VF_PRIM_WALK_IND
));
127 radeonEmitState(&rmesa
->radeon
);
129 if (R200_DEBUG
& (DEBUG_IOCTL
|DEBUG_PRIMS
))
130 fprintf(stderr
, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__
,
131 rmesa
->store
.cmd_used
/4, primitive
, vertex_nr
);
134 OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2
, 0);
135 OUT_BATCH(primitive
| R200_VF_PRIM_WALK_LIST
| R200_VF_COLOR_ORDER_RGBA
|
136 (vertex_nr
<< R200_VF_VERTEX_NUMBER_SHIFT
));
140 static void r200FireEB(r200ContextPtr rmesa
, int vertex_count
, int type
)
142 BATCH_LOCALS(&rmesa
->radeon
);
144 if (vertex_count
> 0) {
146 OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_INDX_2
, 0);
147 OUT_BATCH(R200_VF_PRIM_WALK_IND
|
148 R200_VF_COLOR_ORDER_RGBA
|
149 ((vertex_count
+ 0) << 16) |
152 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
153 OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER
, 2);
154 OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
155 OUT_BATCH_RELOC(rmesa
->radeon
.tcl
.elt_dma_offset
,
156 rmesa
->radeon
.tcl
.elt_dma_bo
,
157 rmesa
->radeon
.tcl
.elt_dma_offset
,
158 RADEON_GEM_DOMAIN_GTT
, 0, 0);
159 OUT_BATCH((vertex_count
+ 1)/2);
161 OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER
, 2);
162 OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
163 OUT_BATCH(rmesa
->radeon
.tcl
.elt_dma_offset
);
164 OUT_BATCH((vertex_count
+ 1)/2);
165 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
166 rmesa
->radeon
.tcl
.elt_dma_bo
,
167 RADEON_GEM_DOMAIN_GTT
, 0, 0);
173 void r200FlushElts(GLcontext
*ctx
)
175 r200ContextPtr rmesa
= R200_CONTEXT(ctx
);
176 int nr
, elt_used
= rmesa
->tcl
.elt_used
;
178 if (R200_DEBUG
& (DEBUG_IOCTL
|DEBUG_PRIMS
))
179 fprintf(stderr
, "%s %x %d\n", __FUNCTION__
, rmesa
->tcl
.hw_primitive
, elt_used
);
181 assert( rmesa
->radeon
.dma
.flush
== r200FlushElts
);
182 rmesa
->radeon
.dma
.flush
= NULL
;
186 radeon_bo_unmap(rmesa
->radeon
.tcl
.elt_dma_bo
);
188 r200FireEB(rmesa
, nr
, rmesa
->tcl
.hw_primitive
);
190 radeon_bo_unref(rmesa
->radeon
.tcl
.elt_dma_bo
);
191 rmesa
->radeon
.tcl
.elt_dma_bo
= NULL
;
193 if (R200_ELT_BUF_SZ
> elt_used
)
194 radeonReturnDmaRegion(&rmesa
->radeon
, R200_ELT_BUF_SZ
- elt_used
);
196 if (R200_DEBUG
& DEBUG_SYNC
) {
197 fprintf(stderr
, "%s: Syncing\n", __FUNCTION__
);
198 radeonFinish( rmesa
->radeon
.glCtx
);
203 GLushort
*r200AllocEltsOpenEnded( r200ContextPtr rmesa
,
209 if (R200_DEBUG
& DEBUG_IOCTL
)
210 fprintf(stderr
, "%s %d prim %x\n", __FUNCTION__
, min_nr
, primitive
);
212 assert((primitive
& R200_VF_PRIM_WALK_IND
));
214 radeonEmitState(&rmesa
->radeon
);
216 radeonAllocDmaRegion(&rmesa
->radeon
, &rmesa
->radeon
.tcl
.elt_dma_bo
,
217 &rmesa
->radeon
.tcl
.elt_dma_offset
, R200_ELT_BUF_SZ
, 4);
218 rmesa
->tcl
.elt_used
= min_nr
* 2;
220 radeon_bo_map(rmesa
->radeon
.tcl
.elt_dma_bo
, 1);
221 retval
= rmesa
->radeon
.tcl
.elt_dma_bo
->ptr
+ rmesa
->radeon
.tcl
.elt_dma_offset
;
223 if (R200_DEBUG
& DEBUG_PRIMS
)
224 fprintf(stderr
, "%s: header prim %x \n",
225 __FUNCTION__
, primitive
);
227 assert(!rmesa
->radeon
.dma
.flush
);
228 rmesa
->radeon
.glCtx
->Driver
.NeedFlush
|= FLUSH_STORED_VERTICES
;
229 rmesa
->radeon
.dma
.flush
= r200FlushElts
;
236 void r200EmitVertexAOS( r200ContextPtr rmesa
,
238 struct radeon_bo
*bo
,
241 BATCH_LOCALS(&rmesa
->radeon
);
243 if (R200_DEBUG
& (DEBUG_PRIMS
|DEBUG_IOCTL
))
244 fprintf(stderr
, "%s: vertex_size 0x%x offset 0x%x \n",
245 __FUNCTION__
, vertex_size
, offset
);
249 OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR
, 2);
251 OUT_BATCH(vertex_size
| (vertex_size
<< 8));
252 OUT_BATCH_RELOC(offset
, bo
, offset
, RADEON_GEM_DOMAIN_GTT
, 0, 0);
256 void r200EmitAOS(r200ContextPtr rmesa
, GLuint nr
, GLuint offset
)
258 BATCH_LOCALS(&rmesa
->radeon
);
260 int sz
= 1 + (nr
>> 1) * 3 + (nr
& 1) * 2;
263 if (RADEON_DEBUG
& DEBUG_VERTS
)
264 fprintf(stderr
, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__
, nr
,
267 BEGIN_BATCH(sz
+2+ (nr
*2));
268 OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR
, sz
- 1);
272 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
273 for (i
= 0; i
+ 1 < nr
; i
+= 2) {
274 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[i
].components
<< 0) |
275 (rmesa
->radeon
.tcl
.aos
[i
].stride
<< 8) |
276 (rmesa
->radeon
.tcl
.aos
[i
+ 1].components
<< 16) |
277 (rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
<< 24));
279 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 0].offset
+
280 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 0].stride
;
281 OUT_BATCH_RELOC(voffset
,
282 rmesa
->radeon
.tcl
.aos
[i
].bo
,
284 RADEON_GEM_DOMAIN_GTT
,
286 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 1].offset
+
287 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
;
288 OUT_BATCH_RELOC(voffset
,
289 rmesa
->radeon
.tcl
.aos
[i
+1].bo
,
291 RADEON_GEM_DOMAIN_GTT
,
296 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[nr
- 1].components
<< 0) |
297 (rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
<< 8));
298 voffset
= rmesa
->radeon
.tcl
.aos
[nr
- 1].offset
+
299 offset
* 4 * rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
;
300 OUT_BATCH_RELOC(voffset
,
301 rmesa
->radeon
.tcl
.aos
[nr
- 1].bo
,
303 RADEON_GEM_DOMAIN_GTT
,
307 for (i
= 0; i
+ 1 < nr
; i
+= 2) {
308 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[i
].components
<< 0) |
309 (rmesa
->radeon
.tcl
.aos
[i
].stride
<< 8) |
310 (rmesa
->radeon
.tcl
.aos
[i
+ 1].components
<< 16) |
311 (rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
<< 24));
313 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 0].offset
+
314 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 0].stride
;
316 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 1].offset
+
317 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
;
322 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[nr
- 1].components
<< 0) |
323 (rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
<< 8));
324 voffset
= rmesa
->radeon
.tcl
.aos
[nr
- 1].offset
+
325 offset
* 4 * rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
;
328 for (i
= 0; i
+ 1 < nr
; i
+= 2) {
329 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 0].offset
+
330 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 0].stride
;
331 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
332 rmesa
->radeon
.tcl
.aos
[i
+0].bo
,
333 RADEON_GEM_DOMAIN_GTT
,
335 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 1].offset
+
336 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
;
337 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
338 rmesa
->radeon
.tcl
.aos
[i
+1].bo
,
339 RADEON_GEM_DOMAIN_GTT
,
343 voffset
= rmesa
->radeon
.tcl
.aos
[nr
- 1].offset
+
344 offset
* 4 * rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
;
345 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
346 rmesa
->radeon
.tcl
.aos
[nr
-1].bo
,
347 RADEON_GEM_DOMAIN_GTT
,