2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/macros.h"
37 #include "main/context.h"
38 #include "swrast/swrast.h"
39 #include "main/simple_list.h"
41 #include "r200_context.h"
42 #include "r200_state.h"
43 #include "r200_ioctl.h"
45 #include "r200_sanity.h"
46 #include "radeon_reg.h"
48 static void print_state_atom( struct r200_state_atom
*state
)
52 fprintf(stderr
, "emit %s/%d\n", state
->name
, state
->cmd_size
);
54 if (0 & R200_DEBUG
& DEBUG_VERBOSE
)
55 for (i
= 0 ; i
< state
->cmd_size
; i
++)
56 fprintf(stderr
, "\t%s[%d]: %x\n", state
->name
, i
, state
->cmd
[i
]);
60 /* The state atoms will be emitted in the order they appear in the atom list,
61 * so this step is important.
63 void r200SetUpAtomList( r200ContextPtr rmesa
)
67 mtu
= rmesa
->glCtx
->Const
.MaxTextureUnits
;
69 make_empty_list(&rmesa
->hw
.atomlist
);
70 rmesa
->hw
.atomlist
.name
= "atom-list";
72 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.ctx
);
73 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.set
);
74 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.lin
);
75 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.msk
);
76 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.vpt
);
77 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.vtx
);
78 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.vap
);
79 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.vte
);
80 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.msc
);
81 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.cst
);
82 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.zbs
);
83 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.tcl
);
84 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.msl
);
85 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.tcg
);
86 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.grd
);
87 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.fog
);
88 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.tam
);
89 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.tf
);
90 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.atf
);
91 for (i
= 0; i
< mtu
; ++i
)
92 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.tex
[i
] );
93 for (i
= 0; i
< mtu
; ++i
)
94 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.cube
[i
] );
95 for (i
= 0; i
< 6; ++i
)
96 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.pix
[i
] );
97 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.afs
[0] );
98 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.afs
[1] );
99 for (i
= 0; i
< 8; ++i
)
100 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.lit
[i
] );
101 for (i
= 0; i
< 3 + mtu
; ++i
)
102 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.mat
[i
] );
103 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.eye
);
104 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.glt
);
105 for (i
= 0; i
< 2; ++i
)
106 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.mtl
[i
] );
107 for (i
= 0; i
< 6; ++i
)
108 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.ucp
[i
] );
109 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.spr
);
110 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.ptp
);
111 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.prf
);
112 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.pvs
);
113 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.vpp
[0] );
114 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.vpp
[1] );
115 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.vpi
[0] );
116 insert_at_tail( &rmesa
->hw
.atomlist
, &rmesa
->hw
.vpi
[1] );
119 static void r200SaveHwState( r200ContextPtr rmesa
)
121 struct r200_state_atom
*atom
;
122 char * dest
= rmesa
->backup_store
.cmd_buf
;
124 if (R200_DEBUG
& DEBUG_STATE
)
125 fprintf(stderr
, "%s\n", __FUNCTION__
);
127 rmesa
->backup_store
.cmd_used
= 0;
129 foreach( atom
, &rmesa
->hw
.atomlist
) {
130 if ( atom
->check( rmesa
->glCtx
, atom
->idx
) ) {
131 int size
= atom
->cmd_size
* 4;
132 memcpy( dest
, atom
->cmd
, size
);
134 rmesa
->backup_store
.cmd_used
+= size
;
135 if (R200_DEBUG
& DEBUG_STATE
)
136 print_state_atom( atom
);
140 assert( rmesa
->backup_store
.cmd_used
<= R200_CMD_BUF_SZ
);
141 if (R200_DEBUG
& DEBUG_STATE
)
142 fprintf(stderr
, "Returning to r200EmitState\n");
145 void r200EmitState( r200ContextPtr rmesa
)
149 struct r200_state_atom
*atom
;
151 if (R200_DEBUG
& (DEBUG_STATE
|DEBUG_PRIMS
))
152 fprintf(stderr
, "%s\n", __FUNCTION__
);
154 if (rmesa
->save_on_next_emit
) {
155 r200SaveHwState(rmesa
);
156 rmesa
->save_on_next_emit
= GL_FALSE
;
159 if (!rmesa
->hw
.is_dirty
&& !rmesa
->hw
.all_dirty
)
162 mtu
= rmesa
->glCtx
->Const
.MaxTextureUnits
;
164 /* To avoid going across the entire set of states multiple times, just check
165 * for enough space for the case of emitting all state, and inline the
166 * r200AllocCmdBuf code here without all the checks.
168 r200EnsureCmdBufSpace( rmesa
, rmesa
->hw
.max_state_size
);
170 /* we need to calculate dest after EnsureCmdBufSpace
171 as we may flush the buffer - airlied */
172 dest
= rmesa
->store
.cmd_buf
+ rmesa
->store
.cmd_used
;
173 if (R200_DEBUG
& DEBUG_STATE
) {
174 foreach( atom
, &rmesa
->hw
.atomlist
) {
175 if ( atom
->dirty
|| rmesa
->hw
.all_dirty
) {
176 if ( atom
->check( rmesa
->glCtx
, atom
->idx
) )
177 print_state_atom( atom
);
179 fprintf(stderr
, "skip state %s\n", atom
->name
);
184 foreach( atom
, &rmesa
->hw
.atomlist
) {
185 if ( rmesa
->hw
.all_dirty
)
186 atom
->dirty
= GL_TRUE
;
188 if ( atom
->check( rmesa
->glCtx
, atom
->idx
) ) {
189 int size
= atom
->cmd_size
* 4;
190 memcpy( dest
, atom
->cmd
, size
);
192 rmesa
->store
.cmd_used
+= size
;
193 atom
->dirty
= GL_FALSE
;
198 assert( rmesa
->store
.cmd_used
<= R200_CMD_BUF_SZ
);
200 rmesa
->hw
.is_dirty
= GL_FALSE
;
201 rmesa
->hw
.all_dirty
= GL_FALSE
;
204 /* Fire a section of the retained (indexed_verts) buffer as a regular
207 void r200EmitVbufPrim( r200ContextPtr rmesa
,
211 drm_radeon_cmd_header_t
*cmd
;
213 assert(!(primitive
& R200_VF_PRIM_WALK_IND
));
215 r200EmitState( rmesa
);
217 if (R200_DEBUG
& (DEBUG_IOCTL
|DEBUG_PRIMS
))
218 fprintf(stderr
, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__
,
219 rmesa
->store
.cmd_used
/4, primitive
, vertex_nr
);
221 cmd
= (drm_radeon_cmd_header_t
*)r200AllocCmdBuf( rmesa
, VBUF_BUFSZ
,
224 cmd
[0].header
.cmd_type
= RADEON_CMD_PACKET3_CLIP
;
225 cmd
[1].i
= R200_CP_CMD_3D_DRAW_VBUF_2
;
226 cmd
[2].i
= (primitive
|
227 R200_VF_PRIM_WALK_LIST
|
228 R200_VF_COLOR_ORDER_RGBA
|
229 (vertex_nr
<< R200_VF_VERTEX_NUMBER_SHIFT
));
233 void r200FlushElts( r200ContextPtr rmesa
)
235 int *cmd
= (int *)(rmesa
->store
.cmd_buf
+ rmesa
->store
.elts_start
);
237 int nr
= (rmesa
->store
.cmd_used
- (rmesa
->store
.elts_start
+ 12)) / 2;
239 if (R200_DEBUG
& (DEBUG_IOCTL
|DEBUG_PRIMS
))
240 fprintf(stderr
, "%s\n", __FUNCTION__
);
242 assert( rmesa
->dma
.flush
== r200FlushElts
);
243 rmesa
->dma
.flush
= NULL
;
245 /* Cope with odd number of elts:
247 rmesa
->store
.cmd_used
= (rmesa
->store
.cmd_used
+ 2) & ~2;
248 dwords
= (rmesa
->store
.cmd_used
- rmesa
->store
.elts_start
) / 4;
250 cmd
[1] |= (dwords
- 3) << 16;
251 cmd
[2] |= nr
<< R200_VF_VERTEX_NUMBER_SHIFT
;
253 if (R200_DEBUG
& DEBUG_SYNC
) {
254 fprintf(stderr
, "%s: Syncing\n", __FUNCTION__
);
255 r200Finish( rmesa
->glCtx
);
260 GLushort
*r200AllocEltsOpenEnded( r200ContextPtr rmesa
,
264 drm_radeon_cmd_header_t
*cmd
;
267 if (R200_DEBUG
& DEBUG_IOCTL
)
268 fprintf(stderr
, "%s %d prim %x\n", __FUNCTION__
, min_nr
, primitive
);
270 assert((primitive
& R200_VF_PRIM_WALK_IND
));
272 r200EmitState( rmesa
);
274 cmd
= (drm_radeon_cmd_header_t
*)r200AllocCmdBuf( rmesa
, ELTS_BUFSZ(min_nr
),
277 cmd
[0].header
.cmd_type
= RADEON_CMD_PACKET3_CLIP
;
278 cmd
[1].i
= R200_CP_CMD_3D_DRAW_INDX_2
;
279 cmd
[2].i
= (primitive
|
280 R200_VF_PRIM_WALK_IND
|
281 R200_VF_COLOR_ORDER_RGBA
);
284 retval
= (GLushort
*)(cmd
+3);
286 if (R200_DEBUG
& DEBUG_PRIMS
)
287 fprintf(stderr
, "%s: header 0x%x prim %x \n",
289 cmd
[1].i
, primitive
);
291 assert(!rmesa
->dma
.flush
);
292 rmesa
->glCtx
->Driver
.NeedFlush
|= FLUSH_STORED_VERTICES
;
293 rmesa
->dma
.flush
= r200FlushElts
;
295 rmesa
->store
.elts_start
= ((char *)cmd
) - rmesa
->store
.cmd_buf
;
302 void r200EmitVertexAOS( r200ContextPtr rmesa
,
306 drm_radeon_cmd_header_t
*cmd
;
308 if (R200_DEBUG
& (DEBUG_PRIMS
|DEBUG_IOCTL
))
309 fprintf(stderr
, "%s: vertex_size 0x%x offset 0x%x \n",
310 __FUNCTION__
, vertex_size
, offset
);
312 cmd
= (drm_radeon_cmd_header_t
*)r200AllocCmdBuf( rmesa
, VERT_AOS_BUFSZ
,
315 cmd
[0].header
.cmd_type
= RADEON_CMD_PACKET3
;
316 cmd
[1].i
= R200_CP_CMD_3D_LOAD_VBPNTR
| (2 << 16);
318 cmd
[3].i
= vertex_size
| (vertex_size
<< 8);
323 void r200EmitAOS( r200ContextPtr rmesa
,
324 struct radeon_dma_region
**component
,
328 drm_radeon_cmd_header_t
*cmd
;
329 int sz
= AOS_BUFSZ(nr
);
333 if (R200_DEBUG
& DEBUG_IOCTL
)
334 fprintf(stderr
, "%s nr arrays: %d\n", __FUNCTION__
, nr
);
336 cmd
= (drm_radeon_cmd_header_t
*)r200AllocCmdBuf( rmesa
, sz
, __FUNCTION__
);
338 cmd
[0].header
.cmd_type
= RADEON_CMD_PACKET3
;
339 cmd
[1].i
= R200_CP_CMD_3D_LOAD_VBPNTR
| (((sz
/ sizeof(int)) - 3) << 16);
344 for (i
= 0 ; i
< nr
; i
++) {
346 cmd
[0].i
|= ((component
[i
]->aos_stride
<< 24) |
347 (component
[i
]->aos_size
<< 16));
348 cmd
[2].i
= (component
[i
]->aos_start
+
349 offset
* component
[i
]->aos_stride
* 4);
353 cmd
[0].i
= ((component
[i
]->aos_stride
<< 8) |
354 (component
[i
]->aos_size
<< 0));
355 cmd
[1].i
= (component
[i
]->aos_start
+
356 offset
* component
[i
]->aos_stride
* 4);
360 if (R200_DEBUG
& DEBUG_VERTS
) {
361 fprintf(stderr
, "%s:\n", __FUNCTION__
);
362 for (i
= 0 ; i
< sz
; i
++)
363 fprintf(stderr
, " %d: %x\n", i
, tmp
[i
]);
367 void r200EmitBlit( r200ContextPtr rmesa
,
373 GLint srcx
, GLint srcy
,
374 GLint dstx
, GLint dsty
,
377 drm_radeon_cmd_header_t
*cmd
;
379 if (R200_DEBUG
& DEBUG_IOCTL
)
380 fprintf(stderr
, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
382 src_pitch
, src_offset
, srcx
, srcy
,
383 dst_pitch
, dst_offset
, dstx
, dsty
,
386 assert( (src_pitch
& 63) == 0 );
387 assert( (dst_pitch
& 63) == 0 );
388 assert( (src_offset
& 1023) == 0 );
389 assert( (dst_offset
& 1023) == 0 );
390 assert( w
< (1<<16) );
391 assert( h
< (1<<16) );
393 cmd
= (drm_radeon_cmd_header_t
*)r200AllocCmdBuf( rmesa
, 8 * sizeof(int),
397 cmd
[0].header
.cmd_type
= RADEON_CMD_PACKET3
;
398 cmd
[1].i
= R200_CP_CMD_BITBLT_MULTI
| (5 << 16);
399 cmd
[2].i
= (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
|
400 RADEON_GMC_DST_PITCH_OFFSET_CNTL
|
401 RADEON_GMC_BRUSH_NONE
|
403 RADEON_GMC_SRC_DATATYPE_COLOR
|
405 RADEON_DP_SRC_SOURCE_MEMORY
|
406 RADEON_GMC_CLR_CMP_CNTL_DIS
|
407 RADEON_GMC_WR_MSK_DIS
);
409 cmd
[3].i
= ((src_pitch
/64)<<22) | (src_offset
>> 10);
410 cmd
[4].i
= ((dst_pitch
/64)<<22) | (dst_offset
>> 10);
411 cmd
[5].i
= (srcx
<< 16) | srcy
;
412 cmd
[6].i
= (dstx
<< 16) | dsty
; /* dst */
413 cmd
[7].i
= (w
<< 16) | h
;
417 void r200EmitWait( r200ContextPtr rmesa
, GLuint flags
)
419 drm_radeon_cmd_header_t
*cmd
;
421 assert( !(flags
& ~(RADEON_WAIT_2D
|RADEON_WAIT_3D
)) );
423 cmd
= (drm_radeon_cmd_header_t
*)r200AllocCmdBuf( rmesa
, 1 * sizeof(int),
426 cmd
[0].wait
.cmd_type
= RADEON_CMD_WAIT
;
427 cmd
[0].wait
.flags
= flags
;