src/mesa/drivers/dri/r200/r200_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27 */
  28
  29 /*
  30  * Authors:
  31  *   Keith Whitwell <keith@tungstengraphics.com>
  32  */
  33
  34 #include "main/glheader.h"
  35 #include "main/imports.h"
  36 #include "main/macros.h"
  37 #include "main/context.h"
  38 #include "swrast/swrast.h"
  39 #include "main/simple_list.h"
  40
  41 #include "radeon_common.h"
  42 #include "r200_context.h"
  43 #include "r200_state.h"
  44 #include "r200_ioctl.h"
  45 #include "r200_tcl.h"
  46 #include "r200_sanity.h"
  47 #include "radeon_reg.h"
  48
  49 /* The state atoms will be emitted in the order they appear in the atom list,
  50  * so this step is important.
  51  */
  52 void r200SetUpAtomList( r200ContextPtr rmesa )
  53 {
  54    int i, mtu;
  55
  56    mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits;
  57
  58    make_empty_list(&rmesa->radeon.hw.atomlist);
  59    rmesa->radeon.hw.atomlist.name = "atom-list";
  60
  61    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ctx );
  62    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.set );
  63    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.lin );
  64    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msk );
  65    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpt );
  66    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vtx );
  67    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vap );
  68    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vte );
  69    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msc );
  70    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.cst );
  71    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.zbs );
  72    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl );
  73    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msl );
  74    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcg );
  75    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.grd );
  76    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.fog );
  77    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tam );
  78    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tf );
  79    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.atf );
  80    for (i = 0; i < mtu; ++i)
  81        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i] );
  82    for (i = 0; i < mtu; ++i)
  83        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i] );
  84    for (i = 0; i < 6; ++i)
  85        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.pix[i] );
  86    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[0] );
  87    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[1] );
  88    for (i = 0; i < 8; ++i)
  89        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i] );
  90    for (i = 0; i < 3 + mtu; ++i)
  91        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i] );
  92    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.eye );
  93    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.glt );
  94    for (i = 0; i < 2; ++i)
  95       insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.mtl[i] );
  96    for (i = 0; i < 6; ++i)
  97        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i] );
  98    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.spr );
  99    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ptp );
 100    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.prf );
 101    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.pvs );
 102    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[0] );
 103    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[1] );
 104    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[0] );
 105    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[1] );
 106 }
 107
 108 /* Fire a section of the retained (indexed_verts) buffer as a regular
 109  * primtive.
 110  */
 111 void r200EmitVbufPrim( r200ContextPtr rmesa,
 112                        GLuint primitive,
 113                        GLuint vertex_nr )
 114 {
 115    BATCH_LOCALS(&rmesa->radeon);
 116
 117    assert(!(primitive & R200_VF_PRIM_WALK_IND));
 118
 119    radeonEmitState(&rmesa->radeon);
 120
 121    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 122       fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__,
 123               rmesa->store.cmd_used/4, primitive, vertex_nr);
 124
 125    BEGIN_BATCH(3);
 126    OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2, 0);
 127    OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA |
 128              (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT));
 129    END_BATCH();
 130 }
 131
 132 static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type)
 133 {
 134         BATCH_LOCALS(&rmesa->radeon);
 135
 136         if (vertex_count > 0) {
 137                 BEGIN_BATCH(8+2);
 138                 OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_INDX_2, 0);
 139                 OUT_BATCH(R200_VF_PRIM_WALK_IND |
 140                           R200_VF_COLOR_ORDER_RGBA |
 141                           ((vertex_count + 0) << 16) |
 142                           type);
 143
 144                 if (!rmesa->radeon.radeonScreen->kernel_mm) {
 145                         OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
 146                         OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
 147                         OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset,
 148                                         rmesa->radeon.tcl.elt_dma_bo,
 149                                         rmesa->radeon.tcl.elt_dma_offset,
 150                                         RADEON_GEM_DOMAIN_GTT, 0, 0);
 151                         OUT_BATCH((vertex_count + 1)/2);
 152                 } else {
 153                         OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
 154                         OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
 155                         OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
 156                         OUT_BATCH((vertex_count + 1)/2);
 157                         radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 158                                               rmesa->radeon.tcl.elt_dma_bo,
 159                                               RADEON_GEM_DOMAIN_GTT, 0, 0);
 160                 }
 161                 END_BATCH();
 162         }
 163 }
 164
 165 void r200FlushElts(GLcontext *ctx)
 166 {
 167    r200ContextPtr rmesa = R200_CONTEXT(ctx);
 168    int nr, elt_used = rmesa->tcl.elt_used;
 169
 170    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 171      fprintf(stderr, "%s %x %d\n", __FUNCTION__, rmesa->tcl.hw_primitive, elt_used);
 172
 173    assert( rmesa->radeon.dma.flush == r200FlushElts );
 174    rmesa->radeon.dma.flush = NULL;
 175
 176    nr = elt_used / 2;
 177
 178    radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
 179
 180    r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
 181
 182    radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo);
 183    rmesa->radeon.tcl.elt_dma_bo = NULL;
 184
 185    if (R200_DEBUG & DEBUG_SYNC) {
 186       fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
 187       radeonFinish( rmesa->radeon.glCtx );
 188    }
 189 }
 190
 191
 192 GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
 193                                     GLuint primitive,
 194                                     GLuint min_nr )
 195 {
 196    GLushort *retval;
 197
 198    if (R200_DEBUG & DEBUG_IOCTL)
 199       fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
 200
 201    assert((primitive & R200_VF_PRIM_WALK_IND));
 202
 203    radeonEmitState(&rmesa->radeon);
 204
 205    rmesa->radeon.tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
 206                                           0, R200_ELT_BUF_SZ, 4,
 207                                           RADEON_GEM_DOMAIN_GTT, 0);
 208    rmesa->radeon.tcl.elt_dma_offset = 0;
 209    rmesa->tcl.elt_used = min_nr * 2;
 210
 211    radeon_validate_bo(&rmesa->radeon, rmesa->radeon.tcl.elt_dma_bo,
 212                       RADEON_GEM_DOMAIN_GTT, 0);
 213    if (radeon_revalidate_bos(rmesa->radeon.glCtx) == GL_FALSE)
 214       fprintf(stderr,"failure to revalidate BOs - badness\n");
 215
 216    radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1);
 217    retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset;
 218
 219
 220    if (R200_DEBUG & DEBUG_PRIMS)
 221       fprintf(stderr, "%s: header prim %x \n",
 222               __FUNCTION__, primitive);
 223
 224    assert(!rmesa->radeon.dma.flush);
 225    rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
 226    rmesa->radeon.dma.flush = r200FlushElts;
 227
 228    return retval;
 229 }
 230
 231
 232
 233 void r200EmitVertexAOS( r200ContextPtr rmesa,
 234                         GLuint vertex_size,
 235                         struct radeon_bo *bo,
 236                         GLuint offset )
 237 {
 238    BATCH_LOCALS(&rmesa->radeon);
 239
 240    if (R200_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
 241       fprintf(stderr, "%s:  vertex_size 0x%x offset 0x%x \n",
 242               __FUNCTION__, vertex_size, offset);
 243
 244
 245    BEGIN_BATCH(7);
 246    OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, 2);
 247    OUT_BATCH(1);
 248    OUT_BATCH(vertex_size | (vertex_size << 8));
 249    OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
 250    END_BATCH();
 251 }
 252
 253 void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset)
 254 {
 255    BATCH_LOCALS(&rmesa->radeon);
 256    uint32_t voffset;
 257    int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2;
 258    int i;
 259
 260    if (RADEON_DEBUG & DEBUG_VERTS)
 261       fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr,
 262               offset);
 263
 264    BEGIN_BATCH(sz+2+ (nr*2));
 265    OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, sz - 1);
 266    OUT_BATCH(nr);
 267
 268
 269    if (!rmesa->radeon.radeonScreen->kernel_mm) {
 270       for (i = 0; i + 1 < nr; i += 2) {
 271          OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
 272                    (rmesa->radeon.tcl.aos[i].stride << 8) |
 273                    (rmesa->radeon.tcl.aos[i + 1].components << 16) |
 274                    (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 275
 276          voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 277             offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 278          OUT_BATCH_RELOC(voffset,
 279                          rmesa->radeon.tcl.aos[i].bo,
 280                          voffset,
 281                          RADEON_GEM_DOMAIN_GTT,
 282                          0, 0);
 283          voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 284             offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 285          OUT_BATCH_RELOC(voffset,
 286                          rmesa->radeon.tcl.aos[i+1].bo,
 287                          voffset,
 288                          RADEON_GEM_DOMAIN_GTT,
 289                          0, 0);
 290       }
 291
 292       if (nr & 1) {
 293          OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
 294                    (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
 295          voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 296             offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 297          OUT_BATCH_RELOC(voffset,
 298                          rmesa->radeon.tcl.aos[nr - 1].bo,
 299                          voffset,
 300                          RADEON_GEM_DOMAIN_GTT,
 301                          0, 0);
 302       }
 303    } else {
 304       for (i = 0; i + 1 < nr; i += 2) {
 305          OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
 306                    (rmesa->radeon.tcl.aos[i].stride << 8) |
 307                    (rmesa->radeon.tcl.aos[i + 1].components << 16) |
 308                    (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 309
 310          voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 311             offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 312          OUT_BATCH(voffset);
 313          voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 314             offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 315          OUT_BATCH(voffset);
 316       }
 317
 318       if (nr & 1) {
 319          OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
 320                    (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
 321          voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 322             offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 323          OUT_BATCH(voffset);
 324       }
 325       for (i = 0; i + 1 < nr; i += 2) {
 326          voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 327             offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 328          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 329                                rmesa->radeon.tcl.aos[i+0].bo,
 330                                RADEON_GEM_DOMAIN_GTT,
 331                                0, 0);
 332          voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 333             offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 334          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 335                                rmesa->radeon.tcl.aos[i+1].bo,
 336                                RADEON_GEM_DOMAIN_GTT,
 337                                0, 0);
 338       }
 339       if (nr & 1) {
 340          voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 341             offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 342          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 343                                rmesa->radeon.tcl.aos[nr-1].bo,
 344                                RADEON_GEM_DOMAIN_GTT,
 345                                0, 0);
 346       }
 347    }
 348    END_BATCH();
 349 }