src/mesa/drivers/dri/r200/r200_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27 */
  28
  29 /*
  30  * Authors:
  31  *   Keith Whitwell <keith@tungstengraphics.com>
  32  */
  33
  34 #include "main/glheader.h"
  35 #include "main/imports.h"
  36 #include "main/macros.h"
  37 #include "main/context.h"
  38 #include "swrast/swrast.h"
  39 #include "main/simple_list.h"
  40
  41 #include "radeon_common.h"
  42 #include "r200_context.h"
  43 #include "r200_state.h"
  44 #include "r200_ioctl.h"
  45 #include "r200_tcl.h"
  46 #include "r200_sanity.h"
  47 #include "radeon_reg.h"
  48
  49 /* The state atoms will be emitted in the order they appear in the atom list,
  50  * so this step is important.
  51  */
  52 void r200SetUpAtomList( r200ContextPtr rmesa )
  53 {
  54    int i, mtu;
  55
  56    mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits;
  57
  58    make_empty_list(&rmesa->radeon.hw.atomlist);
  59    rmesa->radeon.hw.atomlist.name = "atom-list";
  60
  61    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ctx );
  62    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.set );
  63    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.lin );
  64    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msk );
  65    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpt );
  66    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vtx );
  67    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vap );
  68    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vte );
  69    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msc );
  70    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.cst );
  71    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.zbs );
  72    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl );
  73    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msl );
  74    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcg );
  75    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.grd );
  76    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.fog );
  77    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tam );
  78    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tf );
  79    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.atf );
  80    for (i = 0; i < mtu; ++i)
  81        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i] );
  82    for (i = 0; i < mtu; ++i)
  83        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i] );
  84    for (i = 0; i < 6; ++i)
  85        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.pix[i] );
  86    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[0] );
  87    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[1] );
  88    for (i = 0; i < 8; ++i)
  89        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i] );
  90    for (i = 0; i < 3 + mtu; ++i)
  91        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i] );
  92    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.eye );
  93    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.glt );
  94    for (i = 0; i < 2; ++i)
  95       insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.mtl[i] );
  96    for (i = 0; i < 6; ++i)
  97        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i] );
  98    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.spr );
  99    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ptp );
 100    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.prf );
 101    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.pvs );
 102    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[0] );
 103    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[1] );
 104    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[0] );
 105    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[1] );
 106 }
 107
 108 /* Fire a section of the retained (indexed_verts) buffer as a regular
 109  * primtive.
 110  */
 111 void r200EmitVbufPrim( r200ContextPtr rmesa,
 112                        GLuint primitive,
 113                        GLuint vertex_nr )
 114 {
 115    BATCH_LOCALS(&rmesa->radeon);
 116
 117    assert(!(primitive & R200_VF_PRIM_WALK_IND));
 118
 119    radeonEmitState(&rmesa->radeon);
 120
 121    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 122       fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__,
 123               rmesa->store.cmd_used/4, primitive, vertex_nr);
 124
 125    BEGIN_BATCH(3);
 126    OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2, 0);
 127    OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA |
 128              (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT));
 129    END_BATCH();
 130 }
 131
 132 static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type)
 133 {
 134         BATCH_LOCALS(&rmesa->radeon);
 135
 136         if (vertex_count > 0) {
 137                 BEGIN_BATCH(8+2);
 138                 OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_INDX_2, 0);
 139                 OUT_BATCH(R200_VF_PRIM_WALK_IND |
 140                           ((vertex_count + 0) << 16) |
 141                           type);
 142
 143                 if (!rmesa->radeon.radeonScreen->kernel_mm) {
 144                         OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
 145                         OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
 146                         OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset,
 147                                         rmesa->radeon.tcl.elt_dma_bo,
 148                                         rmesa->radeon.tcl.elt_dma_offset,
 149                                         RADEON_GEM_DOMAIN_GTT, 0, 0);
 150                         OUT_BATCH(vertex_count/2);
 151                 } else {
 152                         OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
 153                         OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
 154                         OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
 155                         OUT_BATCH(vertex_count/2);
 156                         radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 157                                               rmesa->radeon.tcl.elt_dma_bo,
 158                                               RADEON_GEM_DOMAIN_GTT, 0, 0);
 159                 }
 160                 END_BATCH();
 161         }
 162 }
 163
 164 void r200FlushElts(GLcontext *ctx)
 165 {
 166    r200ContextPtr rmesa = R200_CONTEXT(ctx);
 167    int nr, elt_used = rmesa->tcl.elt_used;
 168
 169    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 170      fprintf(stderr, "%s %x %d\n", __FUNCTION__, rmesa->tcl.hw_primitive, elt_used);
 171
 172    assert( rmesa->radeon.dma.flush == r200FlushElts );
 173    rmesa->radeon.dma.flush = NULL;
 174
 175    elt_used = (elt_used + 2) & ~2;
 176
 177    nr = elt_used / 2;
 178
 179    radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
 180
 181    r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
 182
 183    radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo);
 184    rmesa->radeon.tcl.elt_dma_bo = NULL;
 185
 186    if (R200_DEBUG & DEBUG_SYNC) {
 187       fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
 188       radeonFinish( rmesa->radeon.glCtx );
 189    }
 190 }
 191
 192
 193 GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
 194                                     GLuint primitive,
 195                                     GLuint min_nr )
 196 {
 197    GLushort *retval;
 198
 199    if (R200_DEBUG & DEBUG_IOCTL)
 200       fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
 201
 202    assert((primitive & R200_VF_PRIM_WALK_IND));
 203
 204    radeonEmitState(&rmesa->radeon);
 205
 206    rmesa->radeon.tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
 207                                           0, R200_ELT_BUF_SZ, 4,
 208                                           RADEON_GEM_DOMAIN_GTT, 0);
 209    rmesa->radeon.tcl.elt_dma_offset = 0;
 210    rmesa->tcl.elt_used = min_nr * 2;
 211
 212    radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1);
 213    retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset;
 214
 215
 216    if (R200_DEBUG & DEBUG_PRIMS)
 217       fprintf(stderr, "%s: header prim %x \n",
 218               __FUNCTION__, primitive);
 219
 220    assert(!rmesa->radeon.dma.flush);
 221    rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
 222    rmesa->radeon.dma.flush = r200FlushElts;
 223
 224    return retval;
 225 }
 226
 227
 228
 229 void r200EmitVertexAOS( r200ContextPtr rmesa,
 230                         GLuint vertex_size,
 231                         struct radeon_bo *bo,
 232                         GLuint offset )
 233 {
 234    BATCH_LOCALS(&rmesa->radeon);
 235
 236    if (R200_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
 237       fprintf(stderr, "%s:  vertex_size 0x%x offset 0x%x \n",
 238               __FUNCTION__, vertex_size, offset);
 239
 240
 241    BEGIN_BATCH(5);
 242    OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, 2);
 243    OUT_BATCH(1);
 244    OUT_BATCH(vertex_size | (vertex_size << 8));
 245    OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
 246    END_BATCH();
 247 }
 248
 249 void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset)
 250 {
 251    BATCH_LOCALS(&rmesa->radeon);
 252    uint32_t voffset;
 253    int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2;
 254    int i;
 255
 256    if (RADEON_DEBUG & DEBUG_VERTS)
 257       fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr,
 258               offset);
 259
 260    BEGIN_BATCH(sz+2+ (nr*2));
 261    OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, sz - 1);
 262    OUT_BATCH(nr);
 263
 264
 265    if (!rmesa->radeon.radeonScreen->kernel_mm) {
 266       for (i = 0; i + 1 < nr; i += 2) {
 267          OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
 268                    (rmesa->radeon.tcl.aos[i].stride << 8) |
 269                    (rmesa->radeon.tcl.aos[i + 1].components << 16) |
 270                    (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 271
 272          voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 273             offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 274          OUT_BATCH_RELOC(voffset,
 275                          rmesa->radeon.tcl.aos[i].bo,
 276                          voffset,
 277                          RADEON_GEM_DOMAIN_GTT,
 278                          0, 0);
 279          voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 280             offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 281          OUT_BATCH_RELOC(voffset,
 282                          rmesa->radeon.tcl.aos[i+1].bo,
 283                          voffset,
 284                          RADEON_GEM_DOMAIN_GTT,
 285                          0, 0);
 286       }
 287
 288       if (nr & 1) {
 289          OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
 290                    (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
 291          voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 292             offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 293          OUT_BATCH_RELOC(voffset,
 294                          rmesa->radeon.tcl.aos[nr - 1].bo,
 295                          voffset,
 296                          RADEON_GEM_DOMAIN_GTT,
 297                          0, 0);
 298       }
 299    } else {
 300       for (i = 0; i + 1 < nr; i += 2) {
 301          OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
 302                    (rmesa->radeon.tcl.aos[i].stride << 8) |
 303                    (rmesa->radeon.tcl.aos[i + 1].components << 16) |
 304                    (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 305
 306          voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 307             offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 308          OUT_BATCH(voffset);
 309          voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 310             offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 311          OUT_BATCH(voffset);
 312       }
 313
 314       if (nr & 1) {
 315          OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
 316                    (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
 317          voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 318             offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 319          OUT_BATCH(voffset);
 320       }
 321       for (i = 0; i + 1 < nr; i += 2) {
 322          voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 323             offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 324          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 325                                rmesa->radeon.tcl.aos[i+0].bo,
 326                                RADEON_GEM_DOMAIN_GTT,
 327                                0, 0);
 328          voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 329             offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 330          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 331                                rmesa->radeon.tcl.aos[i+1].bo,
 332                                RADEON_GEM_DOMAIN_GTT,
 333                                0, 0);
 334       }
 335       if (nr & 1) {
 336          voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 337             offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 338          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 339                                rmesa->radeon.tcl.aos[nr-1].bo,
 340                                RADEON_GEM_DOMAIN_GTT,
 341                                0, 0);
 342       }
 343    }
 344    END_BATCH();
 345 }