src/mesa/drivers/dri/r200/r200_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27 */
  28
  29 /*
  30  * Authors:
  31  *   Keith Whitwell <keith@tungstengraphics.com>
  32  */
  33
  34 #include "main/glheader.h"
  35 #include "main/imports.h"
  36 #include "main/macros.h"
  37 #include "main/context.h"
  38 #include "swrast/swrast.h"
  39 #include "main/simple_list.h"
  40
  41 #include "radeon_common.h"
  42 #include "r200_context.h"
  43 #include "r200_state.h"
  44 #include "r200_ioctl.h"
  45 #include "r200_tcl.h"
  46 #include "r200_sanity.h"
  47 #include "radeon_reg.h"
  48
  49 /* The state atoms will be emitted in the order they appear in the atom list,
  50  * so this step is important.
  51  */
  52 void r200SetUpAtomList( r200ContextPtr rmesa )
  53 {
  54    int i, mtu;
  55
  56    mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits;
  57
  58    make_empty_list(&rmesa->radeon.hw.atomlist);
  59    rmesa->radeon.hw.atomlist.name = "atom-list";
  60
  61    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ctx );
  62    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.set );
  63    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.lin );
  64    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msk );
  65    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpt );
  66    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vtx );
  67    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vap );
  68    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vte );
  69    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msc );
  70    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.cst );
  71    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.zbs );
  72    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl );
  73    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msl );
  74    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcg );
  75    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.grd );
  76    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.fog );
  77    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tam );
  78    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tf );
  79    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.atf );
  80    for (i = 0; i < mtu; ++i)
  81        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i] );
  82    for (i = 0; i < mtu; ++i)
  83        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i] );
  84    for (i = 0; i < 6; ++i)
  85        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.pix[i] );
  86    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[0] );
  87    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[1] );
  88    for (i = 0; i < 8; ++i)
  89        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i] );
  90    for (i = 0; i < 3 + mtu; ++i)
  91        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i] );
  92    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.eye );
  93    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.glt );
  94    for (i = 0; i < 2; ++i)
  95       insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.mtl[i] );
  96    for (i = 0; i < 6; ++i)
  97        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i] );
  98    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.spr );
  99    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ptp );
 100    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.prf );
 101    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.pvs );
 102    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[0] );
 103    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[1] );
 104    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[0] );
 105    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[1] );
 106 }
 107
 108 void r200EmitScissor(r200ContextPtr rmesa)
 109 {
 110     unsigned x1, y1, x2, y2;
 111     struct radeon_renderbuffer *rrb;
 112     BATCH_LOCALS(&rmesa->radeon);
 113     if (!rmesa->radeon.radeonScreen->kernel_mm) {
 114        return;
 115     }
 116     rrb = radeon_get_colorbuffer(&rmesa->radeon);
 117     if (!rrb || !rrb->bo)
 118         return;
 119
 120     if (rmesa->radeon.state.scissor.enabled) {
 121         x1 = rmesa->radeon.state.scissor.rect.x1;
 122         y1 = rmesa->radeon.state.scissor.rect.y1;
 123         x2 = rmesa->radeon.state.scissor.rect.x2 - 1;
 124         y2 = rmesa->radeon.state.scissor.rect.y2 - 1;
 125     } else {
 126         x1 = 0;
 127         y1 = 0;
 128         x2 = rrb->base.Width - 1;
 129         y2 = rrb->base.Height - 1;
 130     }
 131     BEGIN_BATCH(8);
 132     OUT_BATCH(CP_PACKET0(R200_RE_CNTL, 0));
 133     OUT_BATCH(R200_SCISSOR_ENABLE | rmesa->hw.set.cmd[SET_RE_CNTL]);
 134     OUT_BATCH(CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0));
 135     OUT_BATCH(0);
 136     OUT_BATCH(CP_PACKET0(R200_RE_TOP_LEFT, 0));
 137     OUT_BATCH((y1 << 16) | x1);
 138     OUT_BATCH(CP_PACKET0(R200_RE_WIDTH_HEIGHT, 0));
 139     OUT_BATCH((y2 << 16) | x2);
 140     END_BATCH();
 141 }
 142
 143 /* Fire a section of the retained (indexed_verts) buffer as a regular
 144  * primtive.
 145  */
 146 void r200EmitVbufPrim( r200ContextPtr rmesa,
 147                        GLuint primitive,
 148                        GLuint vertex_nr )
 149 {
 150    BATCH_LOCALS(&rmesa->radeon);
 151
 152    assert(!(primitive & R200_VF_PRIM_WALK_IND));
 153
 154    radeonEmitState(&rmesa->radeon);
 155
 156    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 157       fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__,
 158               rmesa->store.cmd_used/4, primitive, vertex_nr);
 159    r200EmitScissor(rmesa);
 160
 161    BEGIN_BATCH(3);
 162    OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2, 0);
 163    OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA |
 164              (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT));
 165    END_BATCH();
 166 }
 167
 168 static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type)
 169 {
 170         BATCH_LOCALS(&rmesa->radeon);
 171
 172         if (vertex_count > 0) {
 173         r200EmitScissor(rmesa);
 174                 BEGIN_BATCH(8+2);
 175                 OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_INDX_2, 0);
 176                 OUT_BATCH(R200_VF_PRIM_WALK_IND |
 177                           R200_VF_COLOR_ORDER_RGBA |
 178                           ((vertex_count + 0) << 16) |
 179                           type);
 180
 181                 if (!rmesa->radeon.radeonScreen->kernel_mm) {
 182                         OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
 183                         OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
 184                         OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset,
 185                                         rmesa->radeon.tcl.elt_dma_bo,
 186                                         rmesa->radeon.tcl.elt_dma_offset,
 187                                         RADEON_GEM_DOMAIN_GTT, 0, 0);
 188                         OUT_BATCH((vertex_count + 1)/2);
 189                 } else {
 190                         OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
 191                         OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
 192                         OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
 193                         OUT_BATCH((vertex_count + 1)/2);
 194                         radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 195                                               rmesa->radeon.tcl.elt_dma_bo,
 196                                               RADEON_GEM_DOMAIN_GTT, 0, 0);
 197                 }
 198                 END_BATCH();
 199         }
 200 }
 201
 202 void r200FlushElts(GLcontext *ctx)
 203 {
 204    r200ContextPtr rmesa = R200_CONTEXT(ctx);
 205    int nr, elt_used = rmesa->tcl.elt_used;
 206
 207    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 208      fprintf(stderr, "%s %x %d\n", __FUNCTION__, rmesa->tcl.hw_primitive, elt_used);
 209
 210    assert( rmesa->radeon.dma.flush == r200FlushElts );
 211    rmesa->radeon.dma.flush = NULL;
 212
 213    nr = elt_used / 2;
 214
 215    radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
 216
 217    r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
 218
 219    radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo);
 220    rmesa->radeon.tcl.elt_dma_bo = NULL;
 221
 222    if (R200_DEBUG & DEBUG_SYNC) {
 223       fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
 224       radeonFinish( rmesa->radeon.glCtx );
 225    }
 226 }
 227
 228
 229 GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
 230                                     GLuint primitive,
 231                                     GLuint min_nr )
 232 {
 233    GLushort *retval;
 234    int ret;
 235
 236    if (R200_DEBUG & DEBUG_IOCTL)
 237       fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
 238
 239    assert((primitive & R200_VF_PRIM_WALK_IND));
 240
 241    radeonEmitState(&rmesa->radeon);
 242
 243 #ifdef RADEON_DEBUG_BO
 244    rmesa->radeon.tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
 245                                           0, R200_ELT_BUF_SZ, 4,
 246                                                  RADEON_GEM_DOMAIN_GTT, 0, "ELT");
 247 #else
 248    rmesa->radeon.tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
 249                                           0, R200_ELT_BUF_SZ, 4,
 250                                           RADEON_GEM_DOMAIN_GTT, 0);
 251 #endif
 252    rmesa->radeon.tcl.elt_dma_offset = 0;
 253    rmesa->tcl.elt_used = min_nr * 2;
 254
 255    ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, rmesa->radeon.tcl.elt_dma_bo,
 256                                  RADEON_GEM_DOMAIN_GTT, 0);
 257    if (ret) {
 258       fprintf(stderr,"failure to revalidate BOs - badness\n");
 259    }
 260
 261    radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1);
 262    retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset;
 263
 264
 265    if (R200_DEBUG & DEBUG_PRIMS)
 266       fprintf(stderr, "%s: header prim %x \n",
 267               __FUNCTION__, primitive);
 268
 269    assert(!rmesa->radeon.dma.flush);
 270    rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
 271    rmesa->radeon.dma.flush = r200FlushElts;
 272
 273    return retval;
 274 }
 275
 276
 277
 278 void r200EmitVertexAOS( r200ContextPtr rmesa,
 279                         GLuint vertex_size,
 280                         struct radeon_bo *bo,
 281                         GLuint offset )
 282 {
 283    BATCH_LOCALS(&rmesa->radeon);
 284
 285    if (R200_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
 286       fprintf(stderr, "%s:  vertex_size 0x%x offset 0x%x \n",
 287               __FUNCTION__, vertex_size, offset);
 288
 289
 290    BEGIN_BATCH(7);
 291    OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, 2);
 292    OUT_BATCH(1);
 293    OUT_BATCH(vertex_size | (vertex_size << 8));
 294    OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
 295    END_BATCH();
 296 }
 297
 298 void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset)
 299 {
 300    BATCH_LOCALS(&rmesa->radeon);
 301    uint32_t voffset;
 302    int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2;
 303    int i;
 304
 305    if (RADEON_DEBUG & DEBUG_VERTS)
 306       fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr,
 307               offset);
 308
 309    BEGIN_BATCH(sz+2+ (nr*2));
 310    OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, sz - 1);
 311    OUT_BATCH(nr);
 312
 313
 314    if (!rmesa->radeon.radeonScreen->kernel_mm) {
 315       for (i = 0; i + 1 < nr; i += 2) {
 316          OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
 317                    (rmesa->radeon.tcl.aos[i].stride << 8) |
 318                    (rmesa->radeon.tcl.aos[i + 1].components << 16) |
 319                    (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 320
 321          voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 322             offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 323          OUT_BATCH_RELOC(voffset,
 324                          rmesa->radeon.tcl.aos[i].bo,
 325                          voffset,
 326                          RADEON_GEM_DOMAIN_GTT,
 327                          0, 0);
 328          voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 329             offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 330          OUT_BATCH_RELOC(voffset,
 331                          rmesa->radeon.tcl.aos[i+1].bo,
 332                          voffset,
 333                          RADEON_GEM_DOMAIN_GTT,
 334                          0, 0);
 335       }
 336
 337       if (nr & 1) {
 338          OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
 339                    (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
 340          voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 341             offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 342          OUT_BATCH_RELOC(voffset,
 343                          rmesa->radeon.tcl.aos[nr - 1].bo,
 344                          voffset,
 345                          RADEON_GEM_DOMAIN_GTT,
 346                          0, 0);
 347       }
 348    } else {
 349       for (i = 0; i + 1 < nr; i += 2) {
 350          OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
 351                    (rmesa->radeon.tcl.aos[i].stride << 8) |
 352                    (rmesa->radeon.tcl.aos[i + 1].components << 16) |
 353                    (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 354
 355          voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 356             offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 357          OUT_BATCH(voffset);
 358          voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 359             offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 360          OUT_BATCH(voffset);
 361       }
 362
 363       if (nr & 1) {
 364          OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
 365                    (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
 366          voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 367             offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 368          OUT_BATCH(voffset);
 369       }
 370       for (i = 0; i + 1 < nr; i += 2) {
 371          voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 372             offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 373          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 374                                rmesa->radeon.tcl.aos[i+0].bo,
 375                                RADEON_GEM_DOMAIN_GTT,
 376                                0, 0);
 377          voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 378             offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 379          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 380                                rmesa->radeon.tcl.aos[i+1].bo,
 381                                RADEON_GEM_DOMAIN_GTT,
 382                                0, 0);
 383       }
 384       if (nr & 1) {
 385          voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 386             offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 387          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 388                                rmesa->radeon.tcl.aos[nr-1].bo,
 389                                RADEON_GEM_DOMAIN_GTT,
 390                                0, 0);
 391       }
 392    }
 393    END_BATCH();
 394 }