src/mesa/drivers/dri/r200/r200_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27 */
  28
  29 /*
  30  * Authors:
  31  *   Keith Whitwell <keith@tungstengraphics.com>
  32  */
  33
  34 #include "main/glheader.h"
  35 #include "main/imports.h"
  36 #include "main/macros.h"
  37 #include "main/context.h"
  38 #include "swrast/swrast.h"
  39 #include "main/simple_list.h"
  40
  41 #include "radeon_common.h"
  42 #include "r200_context.h"
  43 #include "r200_state.h"
  44 #include "r200_ioctl.h"
  45 #include "r200_tcl.h"
  46 #include "r200_sanity.h"
  47 #include "radeon_reg.h"
  48
  49 /* The state atoms will be emitted in the order they appear in the atom list,
  50  * so this step is important.
  51  */
  52 void r200SetUpAtomList( r200ContextPtr rmesa )
  53 {
  54    int i, mtu;
  55
  56    mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits;
  57
  58    make_empty_list(&rmesa->radeon.hw.atomlist);
  59    rmesa->radeon.hw.atomlist.name = "atom-list";
  60
  61    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ctx );
  62    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.set );
  63    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.lin );
  64    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msk );
  65    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpt );
  66    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vtx );
  67    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vap );
  68    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vte );
  69    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msc );
  70    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.cst );
  71    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.zbs );
  72    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl );
  73    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msl );
  74    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcg );
  75    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.grd );
  76    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.fog );
  77    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tam );
  78    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tf );
  79    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.atf );
  80    for (i = 0; i < mtu; ++i)
  81        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i] );
  82    for (i = 0; i < mtu; ++i)
  83        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i] );
  84    for (i = 0; i < 6; ++i)
  85        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.pix[i] );
  86    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[0] );
  87    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[1] );
  88    for (i = 0; i < 8; ++i)
  89        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i] );
  90    for (i = 0; i < 3 + mtu; ++i)
  91        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i] );
  92    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.eye );
  93    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.glt );
  94    for (i = 0; i < 2; ++i)
  95       insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.mtl[i] );
  96    for (i = 0; i < 6; ++i)
  97        insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i] );
  98    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.spr );
  99    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ptp );
 100    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.prf );
 101    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.pvs );
 102    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[0] );
 103    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[1] );
 104    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[0] );
 105    insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[1] );
 106 }
 107
 108 void r200EmitScissor(r200ContextPtr rmesa)
 109 {
 110     BATCH_LOCALS(&rmesa->radeon);
 111     if (!rmesa->radeon.radeonScreen->kernel_mm) {
 112        return;
 113     }
 114     if (rmesa->radeon.state.scissor.enabled) {
 115         BEGIN_BATCH(8);
 116         OUT_BATCH(CP_PACKET0(R200_RE_CNTL, 0));
 117         OUT_BATCH(R200_SCISSOR_ENABLE | rmesa->hw.set.cmd[SET_RE_CNTL]);
 118         OUT_BATCH(CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0));
 119         OUT_BATCH(R200_SCISSOR_ENABLE_0);
 120         OUT_BATCH(CP_PACKET0(R200_RE_SCISSOR_TL_0, 0));
 121         OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) |
 122                   rmesa->radeon.state.scissor.rect.x1);
 123         OUT_BATCH(CP_PACKET0(R200_RE_SCISSOR_BR_0, 0));
 124         OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2 - 1) << 16) |
 125                   (rmesa->radeon.state.scissor.rect.x2 - 1));
 126         END_BATCH();
 127     } else {
 128         BEGIN_BATCH(4);
 129         OUT_BATCH(CP_PACKET0(R200_RE_CNTL, 0));
 130         OUT_BATCH(rmesa->hw.set.cmd[SET_RE_CNTL] & ~R200_SCISSOR_ENABLE);
 131         OUT_BATCH(CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0));
 132         OUT_BATCH(0);
 133         END_BATCH();
 134     }
 135 }
 136
 137 /* Fire a section of the retained (indexed_verts) buffer as a regular
 138  * primtive.
 139  */
 140 void r200EmitVbufPrim( r200ContextPtr rmesa,
 141                        GLuint primitive,
 142                        GLuint vertex_nr )
 143 {
 144    BATCH_LOCALS(&rmesa->radeon);
 145
 146    assert(!(primitive & R200_VF_PRIM_WALK_IND));
 147
 148    radeonEmitState(&rmesa->radeon);
 149
 150    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 151       fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__,
 152               rmesa->store.cmd_used/4, primitive, vertex_nr);
 153    r200EmitScissor(rmesa);
 154
 155    BEGIN_BATCH(3);
 156    OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2, 0);
 157    OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA |
 158              (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT));
 159    END_BATCH();
 160 }
 161
 162 static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type)
 163 {
 164         BATCH_LOCALS(&rmesa->radeon);
 165
 166         if (vertex_count > 0) {
 167         r200EmitScissor(rmesa);
 168                 BEGIN_BATCH(8+2);
 169                 OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_INDX_2, 0);
 170                 OUT_BATCH(R200_VF_PRIM_WALK_IND |
 171                           R200_VF_COLOR_ORDER_RGBA |
 172                           ((vertex_count + 0) << 16) |
 173                           type);
 174
 175                 if (!rmesa->radeon.radeonScreen->kernel_mm) {
 176                         OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
 177                         OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
 178                         OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset,
 179                                         rmesa->radeon.tcl.elt_dma_bo,
 180                                         rmesa->radeon.tcl.elt_dma_offset,
 181                                         RADEON_GEM_DOMAIN_GTT, 0, 0);
 182                         OUT_BATCH((vertex_count + 1)/2);
 183                 } else {
 184                         OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
 185                         OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
 186                         OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
 187                         OUT_BATCH((vertex_count + 1)/2);
 188                         radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 189                                               rmesa->radeon.tcl.elt_dma_bo,
 190                                               RADEON_GEM_DOMAIN_GTT, 0, 0);
 191                 }
 192                 END_BATCH();
 193         }
 194 }
 195
 196 void r200FlushElts(GLcontext *ctx)
 197 {
 198    r200ContextPtr rmesa = R200_CONTEXT(ctx);
 199    int nr, elt_used = rmesa->tcl.elt_used;
 200
 201    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
 202      fprintf(stderr, "%s %x %d\n", __FUNCTION__, rmesa->tcl.hw_primitive, elt_used);
 203
 204    assert( rmesa->radeon.dma.flush == r200FlushElts );
 205    rmesa->radeon.dma.flush = NULL;
 206
 207    nr = elt_used / 2;
 208
 209    radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
 210
 211    r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
 212
 213    radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo);
 214    rmesa->radeon.tcl.elt_dma_bo = NULL;
 215
 216    if (R200_ELT_BUF_SZ > elt_used)
 217      radeonReturnDmaRegion(rmesa, R200_ELT_BUF_SZ - elt_used);
 218
 219    if (R200_DEBUG & DEBUG_SYNC) {
 220       fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
 221       radeonFinish( rmesa->radeon.glCtx );
 222    }
 223 }
 224
 225
 226 GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
 227                                     GLuint primitive,
 228                                     GLuint min_nr )
 229 {
 230    GLushort *retval;
 231
 232    if (R200_DEBUG & DEBUG_IOCTL)
 233       fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
 234
 235    assert((primitive & R200_VF_PRIM_WALK_IND));
 236
 237    radeonEmitState(&rmesa->radeon);
 238
 239    radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo,
 240                         &rmesa->radeon.tcl.elt_dma_offset, R200_ELT_BUF_SZ, 4);
 241    rmesa->tcl.elt_used = min_nr * 2;
 242
 243    radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1);
 244    retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset;
 245
 246    if (R200_DEBUG & DEBUG_PRIMS)
 247       fprintf(stderr, "%s: header prim %x \n",
 248               __FUNCTION__, primitive);
 249
 250    assert(!rmesa->radeon.dma.flush);
 251    rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
 252    rmesa->radeon.dma.flush = r200FlushElts;
 253
 254    return retval;
 255 }
 256
 257
 258
 259 void r200EmitVertexAOS( r200ContextPtr rmesa,
 260                         GLuint vertex_size,
 261                         struct radeon_bo *bo,
 262                         GLuint offset )
 263 {
 264    BATCH_LOCALS(&rmesa->radeon);
 265
 266    if (R200_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
 267       fprintf(stderr, "%s:  vertex_size 0x%x offset 0x%x \n",
 268               __FUNCTION__, vertex_size, offset);
 269
 270
 271    BEGIN_BATCH(7);
 272    OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, 2);
 273    OUT_BATCH(1);
 274    OUT_BATCH(vertex_size | (vertex_size << 8));
 275    OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
 276    END_BATCH();
 277 }
 278
 279 void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset)
 280 {
 281    BATCH_LOCALS(&rmesa->radeon);
 282    uint32_t voffset;
 283    int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2;
 284    int i;
 285
 286    if (RADEON_DEBUG & DEBUG_VERTS)
 287       fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr,
 288               offset);
 289
 290    BEGIN_BATCH(sz+2+ (nr*2));
 291    OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, sz - 1);
 292    OUT_BATCH(nr);
 293
 294
 295    if (!rmesa->radeon.radeonScreen->kernel_mm) {
 296       for (i = 0; i + 1 < nr; i += 2) {
 297          OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
 298                    (rmesa->radeon.tcl.aos[i].stride << 8) |
 299                    (rmesa->radeon.tcl.aos[i + 1].components << 16) |
 300                    (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 301
 302          voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 303             offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 304          OUT_BATCH_RELOC(voffset,
 305                          rmesa->radeon.tcl.aos[i].bo,
 306                          voffset,
 307                          RADEON_GEM_DOMAIN_GTT,
 308                          0, 0);
 309          voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 310             offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 311          OUT_BATCH_RELOC(voffset,
 312                          rmesa->radeon.tcl.aos[i+1].bo,
 313                          voffset,
 314                          RADEON_GEM_DOMAIN_GTT,
 315                          0, 0);
 316       }
 317
 318       if (nr & 1) {
 319          OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
 320                    (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
 321          voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 322             offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 323          OUT_BATCH_RELOC(voffset,
 324                          rmesa->radeon.tcl.aos[nr - 1].bo,
 325                          voffset,
 326                          RADEON_GEM_DOMAIN_GTT,
 327                          0, 0);
 328       }
 329    } else {
 330       for (i = 0; i + 1 < nr; i += 2) {
 331          OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
 332                    (rmesa->radeon.tcl.aos[i].stride << 8) |
 333                    (rmesa->radeon.tcl.aos[i + 1].components << 16) |
 334                    (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 335
 336          voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 337             offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 338          OUT_BATCH(voffset);
 339          voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 340             offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 341          OUT_BATCH(voffset);
 342       }
 343
 344       if (nr & 1) {
 345          OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
 346                    (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
 347          voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 348             offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 349          OUT_BATCH(voffset);
 350       }
 351       for (i = 0; i + 1 < nr; i += 2) {
 352          voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 353             offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 354          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 355                                rmesa->radeon.tcl.aos[i+0].bo,
 356                                RADEON_GEM_DOMAIN_GTT,
 357                                0, 0);
 358          voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
 359             offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 360          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 361                                rmesa->radeon.tcl.aos[i+1].bo,
 362                                RADEON_GEM_DOMAIN_GTT,
 363                                0, 0);
 364       }
 365       if (nr & 1) {
 366          voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
 367             offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 368          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 369                                rmesa->radeon.tcl.aos[nr-1].bo,
 370                                RADEON_GEM_DOMAIN_GTT,
 371                                0, 0);
 372       }
 373    }
 374    END_BATCH();
 375 }