r200: Drop the non-kernel-memory-manager and DRI1 code.
[mesa.git] / src / mesa / drivers / dri / r200 / r200_context.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /*
31 * Authors:
32 * Keith Whitwell <keith@tungstengraphics.com>
33 */
34
35 #include <stdbool.h>
36 #include "main/glheader.h"
37 #include "main/api_arrayelt.h"
38 #include "main/context.h"
39 #include "main/simple_list.h"
40 #include "main/imports.h"
41 #include "main/extensions.h"
42 #include "main/mfeatures.h"
43
44 #include "swrast/swrast.h"
45 #include "swrast_setup/swrast_setup.h"
46 #include "vbo/vbo.h"
47
48 #include "tnl/tnl.h"
49 #include "tnl/t_pipeline.h"
50
51 #include "drivers/common/driverfuncs.h"
52
53 #include "r200_context.h"
54 #include "r200_ioctl.h"
55 #include "r200_state.h"
56 #include "r200_tex.h"
57 #include "r200_swtcl.h"
58 #include "r200_tcl.h"
59 #include "r200_vertprog.h"
60 #include "radeon_queryobj.h"
61 #include "r200_blit.h"
62
63 #include "radeon_span.h"
64
65 #include "utils.h"
66 #include "xmlpool.h" /* for symbolic values of enum-type options */
67
68 /* Return various strings for glGetString().
69 */
70 static const GLubyte *r200GetString( struct gl_context *ctx, GLenum name )
71 {
72 r200ContextPtr rmesa = R200_CONTEXT(ctx);
73 static char buffer[128];
74 unsigned offset;
75 GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type == RADEON_CARD_PCI)? 0 :
76 rmesa->radeon.radeonScreen->AGPMode;
77
78 switch ( name ) {
79 case GL_VENDOR:
80 return (GLubyte *)"Tungsten Graphics, Inc.";
81
82 case GL_RENDERER:
83 offset = driGetRendererString( buffer, "R200", agp_mode );
84
85 sprintf( & buffer[ offset ], " %sTCL",
86 !(rmesa->radeon.TclFallback & R200_TCL_FALLBACK_TCL_DISABLE)
87 ? "" : "NO-" );
88
89 return (GLubyte *)buffer;
90
91 default:
92 return NULL;
93 }
94 }
95
96
97 extern const struct tnl_pipeline_stage _r200_render_stage;
98 extern const struct tnl_pipeline_stage _r200_tcl_stage;
99
100 static const struct tnl_pipeline_stage *r200_pipeline[] = {
101
102 /* Try and go straight to t&l
103 */
104 &_r200_tcl_stage,
105
106 /* Catch any t&l fallbacks
107 */
108 &_tnl_vertex_transform_stage,
109 &_tnl_normal_transform_stage,
110 &_tnl_lighting_stage,
111 &_tnl_fog_coordinate_stage,
112 &_tnl_texgen_stage,
113 &_tnl_texture_transform_stage,
114 &_tnl_point_attenuation_stage,
115 &_tnl_vertex_program_stage,
116 /* Try again to go to tcl?
117 * - no good for asymmetric-twoside (do with multipass)
118 * - no good for asymmetric-unfilled (do with multipass)
119 * - good for material
120 * - good for texgen
121 * - need to manipulate a bit of state
122 *
123 * - worth it/not worth it?
124 */
125
126 /* Else do them here.
127 */
128 /* &_r200_render_stage, */ /* FIXME: bugs with ut2003 */
129 &_tnl_render_stage, /* FALLBACK: */
130 NULL,
131 };
132
133
134
135 /* Initialize the driver's misc functions.
136 */
137 static void r200InitDriverFuncs( struct dd_function_table *functions )
138 {
139 functions->GetBufferSize = NULL; /* OBSOLETE */
140 functions->GetString = r200GetString;
141 }
142
143
144 static void r200_get_lock(radeonContextPtr radeon)
145 {
146 r200ContextPtr rmesa = (r200ContextPtr)radeon;
147 drm_radeon_sarea_t *sarea = radeon->sarea;
148
149 R200_STATECHANGE( rmesa, ctx );
150 if (rmesa->radeon.sarea->tiling_enabled) {
151 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
152 }
153 else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~R200_COLOR_TILE_ENABLE;
154
155 if ( sarea->ctx_owner != rmesa->radeon.dri.hwContext ) {
156 sarea->ctx_owner = rmesa->radeon.dri.hwContext;
157 }
158
159 }
160
161 static void r200_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
162 {
163 }
164
165 static void r200_emit_query_finish(radeonContextPtr radeon)
166 {
167 BATCH_LOCALS(radeon);
168 struct radeon_query_object *query = radeon->query.current;
169
170 BEGIN_BATCH_NO_AUTOSTATE(4);
171 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
172 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
173 END_BATCH();
174 query->curr_offset += sizeof(uint32_t);
175 assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
176 query->emitted_begin = GL_FALSE;
177 }
178
179 static void r200_init_vtbl(radeonContextPtr radeon)
180 {
181 radeon->vtbl.get_lock = r200_get_lock;
182 radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset;
183 radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header;
184 radeon->vtbl.swtcl_flush = r200_swtcl_flush;
185 radeon->vtbl.fallback = r200Fallback;
186 radeon->vtbl.update_scissor = r200_vtbl_update_scissor;
187 radeon->vtbl.emit_query_finish = r200_emit_query_finish;
188 radeon->vtbl.check_blit = r200_check_blit;
189 radeon->vtbl.blit = r200_blit;
190 radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
191 }
192
193
194 /* Create the device specific rendering context.
195 */
196 GLboolean r200CreateContext( gl_api api,
197 const struct gl_config *glVisual,
198 __DRIcontext *driContextPriv,
199 void *sharedContextPrivate)
200 {
201 __DRIscreen *sPriv = driContextPriv->driScreenPriv;
202 radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
203 struct dd_function_table functions;
204 r200ContextPtr rmesa;
205 struct gl_context *ctx;
206 int i;
207 int tcl_mode;
208
209 assert(glVisual);
210 assert(driContextPriv);
211 assert(screen);
212
213 /* Allocate the R200 context */
214 rmesa = (r200ContextPtr) CALLOC( sizeof(*rmesa) );
215 if ( !rmesa )
216 return GL_FALSE;
217
218 rmesa->radeon.radeonScreen = screen;
219 r200_init_vtbl(&rmesa->radeon);
220 /* init exp fog table data */
221 r200InitStaticFogData();
222
223 /* Parse configuration files.
224 * Do this here so that initialMaxAnisotropy is set before we create
225 * the default textures.
226 */
227 driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
228 screen->driScreen->myNum, "r200");
229 rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
230 "def_max_anisotropy");
231
232 if ( sPriv->drm_version.major == 1
233 && driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
234 if ( sPriv->drm_version.minor < 13 )
235 fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
236 "disabling.\n", sPriv->drm_version.minor );
237 else
238 rmesa->using_hyperz = GL_TRUE;
239 }
240
241 if ( sPriv->drm_version.minor >= 15 )
242 rmesa->texmicrotile = GL_TRUE;
243
244 /* Init default driver functions then plug in our R200-specific functions
245 * (the texture functions are especially important)
246 */
247 _mesa_init_driver_functions(&functions);
248 r200InitDriverFuncs(&functions);
249 r200InitIoctlFuncs(&functions);
250 r200InitStateFuncs(&rmesa->radeon, &functions);
251 r200InitTextureFuncs(&rmesa->radeon, &functions);
252 r200InitShaderFuncs(&functions);
253 radeonInitQueryObjFunctions(&functions);
254
255 if (!radeonInitContext(&rmesa->radeon, &functions,
256 glVisual, driContextPriv,
257 sharedContextPrivate)) {
258 FREE(rmesa);
259 return GL_FALSE;
260 }
261
262 rmesa->radeon.swtcl.RenderIndex = ~0;
263 rmesa->radeon.hw.all_dirty = 1;
264
265 /* Set the maximum texture size small enough that we can guarentee that
266 * all texture units can bind a maximal texture and have all of them in
267 * texturable memory at once. Depending on the allow_large_textures driconf
268 * setting allow larger textures.
269 */
270
271 ctx = rmesa->radeon.glCtx;
272 ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
273 "texture_units");
274 ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
275 ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
276
277 ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
278
279 i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
280
281 /* FIXME: When no memory manager is available we should set this
282 * to some reasonable value based on texture memory pool size */
283 ctx->Const.MaxTextureLevels = 12;
284 ctx->Const.Max3DTextureLevels = 9;
285 ctx->Const.MaxCubeTextureLevels = 12;
286 ctx->Const.MaxTextureRectSize = 2048;
287 ctx->Const.MaxRenderbufferSize = 2048;
288
289 ctx->Const.MaxTextureMaxAnisotropy = 16.0;
290
291 /* No wide AA points.
292 */
293 ctx->Const.MinPointSize = 1.0;
294 ctx->Const.MinPointSizeAA = 1.0;
295 ctx->Const.MaxPointSizeAA = 1.0;
296 ctx->Const.PointSizeGranularity = 0.0625;
297 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites)
298 ctx->Const.MaxPointSize = 2047.0;
299 else
300 ctx->Const.MaxPointSize = 1.0;
301
302 /* mesa initialization problem - _mesa_init_point was already called */
303 ctx->Point.MaxSize = ctx->Const.MaxPointSize;
304
305 ctx->Const.MinLineWidth = 1.0;
306 ctx->Const.MinLineWidthAA = 1.0;
307 ctx->Const.MaxLineWidth = 10.0;
308 ctx->Const.MaxLineWidthAA = 10.0;
309 ctx->Const.LineWidthGranularity = 0.0625;
310
311 ctx->Const.VertexProgram.MaxNativeInstructions = R200_VSF_MAX_INST;
312 ctx->Const.VertexProgram.MaxNativeAttribs = 12;
313 ctx->Const.VertexProgram.MaxNativeTemps = R200_VSF_MAX_TEMPS;
314 ctx->Const.VertexProgram.MaxNativeParameters = R200_VSF_MAX_PARAM;
315 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
316
317 ctx->Const.MaxDrawBuffers = 1;
318 ctx->Const.MaxColorAttachments = 1;
319
320 _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
321
322 /* Initialize the software rasterizer and helper modules.
323 */
324 _swrast_CreateContext( ctx );
325 _vbo_CreateContext( ctx );
326 _tnl_CreateContext( ctx );
327 _swsetup_CreateContext( ctx );
328 _ae_create_context( ctx );
329
330 /* Install the customized pipeline:
331 */
332 _tnl_destroy_pipeline( ctx );
333 _tnl_install_pipeline( ctx, r200_pipeline );
334
335 /* Try and keep materials and vertices separate:
336 */
337 /* _tnl_isolate_materials( ctx, GL_TRUE ); */
338
339
340 /* Configure swrast and TNL to match hardware characteristics:
341 */
342 _swrast_allow_pixel_fog( ctx, GL_FALSE );
343 _swrast_allow_vertex_fog( ctx, GL_TRUE );
344 _tnl_allow_pixel_fog( ctx, GL_FALSE );
345 _tnl_allow_vertex_fog( ctx, GL_TRUE );
346
347
348 for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS ; i++ ) {
349 _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
350 _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
351 }
352 _math_matrix_ctr( &rmesa->tmpmat );
353 _math_matrix_set_identity( &rmesa->tmpmat );
354
355 ctx->Extensions.ARB_half_float_pixel = true;
356 ctx->Extensions.ARB_occlusion_query = true;
357 ctx->Extensions.ARB_texture_border_clamp = true;
358 ctx->Extensions.ARB_texture_env_combine = true;
359 ctx->Extensions.ARB_texture_env_dot3 = true;
360 ctx->Extensions.ARB_texture_env_crossbar = true;
361 ctx->Extensions.ARB_vertex_array_object = true;
362 ctx->Extensions.EXT_blend_color =
363 rmesa->radeon.radeonScreen->drmSupportsBlendColor;
364 ctx->Extensions.EXT_blend_minmax = true;
365 ctx->Extensions.EXT_fog_coord = true;
366 ctx->Extensions.EXT_packed_depth_stencil = true;
367 ctx->Extensions.EXT_secondary_color = true;
368 ctx->Extensions.EXT_texture_env_dot3 = true;
369 ctx->Extensions.EXT_texture_filter_anisotropic = true;
370 ctx->Extensions.EXT_texture_mirror_clamp = true;
371 ctx->Extensions.APPLE_vertex_array_object = true;
372 ctx->Extensions.ATI_texture_env_combine3 = true;
373 ctx->Extensions.ATI_texture_mirror_once = true;
374 ctx->Extensions.MESA_pack_invert = true;
375 ctx->Extensions.NV_blend_square = true;
376 ctx->Extensions.NV_texture_rectangle = true;
377 #if FEATURE_OES_EGL_image
378 ctx->Extensions.OES_EGL_image = true;
379 #endif
380
381 ctx->Extensions.EXT_framebuffer_object = true;
382 ctx->Extensions.ARB_occlusion_query = true;
383
384 if (!(rmesa->radeon.radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) {
385 /* yuv textures don't work with some chips - R200 / rv280 okay so far
386 others get the bit ordering right but don't actually do YUV-RGB conversion */
387 ctx->Extensions.MESA_ycbcr_texture = true;
388 }
389 if (rmesa->radeon.glCtx->Mesa_DXTn) {
390 ctx->Extensions.EXT_texture_compression_s3tc = true;
391 ctx->Extensions.S3_s3tc = true;
392 }
393 else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
394 ctx->Extensions.EXT_texture_compression_s3tc = true;
395 }
396
397 ctx->Extensions.ARB_texture_cube_map =
398 rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200;
399
400 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
401 ctx->Extensions.EXT_blend_equation_separate = true;
402 ctx->Extensions.EXT_blend_func_separate = true;
403 }
404
405 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
406 ctx->Extensions.ARB_vertex_program = true;
407 ctx->Extensions.EXT_gpu_program_parameters = true;
408 }
409
410 ctx->Extensions.NV_vertex_program =
411 driQueryOptionb(&rmesa->radeon.optionCache, "nv_vertex_program");
412
413 ctx->Extensions.ATI_fragment_shader = (ctx->Const.MaxTextureUnits == 6)
414 && rmesa->radeon.radeonScreen->drmSupportsFragShader;
415
416 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
417 ctx->Extensions.ARB_point_sprite = true;
418 ctx->Extensions.EXT_point_parameters = true;
419 }
420
421 #if 0
422 r200InitDriverFuncs( ctx );
423 r200InitIoctlFuncs( ctx );
424 r200InitStateFuncs( ctx );
425 r200InitTextureFuncs( ctx );
426 #endif
427 /* plug in a few more device driver functions */
428 /* XXX these should really go right after _mesa_init_driver_functions() */
429 radeon_fbo_init(&rmesa->radeon);
430 radeonInitSpanFuncs( ctx );
431 r200InitTnlFuncs( ctx );
432 r200InitState( rmesa );
433 r200InitSwtcl( ctx );
434
435 rmesa->prefer_gart_client_texturing =
436 (getenv("R200_GART_CLIENT_TEXTURES") != 0);
437
438 tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
439 if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
440 fprintf(stderr, "disabling 3D acceleration\n");
441 FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1);
442 }
443 else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") ||
444 !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
445 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
446 rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
447 fprintf(stderr, "Disabling HW TCL support\n");
448 }
449 TCL_FALLBACK(rmesa->radeon.glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1);
450 }
451
452 return GL_TRUE;
453 }
454
455
456 void r200DestroyContext( __DRIcontext *driContextPriv )
457 {
458 int i;
459 r200ContextPtr rmesa = (r200ContextPtr)driContextPriv->driverPrivate;
460 if (rmesa)
461 {
462 for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS ; i++ ) {
463 _math_matrix_dtr( &rmesa->TexGenMatrix[i] );
464 }
465 }
466 radeonDestroyContext(driContextPriv);
467 }