2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
35 #ifndef __R200_CONTEXT_H__
36 #define __R200_CONTEXT_H__
38 #include "tnl/t_vertex.h"
40 #include "radeon_drm.h"
44 #include "main/macros.h"
45 #include "main/mtypes.h"
46 #include "main/colormac.h"
48 #include "r200_vertprog.h"
50 #define ENABLE_HW_3D_TEXTURE 1 /* XXX this is temporary! */
52 #ifndef R200_EMIT_VAP_PVS_CNTL
53 #error This driver requires a newer libdrm to compile
56 #include "common_context.h"
59 typedef struct r200_context r200ContextRec
;
60 typedef struct r200_context
*r200ContextPtr
;
62 #include "r200_lock.h"
63 #include "radeon_screen.h"
66 typedef void (*r200_tri_func
)( r200ContextPtr
,
71 typedef void (*r200_line_func
)( r200ContextPtr
,
75 typedef void (*r200_point_func
)( r200ContextPtr
,
79 struct r200_vertex_program
{
80 struct gl_vertex_program mesa_program
; /* Must be first */
82 /* need excess instr: 1 for late loop checking, 2 for
83 additional instr due to instr/attr, 3 for fog */
84 VERTEX_SHADER_INSTRUCTION instr
[R200_VSF_MAX_INST
+ 6];
86 int inputs
[VERT_ATTRIB_MAX
];
87 GLubyte inputmap_rev
[16];
93 #define R200_TEX_ALL 0x3f
96 struct r200_texture_env_state
{
97 radeonTexObjPtr texobj
;
102 #define R200_MAX_TEXTURE_UNITS 6
104 struct r200_texture_state
{
105 struct r200_texture_env_state unit
[R200_MAX_TEXTURE_UNITS
];
109 /* Trying to keep these relatively short as the variables are becoming
110 * extravagently long. Drop the driver name prefix off the front of
111 * everything - I think we know which driver we're in by now, and keep the
112 * prefix to 3 letters unless absolutely impossible.
116 #define CTX_PP_MISC 1
117 #define CTX_PP_FOG_COLOR 2
118 #define CTX_RE_SOLID_COLOR 3
119 #define CTX_RB3D_BLENDCNTL 4
120 #define CTX_RB3D_DEPTHOFFSET 5
121 #define CTX_RB3D_DEPTHPITCH 6
122 #define CTX_RB3D_ZSTENCILCNTL 7
124 #define CTX_PP_CNTL 9
125 #define CTX_RB3D_CNTL 10
126 #define CTX_RB3D_COLOROFFSET 11
127 #define CTX_CMD_2 12 /* why */
128 #define CTX_RB3D_COLORPITCH 13 /* why */
129 #define CTX_STATE_SIZE_OLDDRM 14
131 #define CTX_RB3D_BLENDCOLOR 15
132 #define CTX_RB3D_ABLENDCNTL 16
133 #define CTX_RB3D_CBLENDCNTL 17
134 #define CTX_STATE_SIZE_NEWDRM 18
137 #define SET_SE_CNTL 1
138 #define SET_RE_CNTL 2 /* replace se_coord_fmt */
139 #define SET_STATE_SIZE 3
142 #define VTE_SE_VTE_CNTL 1
143 #define VTE_STATE_SIZE 2
146 #define LIN_RE_LINE_PATTERN 1
147 #define LIN_RE_LINE_STATE 2
149 #define LIN_SE_LINE_WIDTH 4
150 #define LIN_STATE_SIZE 5
153 #define MSK_RB3D_STENCILREFMASK 1
154 #define MSK_RB3D_ROPCNTL 2
155 #define MSK_RB3D_PLANEMASK 3
156 #define MSK_STATE_SIZE 4
159 #define VPT_SE_VPORT_XSCALE 1
160 #define VPT_SE_VPORT_XOFFSET 2
161 #define VPT_SE_VPORT_YSCALE 3
162 #define VPT_SE_VPORT_YOFFSET 4
163 #define VPT_SE_VPORT_ZSCALE 5
164 #define VPT_SE_VPORT_ZOFFSET 6
165 #define VPT_STATE_SIZE 7
168 #define ZBS_SE_ZBIAS_FACTOR 1
169 #define ZBS_SE_ZBIAS_CONSTANT 2
170 #define ZBS_STATE_SIZE 3
173 #define MSC_RE_MISC 1
174 #define MSC_STATE_SIZE 2
178 #define TAM_STATE_SIZE 2
181 #define TEX_PP_TXFILTER 1 /*2c00*/
182 #define TEX_PP_TXFORMAT 2 /*2c04*/
183 #define TEX_PP_TXFORMAT_X 3 /*2c08*/
184 #define TEX_PP_TXSIZE 4 /*2c0c*/
185 #define TEX_PP_TXPITCH 5 /*2c10*/
186 #define TEX_PP_BORDER_COLOR 6 /*2c14*/
187 #define TEX_CMD_1_OLDDRM 7
188 #define TEX_PP_TXOFFSET_OLDDRM 8 /*2d00 */
189 #define TEX_STATE_SIZE_OLDDRM 9
190 #define TEX_PP_CUBIC_FACES 7
191 #define TEX_PP_TXMULTI_CTL 8
192 #define TEX_CMD_1_NEWDRM 9
193 #define TEX_PP_TXOFFSET_NEWDRM 10
194 #define TEX_STATE_SIZE_NEWDRM 11
196 #define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */
197 #define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */
198 #define CUBE_CMD_1 2 /* 5 registers follow */
199 #define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */
200 #define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */
201 #define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */
202 #define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */
203 #define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */
204 #define CUBE_STATE_SIZE 8
207 #define PIX_PP_TXCBLEND 1
208 #define PIX_PP_TXCBLEND2 2
209 #define PIX_PP_TXABLEND 3
210 #define PIX_PP_TXABLEND2 4
211 #define PIX_STATE_SIZE 5
214 #define TF_TFACTOR_0 1
215 #define TF_TFACTOR_1 2
216 #define TF_TFACTOR_2 3
217 #define TF_TFACTOR_3 4
218 #define TF_TFACTOR_4 5
219 #define TF_TFACTOR_5 6
220 #define TF_STATE_SIZE 7
223 #define ATF_TFACTOR_0 1
224 #define ATF_TFACTOR_1 2
225 #define ATF_TFACTOR_2 3
226 #define ATF_TFACTOR_3 4
227 #define ATF_TFACTOR_4 5
228 #define ATF_TFACTOR_5 6
229 #define ATF_TFACTOR_6 7
230 #define ATF_TFACTOR_7 8
231 #define ATF_STATE_SIZE 9
233 /* ATI_FRAGMENT_SHADER */
235 #define AFS_IC0 1 /* 2f00 */
236 #define AFS_IC1 2 /* 2f04 */
237 #define AFS_IA0 3 /* 2f08 */
238 #define AFS_IA1 4 /* 2f0c */
239 #define AFS_STATE_SIZE 33
244 #define PVS_STATE_SIZE 3
246 /* those are quite big... */
248 #define VPI_OPDST_0 1
252 #define VPI_OPDST_63 253
253 #define VPI_SRC0_63 254
254 #define VPI_SRC1_63 255
255 #define VPI_SRC2_63 256
256 #define VPI_STATE_SIZE 257
259 #define VPP_PARAM0_0 1
260 #define VPP_PARAM1_0 2
261 #define VPP_PARAM2_0 3
262 #define VPP_PARAM3_0 4
263 #define VPP_PARAM0_95 381
264 #define VPP_PARAM1_95 382
265 #define VPP_PARAM2_95 383
266 #define VPP_PARAM3_95 384
267 #define VPP_STATE_SIZE 385
270 #define TCL_LIGHT_MODEL_CTL_0 1
271 #define TCL_LIGHT_MODEL_CTL_1 2
272 #define TCL_PER_LIGHT_CTL_0 3
273 #define TCL_PER_LIGHT_CTL_1 4
274 #define TCL_PER_LIGHT_CTL_2 5
275 #define TCL_PER_LIGHT_CTL_3 6
277 #define TCL_UCP_VERT_BLEND_CTL 8
278 #define TCL_STATE_SIZE 9
281 #define MSL_MATRIX_SELECT_0 1
282 #define MSL_MATRIX_SELECT_1 2
283 #define MSL_MATRIX_SELECT_2 3
284 #define MSL_MATRIX_SELECT_3 4
285 #define MSL_MATRIX_SELECT_4 5
286 #define MSL_STATE_SIZE 6
289 #define TCG_TEX_PROC_CTL_2 1
290 #define TCG_TEX_PROC_CTL_3 2
291 #define TCG_TEX_PROC_CTL_0 3
292 #define TCG_TEX_PROC_CTL_1 4
293 #define TCG_TEX_CYL_WRAP_CTL 5
294 #define TCG_STATE_SIZE 6
297 #define MTL_EMMISSIVE_RED 1
298 #define MTL_EMMISSIVE_GREEN 2
299 #define MTL_EMMISSIVE_BLUE 3
300 #define MTL_EMMISSIVE_ALPHA 4
301 #define MTL_AMBIENT_RED 5
302 #define MTL_AMBIENT_GREEN 6
303 #define MTL_AMBIENT_BLUE 7
304 #define MTL_AMBIENT_ALPHA 8
305 #define MTL_DIFFUSE_RED 9
306 #define MTL_DIFFUSE_GREEN 10
307 #define MTL_DIFFUSE_BLUE 11
308 #define MTL_DIFFUSE_ALPHA 12
309 #define MTL_SPECULAR_RED 13
310 #define MTL_SPECULAR_GREEN 14
311 #define MTL_SPECULAR_BLUE 15
312 #define MTL_SPECULAR_ALPHA 16
314 #define MTL_SHININESS 18
315 #define MTL_STATE_SIZE 19
318 #define VAP_SE_VAP_CNTL 1
319 #define VAP_STATE_SIZE 2
321 /* Replaces a lot of packet info from radeon
324 #define VTX_VTXFMT_0 1
325 #define VTX_VTXFMT_1 2
326 #define VTX_TCL_OUTPUT_VTXFMT_0 3
327 #define VTX_TCL_OUTPUT_VTXFMT_1 4
329 #define VTX_TCL_OUTPUT_COMPSEL 6
331 #define VTX_STATE_CNTL 8
332 #define VTX_STATE_SIZE 9
334 /* SPR - point sprite state
337 #define SPR_POINT_SPRITE_CNTL 1
338 #define SPR_STATE_SIZE 2
341 #define PTP_VPORT_SCALE_0 1
342 #define PTP_VPORT_SCALE_1 2
343 #define PTP_VPORT_SCALE_PTSIZE 3
344 #define PTP_VPORT_SCALE_3 4
346 #define PTP_ATT_CONST_QUAD 6
347 #define PTP_ATT_CONST_LIN 7
348 #define PTP_ATT_CONST_CON 8
349 #define PTP_ATT_CONST_3 9
354 #define PTP_CLAMP_MIN 14
355 #define PTP_CLAMP_MAX 15
356 #define PTP_CLAMP_2 16
357 #define PTP_CLAMP_3 17
358 #define PTP_STATE_SIZE 18
360 #define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\
364 * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine
365 * how many components are in texture coordinate \c n.
367 #define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07)
371 #define MAT_STATE_SIZE 17
374 #define GRD_VERT_GUARD_CLIP_ADJ 1
375 #define GRD_VERT_GUARD_DISCARD_ADJ 2
376 #define GRD_HORZ_GUARD_CLIP_ADJ 3
377 #define GRD_HORZ_GUARD_DISCARD_ADJ 4
378 #define GRD_STATE_SIZE 5
380 /* position changes frequently when lighting in modelpos - separate
381 * out to new state item?
384 #define LIT_AMBIENT_RED 1
385 #define LIT_AMBIENT_GREEN 2
386 #define LIT_AMBIENT_BLUE 3
387 #define LIT_AMBIENT_ALPHA 4
388 #define LIT_DIFFUSE_RED 5
389 #define LIT_DIFFUSE_GREEN 6
390 #define LIT_DIFFUSE_BLUE 7
391 #define LIT_DIFFUSE_ALPHA 8
392 #define LIT_SPECULAR_RED 9
393 #define LIT_SPECULAR_GREEN 10
394 #define LIT_SPECULAR_BLUE 11
395 #define LIT_SPECULAR_ALPHA 12
396 #define LIT_POSITION_X 13
397 #define LIT_POSITION_Y 14
398 #define LIT_POSITION_Z 15
399 #define LIT_POSITION_W 16
400 #define LIT_DIRECTION_X 17
401 #define LIT_DIRECTION_Y 18
402 #define LIT_DIRECTION_Z 19
403 #define LIT_DIRECTION_W 20
404 #define LIT_ATTEN_QUADRATIC 21
405 #define LIT_ATTEN_LINEAR 22
406 #define LIT_ATTEN_CONST 23
407 #define LIT_ATTEN_XXX 24
409 #define LIT_SPOT_DCD 26
410 #define LIT_SPOT_DCM 27
411 #define LIT_SPOT_EXPONENT 28
412 #define LIT_SPOT_CUTOFF 29
413 #define LIT_SPECULAR_THRESH 30
414 #define LIT_RANGE_CUTOFF 31 /* ? */
415 #define LIT_ATTEN_CONST_INV 32
416 #define LIT_STATE_SIZE 33
425 #define FOG_STATE_SIZE 5
434 #define UCP_STATE_SIZE 5
436 /* GLT - Global ambient
443 #define GLT_STATE_SIZE 5
451 #define EYE_RESCALE_FACTOR 4
452 #define EYE_STATE_SIZE 5
454 /* CST - constant state
457 #define CST_PP_CNTL_X 1
459 #define CST_RB3D_DEPTHXY_OFFSET 3
461 #define CST_RE_AUX_SCISSOR_CNTL 5
463 #define CST_RE_SCISSOR_TL_0 7
464 #define CST_RE_SCISSOR_BR_0 8
466 #define CST_SE_VAP_CNTL_STATUS 10
468 #define CST_RE_POINTSIZE 12
470 #define CST_SE_TCL_INPUT_VTX_0 14
471 #define CST_SE_TCL_INPUT_VTX_1 15
472 #define CST_SE_TCL_INPUT_VTX_2 16
473 #define CST_SE_TCL_INPUT_VTX_3 17
474 #define CST_STATE_SIZE 18
477 #define PRF_PP_TRI_PERF 1
478 #define PRF_PP_PERF_CNTL 2
479 #define PRF_STATE_SIZE 3
482 struct r200_hw_state
{
483 /* Head of the linked list of state atoms. */
484 struct radeon_state_atom atomlist
;
486 /* Hardware state, stored as cmdbuf commands:
487 * -- Need to doublebuffer for
488 * - reviving state after loss of context
489 * - eliding noop statechange loops? (except line stipple count)
491 struct radeon_state_atom ctx
;
492 struct radeon_state_atom set
;
493 struct radeon_state_atom vte
;
494 struct radeon_state_atom lin
;
495 struct radeon_state_atom msk
;
496 struct radeon_state_atom vpt
;
497 struct radeon_state_atom vap
;
498 struct radeon_state_atom vtx
;
499 struct radeon_state_atom tcl
;
500 struct radeon_state_atom msl
;
501 struct radeon_state_atom tcg
;
502 struct radeon_state_atom msc
;
503 struct radeon_state_atom cst
;
504 struct radeon_state_atom tam
;
505 struct radeon_state_atom tf
;
506 struct radeon_state_atom tex
[6];
507 struct radeon_state_atom cube
[6];
508 struct radeon_state_atom zbs
;
509 struct radeon_state_atom mtl
[2];
510 struct radeon_state_atom mat
[9];
511 struct radeon_state_atom lit
[8]; /* includes vec, scl commands */
512 struct radeon_state_atom ucp
[6];
513 struct radeon_state_atom pix
[6]; /* pixshader stages */
514 struct radeon_state_atom eye
; /* eye pos */
515 struct radeon_state_atom grd
; /* guard band clipping */
516 struct radeon_state_atom fog
;
517 struct radeon_state_atom glt
;
518 struct radeon_state_atom prf
;
519 struct radeon_state_atom afs
[2];
520 struct radeon_state_atom pvs
;
521 struct radeon_state_atom vpi
[2];
522 struct radeon_state_atom vpp
[2];
523 struct radeon_state_atom atf
;
524 struct radeon_state_atom spr
;
525 struct radeon_state_atom ptp
;
527 int max_state_size
; /* Number of bytes necessary for a full state emit. */
528 GLboolean is_dirty
, all_dirty
;
532 /* Derived state for internal purposes:
534 struct radeon_colorbuffer_state color
;
535 struct radeon_depthbuffer_state depth
;
536 struct radeon_scissor_state scissor
;
537 struct radeon_stencilbuffer_state stencil
;
538 struct radeon_stipple_state stipple
;
539 struct r200_texture_state texture
;
543 #define GET_START(rvb) (rmesa->r200Screen->gart_buffer_offset + \
544 (rvb)->address - rmesa->dma.buf0_address + \
547 #define R200_CMD_BUF_SZ (16*1024)
552 char cmd_buf
[R200_CMD_BUF_SZ
];
560 struct r200_tcl_info
{
563 /* hw can handle 12 components max */
564 struct radeon_dma_region
*aos_components
[12];
565 GLuint nr_aos_components
;
569 struct radeon_dma_region indexed_verts
;
570 struct radeon_dma_region vertex_data
[15];
576 struct r200_swtcl_info
{
580 * Size of a hardware vertex. This is calculated when \c ::vertex_attrs is
581 * installed in the Mesa state vector.
586 * Attributes instructing the Mesa TCL pipeline where / how to put vertex
587 * data in the hardware buffer.
589 struct tnl_attr_map vertex_attrs
[VERT_ATTRIB_MAX
];
592 * Number of elements of \c ::vertex_attrs that are actually used.
594 GLuint vertex_attr_count
;
597 * Cached pointer to the buffer where Mesa will store vertex data.
601 /* Fallback rasterization functions
603 r200_point_func draw_point
;
604 r200_line_func draw_line
;
605 r200_tri_func draw_tri
;
608 GLenum render_primitive
;
612 * Offset of the 4UB color data within a hardware (swtcl) vertex.
617 * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
622 * Should Mesa project vertex data or will the hardware do it?
626 struct radeon_dma_region indexed_verts
;
632 /* A maximum total of 29 elements per vertex: 3 floats for position, 3
633 * floats for normal, 4 floats for color, 4 bytes for secondary color,
634 * 3 floats for each texture unit (18 floats total).
636 * we maybe need add. 4 to prevent segfault if someone specifies
637 * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: )
639 * The position data is never actually stored here, so 3 elements could be
640 * trimmed out of the buffer.
643 #define R200_MAX_VERTEX_SIZE ((3*6)+11)
646 struct r200_context
{
647 GLcontext
*glCtx
; /* Mesa context */
649 /* Driver and hardware state management
651 struct r200_hw_state hw
;
652 struct r200_state state
;
653 struct r200_vertex_program
*curr_vp_hw
;
655 /* Texture object bookkeeping
658 driTexHeap
* texture_heaps
[ RADEON_NR_TEX_HEAPS
];
659 driTextureObject swapped
;
661 float initialMaxAnisotropy
;
663 /* Rasterization and vertex state:
668 DECLARE_RENDERINPUTS(tnl_index_bitset
); /* index of bits for last tnl_install_attrs */
672 struct radeon_ioctl ioctl
;
673 struct radeon_dma dma
;
674 struct r200_store store
;
675 /* A full state emit as of the first state emit in the main store, in case
676 * the context is lost.
678 struct r200_store backup_store
;
689 drm_radeon_irq_wait_t iw
;
691 /* Clientdata textures;
693 GLuint prefer_gart_client_texturing
;
695 /* Drawable, cliprect and scissor information
697 GLuint numClipRects
; /* Cliprects for the draw buffer */
698 drm_clip_rect_t
*pClipRects
;
699 unsigned int lastStamp
;
700 GLboolean lost_context
;
701 GLboolean save_on_next_emit
;
702 radeonScreenPtr r200Screen
; /* Screen private DRI data */
703 drm_radeon_sarea_t
*sarea
; /* Private SAREA data */
707 GLmatrix TexGenMatrix
[R200_MAX_TEXTURE_UNITS
];
708 GLboolean recheck_texgen
[R200_MAX_TEXTURE_UNITS
];
709 GLboolean TexGenNeedNormals
[R200_MAX_TEXTURE_UNITS
];
710 GLuint TexMatEnabled
;
711 GLuint TexMatCompSel
;
712 GLuint TexGenEnabled
;
713 GLuint TexGenCompSel
;
719 int64_t swap_missed_ust
;
722 GLuint swap_missed_count
;
727 struct r200_tcl_info tcl
;
731 struct r200_swtcl_info swtcl
;
733 /* Mirrors of some DRI state
735 struct radeon_dri_mirror dri
;
737 /* Configuration cache
739 driOptionCache optionCache
;
741 GLboolean using_hyperz
;
742 GLboolean texmicrotile
;
744 struct ati_fragment_shader
*afs_loaded
;
747 #define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx))
750 extern void r200DestroyContext( __DRIcontextPrivate
*driContextPriv
);
751 extern GLboolean
r200CreateContext( const __GLcontextModes
*glVisual
,
752 __DRIcontextPrivate
*driContextPriv
,
753 void *sharedContextPrivate
);
754 extern void r200SwapBuffers( __DRIdrawablePrivate
*dPriv
);
755 extern void r200CopySubBuffer( __DRIdrawablePrivate
* dPriv
,
756 int x
, int y
, int w
, int h
);
757 extern GLboolean
r200MakeCurrent( __DRIcontextPrivate
*driContextPriv
,
758 __DRIdrawablePrivate
*driDrawPriv
,
759 __DRIdrawablePrivate
*driReadPriv
);
760 extern GLboolean
r200UnbindContext( __DRIcontextPrivate
*driContextPriv
);
762 /* ================================================================
768 extern int R200_DEBUG
;
775 #endif /* __R200_CONTEXT_H__ */