2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
35 #ifndef __R200_CONTEXT_H__
36 #define __R200_CONTEXT_H__
38 #include "tnl/t_vertex.h"
40 #include "radeon_drm.h"
44 #include "main/macros.h"
45 #include "main/mtypes.h"
46 #include "main/colormac.h"
48 #include "r200_vertprog.h"
50 #define ENABLE_HW_3D_TEXTURE 1 /* XXX this is temporary! */
52 #ifndef R200_EMIT_VAP_PVS_CNTL
53 #error This driver requires a newer libdrm to compile
56 #include "radeon_screen.h"
57 #include "radeon_common.h"
59 #include "radeon_lock.h"
62 typedef struct r200_context r200ContextRec
;
63 typedef struct r200_context
*r200ContextPtr
;
67 struct r200_vertex_program
{
68 struct gl_vertex_program mesa_program
; /* Must be first */
70 /* need excess instr: 1 for late loop checking, 2 for
71 additional instr due to instr/attr, 3 for fog */
72 VERTEX_SHADER_INSTRUCTION instr
[R200_VSF_MAX_INST
+ 6];
74 int inputs
[VERT_ATTRIB_MAX
];
75 GLubyte inputmap_rev
[16];
81 #define R200_TEX_ALL 0x3f
84 struct r200_texture_env_state
{
85 radeonTexObjPtr texobj
;
90 #define R200_MAX_TEXTURE_UNITS 6
92 struct r200_texture_state
{
93 struct r200_texture_env_state unit
[R200_MAX_TEXTURE_UNITS
];
97 /* Trying to keep these relatively short as the variables are becoming
98 * extravagently long. Drop the driver name prefix off the front of
99 * everything - I think we know which driver we're in by now, and keep the
100 * prefix to 3 letters unless absolutely impossible.
104 #define CTX_PP_MISC 1
105 #define CTX_PP_FOG_COLOR 2
106 #define CTX_RE_SOLID_COLOR 3
107 #define CTX_RB3D_BLENDCNTL 4
108 #define CTX_RB3D_DEPTHOFFSET 5
109 #define CTX_RB3D_DEPTHPITCH 6
110 #define CTX_RB3D_ZSTENCILCNTL 7
112 #define CTX_PP_CNTL 9
113 #define CTX_RB3D_CNTL 10
114 #define CTX_RB3D_COLOROFFSET 11
115 #define CTX_CMD_2 12 /* why */
116 #define CTX_RB3D_COLORPITCH 13 /* why */
117 #define CTX_STATE_SIZE_OLDDRM 14
119 #define CTX_RB3D_BLENDCOLOR 15
120 #define CTX_RB3D_ABLENDCNTL 16
121 #define CTX_RB3D_CBLENDCNTL 17
122 #define CTX_STATE_SIZE_NEWDRM 18
125 #define SET_SE_CNTL 1
126 #define SET_RE_CNTL 2 /* replace se_coord_fmt */
127 #define SET_STATE_SIZE 3
130 #define VTE_SE_VTE_CNTL 1
131 #define VTE_STATE_SIZE 2
134 #define LIN_RE_LINE_PATTERN 1
135 #define LIN_RE_LINE_STATE 2
137 #define LIN_SE_LINE_WIDTH 4
138 #define LIN_STATE_SIZE 5
141 #define MSK_RB3D_STENCILREFMASK 1
142 #define MSK_RB3D_ROPCNTL 2
143 #define MSK_RB3D_PLANEMASK 3
144 #define MSK_STATE_SIZE 4
147 #define VPT_SE_VPORT_XSCALE 1
148 #define VPT_SE_VPORT_XOFFSET 2
149 #define VPT_SE_VPORT_YSCALE 3
150 #define VPT_SE_VPORT_YOFFSET 4
151 #define VPT_SE_VPORT_ZSCALE 5
152 #define VPT_SE_VPORT_ZOFFSET 6
153 #define VPT_STATE_SIZE 7
156 #define ZBS_SE_ZBIAS_FACTOR 1
157 #define ZBS_SE_ZBIAS_CONSTANT 2
158 #define ZBS_STATE_SIZE 3
161 #define MSC_RE_MISC 1
162 #define MSC_STATE_SIZE 2
166 #define TAM_STATE_SIZE 2
169 #define TEX_PP_TXFILTER 1 /*2c00*/
170 #define TEX_PP_TXFORMAT 2 /*2c04*/
171 #define TEX_PP_TXFORMAT_X 3 /*2c08*/
172 #define TEX_PP_TXSIZE 4 /*2c0c*/
173 #define TEX_PP_TXPITCH 5 /*2c10*/
174 #define TEX_PP_BORDER_COLOR 6 /*2c14*/
175 #define TEX_CMD_1_OLDDRM 7
176 #define TEX_PP_TXOFFSET_OLDDRM 8 /*2d00 */
177 #define TEX_STATE_SIZE_OLDDRM 9
178 #define TEX_PP_CUBIC_FACES 7
179 #define TEX_PP_TXMULTI_CTL 8
180 #define TEX_CMD_1_NEWDRM 9
181 #define TEX_PP_TXOFFSET_NEWDRM 10
182 #define TEX_STATE_SIZE_NEWDRM 11
184 #define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */
185 #define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */
186 #define CUBE_CMD_1 2 /* 5 registers follow */
187 #define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */
188 #define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */
189 #define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */
190 #define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */
191 #define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */
192 #define CUBE_STATE_SIZE 8
195 #define PIX_PP_TXCBLEND 1
196 #define PIX_PP_TXCBLEND2 2
197 #define PIX_PP_TXABLEND 3
198 #define PIX_PP_TXABLEND2 4
199 #define PIX_STATE_SIZE 5
202 #define TF_TFACTOR_0 1
203 #define TF_TFACTOR_1 2
204 #define TF_TFACTOR_2 3
205 #define TF_TFACTOR_3 4
206 #define TF_TFACTOR_4 5
207 #define TF_TFACTOR_5 6
208 #define TF_STATE_SIZE 7
211 #define ATF_TFACTOR_0 1
212 #define ATF_TFACTOR_1 2
213 #define ATF_TFACTOR_2 3
214 #define ATF_TFACTOR_3 4
215 #define ATF_TFACTOR_4 5
216 #define ATF_TFACTOR_5 6
217 #define ATF_TFACTOR_6 7
218 #define ATF_TFACTOR_7 8
219 #define ATF_STATE_SIZE 9
221 /* ATI_FRAGMENT_SHADER */
223 #define AFS_IC0 1 /* 2f00 */
224 #define AFS_IC1 2 /* 2f04 */
225 #define AFS_IA0 3 /* 2f08 */
226 #define AFS_IA1 4 /* 2f0c */
227 #define AFS_STATE_SIZE 33
232 #define PVS_STATE_SIZE 3
234 /* those are quite big... */
236 #define VPI_OPDST_0 1
240 #define VPI_OPDST_63 253
241 #define VPI_SRC0_63 254
242 #define VPI_SRC1_63 255
243 #define VPI_SRC2_63 256
244 #define VPI_STATE_SIZE 257
247 #define VPP_PARAM0_0 1
248 #define VPP_PARAM1_0 2
249 #define VPP_PARAM2_0 3
250 #define VPP_PARAM3_0 4
251 #define VPP_PARAM0_95 381
252 #define VPP_PARAM1_95 382
253 #define VPP_PARAM2_95 383
254 #define VPP_PARAM3_95 384
255 #define VPP_STATE_SIZE 385
258 #define TCL_LIGHT_MODEL_CTL_0 1
259 #define TCL_LIGHT_MODEL_CTL_1 2
260 #define TCL_PER_LIGHT_CTL_0 3
261 #define TCL_PER_LIGHT_CTL_1 4
262 #define TCL_PER_LIGHT_CTL_2 5
263 #define TCL_PER_LIGHT_CTL_3 6
265 #define TCL_UCP_VERT_BLEND_CTL 8
266 #define TCL_STATE_SIZE 9
269 #define MSL_MATRIX_SELECT_0 1
270 #define MSL_MATRIX_SELECT_1 2
271 #define MSL_MATRIX_SELECT_2 3
272 #define MSL_MATRIX_SELECT_3 4
273 #define MSL_MATRIX_SELECT_4 5
274 #define MSL_STATE_SIZE 6
277 #define TCG_TEX_PROC_CTL_2 1
278 #define TCG_TEX_PROC_CTL_3 2
279 #define TCG_TEX_PROC_CTL_0 3
280 #define TCG_TEX_PROC_CTL_1 4
281 #define TCG_TEX_CYL_WRAP_CTL 5
282 #define TCG_STATE_SIZE 6
285 #define MTL_EMMISSIVE_RED 1
286 #define MTL_EMMISSIVE_GREEN 2
287 #define MTL_EMMISSIVE_BLUE 3
288 #define MTL_EMMISSIVE_ALPHA 4
289 #define MTL_AMBIENT_RED 5
290 #define MTL_AMBIENT_GREEN 6
291 #define MTL_AMBIENT_BLUE 7
292 #define MTL_AMBIENT_ALPHA 8
293 #define MTL_DIFFUSE_RED 9
294 #define MTL_DIFFUSE_GREEN 10
295 #define MTL_DIFFUSE_BLUE 11
296 #define MTL_DIFFUSE_ALPHA 12
297 #define MTL_SPECULAR_RED 13
298 #define MTL_SPECULAR_GREEN 14
299 #define MTL_SPECULAR_BLUE 15
300 #define MTL_SPECULAR_ALPHA 16
302 #define MTL_SHININESS 18
303 #define MTL_STATE_SIZE 19
306 #define VAP_SE_VAP_CNTL 1
307 #define VAP_STATE_SIZE 2
309 /* Replaces a lot of packet info from radeon
312 #define VTX_VTXFMT_0 1
313 #define VTX_VTXFMT_1 2
314 #define VTX_TCL_OUTPUT_VTXFMT_0 3
315 #define VTX_TCL_OUTPUT_VTXFMT_1 4
317 #define VTX_TCL_OUTPUT_COMPSEL 6
319 #define VTX_STATE_CNTL 8
320 #define VTX_STATE_SIZE 9
322 /* SPR - point sprite state
325 #define SPR_POINT_SPRITE_CNTL 1
326 #define SPR_STATE_SIZE 2
329 #define PTP_VPORT_SCALE_0 1
330 #define PTP_VPORT_SCALE_1 2
331 #define PTP_VPORT_SCALE_PTSIZE 3
332 #define PTP_VPORT_SCALE_3 4
334 #define PTP_ATT_CONST_QUAD 6
335 #define PTP_ATT_CONST_LIN 7
336 #define PTP_ATT_CONST_CON 8
337 #define PTP_ATT_CONST_3 9
342 #define PTP_CLAMP_MIN 14
343 #define PTP_CLAMP_MAX 15
344 #define PTP_CLAMP_2 16
345 #define PTP_CLAMP_3 17
346 #define PTP_STATE_SIZE 18
348 #define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\
352 * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine
353 * how many components are in texture coordinate \c n.
355 #define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07)
359 #define MAT_STATE_SIZE 17
362 #define GRD_VERT_GUARD_CLIP_ADJ 1
363 #define GRD_VERT_GUARD_DISCARD_ADJ 2
364 #define GRD_HORZ_GUARD_CLIP_ADJ 3
365 #define GRD_HORZ_GUARD_DISCARD_ADJ 4
366 #define GRD_STATE_SIZE 5
368 /* position changes frequently when lighting in modelpos - separate
369 * out to new state item?
372 #define LIT_AMBIENT_RED 1
373 #define LIT_AMBIENT_GREEN 2
374 #define LIT_AMBIENT_BLUE 3
375 #define LIT_AMBIENT_ALPHA 4
376 #define LIT_DIFFUSE_RED 5
377 #define LIT_DIFFUSE_GREEN 6
378 #define LIT_DIFFUSE_BLUE 7
379 #define LIT_DIFFUSE_ALPHA 8
380 #define LIT_SPECULAR_RED 9
381 #define LIT_SPECULAR_GREEN 10
382 #define LIT_SPECULAR_BLUE 11
383 #define LIT_SPECULAR_ALPHA 12
384 #define LIT_POSITION_X 13
385 #define LIT_POSITION_Y 14
386 #define LIT_POSITION_Z 15
387 #define LIT_POSITION_W 16
388 #define LIT_DIRECTION_X 17
389 #define LIT_DIRECTION_Y 18
390 #define LIT_DIRECTION_Z 19
391 #define LIT_DIRECTION_W 20
392 #define LIT_ATTEN_QUADRATIC 21
393 #define LIT_ATTEN_LINEAR 22
394 #define LIT_ATTEN_CONST 23
395 #define LIT_ATTEN_XXX 24
397 #define LIT_SPOT_DCD 26
398 #define LIT_SPOT_DCM 27
399 #define LIT_SPOT_EXPONENT 28
400 #define LIT_SPOT_CUTOFF 29
401 #define LIT_SPECULAR_THRESH 30
402 #define LIT_RANGE_CUTOFF 31 /* ? */
403 #define LIT_ATTEN_CONST_INV 32
404 #define LIT_STATE_SIZE 33
413 #define FOG_STATE_SIZE 5
422 #define UCP_STATE_SIZE 5
424 /* GLT - Global ambient
431 #define GLT_STATE_SIZE 5
439 #define EYE_RESCALE_FACTOR 4
440 #define EYE_STATE_SIZE 5
442 /* CST - constant state
445 #define CST_PP_CNTL_X 1
447 #define CST_RB3D_DEPTHXY_OFFSET 3
449 #define CST_RE_AUX_SCISSOR_CNTL 5
451 #define CST_RE_SCISSOR_TL_0 7
452 #define CST_RE_SCISSOR_BR_0 8
454 #define CST_SE_VAP_CNTL_STATUS 10
456 #define CST_RE_POINTSIZE 12
458 #define CST_SE_TCL_INPUT_VTX_0 14
459 #define CST_SE_TCL_INPUT_VTX_1 15
460 #define CST_SE_TCL_INPUT_VTX_2 16
461 #define CST_SE_TCL_INPUT_VTX_3 17
462 #define CST_STATE_SIZE 18
465 #define PRF_PP_TRI_PERF 1
466 #define PRF_PP_PERF_CNTL 2
467 #define PRF_STATE_SIZE 3
476 #define SCI_STATE_SIZE 6
478 #define R200_QUERYOBJ_CMD_0 0
479 #define R200_QUERYOBJ_DATA_0 1
480 #define R200_QUERYOBJ_CMDSIZE 2
482 struct r200_hw_state
{
483 /* Hardware state, stored as cmdbuf commands:
484 * -- Need to doublebuffer for
485 * - reviving state after loss of context
486 * - eliding noop statechange loops? (except line stipple count)
488 struct radeon_state_atom ctx
;
489 struct radeon_state_atom set
;
490 struct radeon_state_atom sci
;
491 struct radeon_state_atom vte
;
492 struct radeon_state_atom lin
;
493 struct radeon_state_atom msk
;
494 struct radeon_state_atom vpt
;
495 struct radeon_state_atom vap
;
496 struct radeon_state_atom vtx
;
497 struct radeon_state_atom tcl
;
498 struct radeon_state_atom msl
;
499 struct radeon_state_atom tcg
;
500 struct radeon_state_atom msc
;
501 struct radeon_state_atom cst
;
502 struct radeon_state_atom tam
;
503 struct radeon_state_atom tf
;
504 struct radeon_state_atom tex
[6];
505 struct radeon_state_atom cube
[6];
506 struct radeon_state_atom zbs
;
507 struct radeon_state_atom mtl
[2];
508 struct radeon_state_atom mat
[9];
509 struct radeon_state_atom lit
[8]; /* includes vec, scl commands */
510 struct radeon_state_atom ucp
[6];
511 struct radeon_state_atom pix
[6]; /* pixshader stages */
512 struct radeon_state_atom eye
; /* eye pos */
513 struct radeon_state_atom grd
; /* guard band clipping */
514 struct radeon_state_atom fog
;
515 struct radeon_state_atom glt
;
516 struct radeon_state_atom prf
;
517 struct radeon_state_atom afs
[2];
518 struct radeon_state_atom pvs
;
519 struct radeon_state_atom vpi
[2];
520 struct radeon_state_atom vpp
[2];
521 struct radeon_state_atom atf
;
522 struct radeon_state_atom spr
;
523 struct radeon_state_atom ptp
;
527 /* Derived state for internal purposes:
529 struct r200_texture_state texture
;
533 #define R200_CMD_BUF_SZ (16*1024)
535 #define R200_ELT_BUF_SZ (16*1024)
538 struct r200_tcl_info
{
548 struct r200_swtcl_info
{
551 radeon_point_func draw_point
;
552 radeon_line_func draw_line
;
553 radeon_tri_func draw_tri
;
556 * Offset of the 4UB color data within a hardware (swtcl) vertex.
561 * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
566 * Should Mesa project vertex data or will the hardware do it?
574 /* A maximum total of 29 elements per vertex: 3 floats for position, 3
575 * floats for normal, 4 floats for color, 4 bytes for secondary color,
576 * 3 floats for each texture unit (18 floats total).
578 * we maybe need add. 4 to prevent segfault if someone specifies
579 * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: )
581 * The position data is never actually stored here, so 3 elements could be
582 * trimmed out of the buffer.
585 #define R200_MAX_VERTEX_SIZE ((3*6)+11)
587 struct r200_context
{
588 struct radeon_context radeon
;
590 /* Driver and hardware state management
592 struct r200_hw_state hw
;
593 struct r200_state state
;
594 struct r200_vertex_program
*curr_vp_hw
;
598 struct radeon_ioctl ioctl
;
599 struct radeon_store store
;
601 /* Clientdata textures;
603 GLuint prefer_gart_client_texturing
;
607 GLmatrix TexGenMatrix
[R200_MAX_TEXTURE_UNITS
];
608 GLboolean recheck_texgen
[R200_MAX_TEXTURE_UNITS
];
609 GLboolean TexGenNeedNormals
[R200_MAX_TEXTURE_UNITS
];
610 GLuint TexMatEnabled
;
611 GLuint TexMatCompSel
;
612 GLuint TexGenEnabled
;
613 GLuint TexGenCompSel
;
618 struct r200_tcl_info tcl
;
622 struct r200_swtcl_info swtcl
;
624 GLboolean using_hyperz
;
625 GLboolean texmicrotile
;
627 struct ati_fragment_shader
*afs_loaded
;
630 #define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx))
633 extern void r200DestroyContext( __DRIcontextPrivate
*driContextPriv
);
634 extern GLboolean
r200CreateContext( const __GLcontextModes
*glVisual
,
635 __DRIcontextPrivate
*driContextPriv
,
636 void *sharedContextPrivate
);
637 extern GLboolean
r200MakeCurrent( __DRIcontextPrivate
*driContextPriv
,
638 __DRIdrawablePrivate
*driDrawPriv
,
639 __DRIdrawablePrivate
*driReadPriv
);
640 extern GLboolean
r200UnbindContext( __DRIcontextPrivate
*driContextPriv
);
642 /* ================================================================
646 #define R200_DEBUG RADEON_DEBUG
650 #endif /* __R200_CONTEXT_H__ */