1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_ioctl.c,v 1.4 2002/12/17 00:32:56 dawes Exp $ */
3 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 The Weather Channel (TM) funded Tungsten Graphics to develop the
6 initial release of the Radeon 8500 driver under the XFree86 license.
7 This notice must be preserved.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Keith Whitwell <keith@tungstengraphics.com>
43 #include "swrast/swrast.h"
45 #include "r200_context.h"
46 #include "r200_state.h"
47 #include "r200_ioctl.h"
49 #include "r200_sanity.h"
50 #include "radeon_reg.h"
55 #define R200_TIMEOUT 512
56 #define R200_IDLE_RETRY 16
59 static void r200WaitForIdle( r200ContextPtr rmesa
);
62 /* At this point we were in FlushCmdBufLocked but we had lost our context, so
63 * we need to unwire our current cmdbuf, hook the one with the saved state in
64 * it, flush it, and then put the current one back. This is so commands at the
65 * start of a cmdbuf can rely on the state being kept from the previous one.
67 static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa
)
69 GLuint nr_released_bufs
;
70 struct r200_store saved_store
;
72 if (rmesa
->backup_store
.cmd_used
== 0)
75 if (R200_DEBUG
& DEBUG_STATE
)
76 fprintf(stderr
, "Emitting backup state on lost context\n");
78 rmesa
->lost_context
= GL_FALSE
;
80 nr_released_bufs
= rmesa
->dma
.nr_released_bufs
;
81 saved_store
= rmesa
->store
;
82 rmesa
->dma
.nr_released_bufs
= 0;
83 rmesa
->store
= rmesa
->backup_store
;
84 r200FlushCmdBufLocked( rmesa
, __FUNCTION__
);
85 rmesa
->dma
.nr_released_bufs
= nr_released_bufs
;
86 rmesa
->store
= saved_store
;
89 int r200FlushCmdBufLocked( r200ContextPtr rmesa
, const char * caller
)
92 drm_radeon_cmd_buffer_t cmd
;
94 if (rmesa
->lost_context
)
95 r200BackUpAndEmitLostStateLocked( rmesa
);
97 if (R200_DEBUG
& DEBUG_IOCTL
) {
98 fprintf(stderr
, "%s from %s\n", __FUNCTION__
, caller
);
100 if (0 & R200_DEBUG
& DEBUG_VERBOSE
)
101 for (i
= 0 ; i
< rmesa
->store
.cmd_used
; i
+= 4 )
102 fprintf(stderr
, "%d: %x\n", i
/4,
103 *(int *)(&rmesa
->store
.cmd_buf
[i
]));
106 if (R200_DEBUG
& DEBUG_DMA
)
107 fprintf(stderr
, "%s: Releasing %d buffers\n", __FUNCTION__
,
108 rmesa
->dma
.nr_released_bufs
);
111 if (R200_DEBUG
& DEBUG_SANITY
) {
112 if (rmesa
->state
.scissor
.enabled
)
113 ret
= r200SanityCmdBuffer( rmesa
,
114 rmesa
->state
.scissor
.numClipRects
,
115 rmesa
->state
.scissor
.pClipRects
);
117 ret
= r200SanityCmdBuffer( rmesa
,
121 fprintf(stderr
, "drmSanityCommandWrite: %d\n", ret
);
127 if (R200_DEBUG
& DEBUG_MEMORY
) {
128 if (! driValidateTextureHeaps( rmesa
->texture_heaps
, rmesa
->nr_heaps
,
129 & rmesa
->swapped
) ) {
130 fprintf( stderr
, "%s: texture memory is inconsistent - expect "
131 "mangled textures\n", __FUNCTION__
);
136 cmd
.bufsz
= rmesa
->store
.cmd_used
;
137 cmd
.buf
= rmesa
->store
.cmd_buf
;
139 if (rmesa
->state
.scissor
.enabled
) {
140 cmd
.nbox
= rmesa
->state
.scissor
.numClipRects
;
141 cmd
.boxes
= (drm_clip_rect_t
*)rmesa
->state
.scissor
.pClipRects
;
143 cmd
.nbox
= rmesa
->numClipRects
;
144 cmd
.boxes
= (drm_clip_rect_t
*)rmesa
->pClipRects
;
147 ret
= drmCommandWrite( rmesa
->dri
.fd
,
152 fprintf(stderr
, "drmCommandWrite: %d\n", ret
);
154 if (R200_DEBUG
& DEBUG_SYNC
) {
155 fprintf(stderr
, "\nSyncing in %s\n\n", __FUNCTION__
);
156 r200WaitForIdleLocked( rmesa
);
161 rmesa
->store
.primnr
= 0;
162 rmesa
->store
.statenr
= 0;
163 rmesa
->store
.cmd_used
= 0;
164 rmesa
->dma
.nr_released_bufs
= 0;
165 rmesa
->save_on_next_emit
= 1;
171 /* Note: does not emit any commands to avoid recursion on
174 void r200FlushCmdBuf( r200ContextPtr rmesa
, const char *caller
)
178 LOCK_HARDWARE( rmesa
);
180 ret
= r200FlushCmdBufLocked( rmesa
, caller
);
182 UNLOCK_HARDWARE( rmesa
);
185 fprintf(stderr
, "drmRadeonCmdBuffer: %d (exiting)\n", ret
);
191 /* =============================================================
192 * Hardware vertex buffer handling
196 void r200RefillCurrentDmaRegion( r200ContextPtr rmesa
)
198 struct r200_dma_buffer
*dmabuf
;
199 int fd
= rmesa
->dri
.fd
;
205 if (R200_DEBUG
& (DEBUG_IOCTL
|DEBUG_DMA
))
206 fprintf(stderr
, "%s\n", __FUNCTION__
);
208 if (rmesa
->dma
.flush
) {
209 rmesa
->dma
.flush( rmesa
);
212 if (rmesa
->dma
.current
.buf
)
213 r200ReleaseDmaRegion( rmesa
, &rmesa
->dma
.current
, __FUNCTION__
);
215 if (rmesa
->dma
.nr_released_bufs
> 4)
216 r200FlushCmdBuf( rmesa
, __FUNCTION__
);
218 dma
.context
= rmesa
->dri
.hwContext
;
220 dma
.send_list
= NULL
;
221 dma
.send_sizes
= NULL
;
223 dma
.request_count
= 1;
224 dma
.request_size
= RADEON_BUFFER_SIZE
;
225 dma
.request_list
= &index
;
226 dma
.request_sizes
= &size
;
227 dma
.granted_count
= 0;
229 LOCK_HARDWARE(rmesa
); /* no need to validate */
232 ret
= drmDMA( fd
, &dma
);
236 if (rmesa
->dma
.nr_released_bufs
) {
237 r200FlushCmdBufLocked( rmesa
, __FUNCTION__
);
240 if (rmesa
->do_usleeps
) {
241 UNLOCK_HARDWARE( rmesa
);
243 LOCK_HARDWARE( rmesa
);
247 UNLOCK_HARDWARE(rmesa
);
249 if (R200_DEBUG
& DEBUG_DMA
)
250 fprintf(stderr
, "Allocated buffer %d\n", index
);
252 dmabuf
= CALLOC_STRUCT( r200_dma_buffer
);
253 dmabuf
->buf
= &rmesa
->r200Screen
->buffers
->list
[index
];
254 dmabuf
->refcount
= 1;
256 rmesa
->dma
.current
.buf
= dmabuf
;
257 rmesa
->dma
.current
.address
= dmabuf
->buf
->address
;
258 rmesa
->dma
.current
.end
= dmabuf
->buf
->total
;
259 rmesa
->dma
.current
.start
= 0;
260 rmesa
->dma
.current
.ptr
= 0;
263 void r200ReleaseDmaRegion( r200ContextPtr rmesa
,
264 struct r200_dma_region
*region
,
267 if (R200_DEBUG
& DEBUG_IOCTL
)
268 fprintf(stderr
, "%s from %s\n", __FUNCTION__
, caller
);
273 if (rmesa
->dma
.flush
)
274 rmesa
->dma
.flush( rmesa
);
276 if (--region
->buf
->refcount
== 0) {
277 drm_radeon_cmd_header_t
*cmd
;
279 if (R200_DEBUG
& (DEBUG_IOCTL
|DEBUG_DMA
))
280 fprintf(stderr
, "%s -- DISCARD BUF %d\n", __FUNCTION__
,
281 region
->buf
->buf
->idx
);
283 cmd
= (drm_radeon_cmd_header_t
*)r200AllocCmdBuf( rmesa
, sizeof(*cmd
),
285 cmd
->dma
.cmd_type
= RADEON_CMD_DMA_DISCARD
;
286 cmd
->dma
.buf_idx
= region
->buf
->buf
->idx
;
288 rmesa
->dma
.nr_released_bufs
++;
295 /* Allocates a region from rmesa->dma.current. If there isn't enough
296 * space in current, grab a new buffer (and discard what was left of current)
298 void r200AllocDmaRegion( r200ContextPtr rmesa
,
299 struct r200_dma_region
*region
,
303 if (R200_DEBUG
& DEBUG_IOCTL
)
304 fprintf(stderr
, "%s %d\n", __FUNCTION__
, bytes
);
306 if (rmesa
->dma
.flush
)
307 rmesa
->dma
.flush( rmesa
);
310 r200ReleaseDmaRegion( rmesa
, region
, __FUNCTION__
);
313 rmesa
->dma
.current
.start
= rmesa
->dma
.current
.ptr
=
314 (rmesa
->dma
.current
.ptr
+ alignment
) & ~alignment
;
316 if ( rmesa
->dma
.current
.ptr
+ bytes
> rmesa
->dma
.current
.end
)
317 r200RefillCurrentDmaRegion( rmesa
);
319 region
->start
= rmesa
->dma
.current
.start
;
320 region
->ptr
= rmesa
->dma
.current
.start
;
321 region
->end
= rmesa
->dma
.current
.start
+ bytes
;
322 region
->address
= rmesa
->dma
.current
.address
;
323 region
->buf
= rmesa
->dma
.current
.buf
;
324 region
->buf
->refcount
++;
326 rmesa
->dma
.current
.ptr
+= bytes
; /* bug - if alignment > 7 */
327 rmesa
->dma
.current
.start
=
328 rmesa
->dma
.current
.ptr
= (rmesa
->dma
.current
.ptr
+ 0x7) & ~0x7;
330 assert( rmesa
->dma
.current
.ptr
<= rmesa
->dma
.current
.end
);
333 void r200AllocDmaRegionVerts( r200ContextPtr rmesa
,
334 struct r200_dma_region
*region
,
339 r200AllocDmaRegion( rmesa
, region
, vertsize
* numverts
, alignment
);
342 /* ================================================================
343 * SwapBuffers with client-side throttling
346 static u_int32_t
r200GetLastFrame(r200ContextPtr rmesa
)
348 drm_radeon_getparam_t gp
;
352 gp
.param
= RADEON_PARAM_LAST_FRAME
;
353 gp
.value
= (int *)&frame
;
354 ret
= drmCommandWriteRead( rmesa
->dri
.fd
, DRM_RADEON_GETPARAM
,
357 fprintf( stderr
, "%s: drmRadeonGetParam: %d\n", __FUNCTION__
, ret
);
364 static void r200EmitIrqLocked( r200ContextPtr rmesa
)
366 drm_radeon_irq_emit_t ie
;
369 ie
.irq_seq
= &rmesa
->iw
.irq_seq
;
370 ret
= drmCommandWriteRead( rmesa
->dri
.fd
, DRM_RADEON_IRQ_EMIT
,
373 fprintf( stderr
, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__
, ret
);
379 static void r200WaitIrq( r200ContextPtr rmesa
)
384 ret
= drmCommandWrite( rmesa
->dri
.fd
, DRM_RADEON_IRQ_WAIT
,
385 &rmesa
->iw
, sizeof(rmesa
->iw
) );
386 } while (ret
&& (errno
== EINTR
|| errno
== EAGAIN
));
389 fprintf( stderr
, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__
, ret
);
395 static void r200WaitForFrameCompletion( r200ContextPtr rmesa
)
397 drm_radeon_sarea_t
*sarea
= rmesa
->sarea
;
399 if (rmesa
->do_irqs
) {
400 if (r200GetLastFrame(rmesa
) < sarea
->last_frame
) {
401 if (!rmesa
->irqsEmitted
) {
402 while (r200GetLastFrame (rmesa
) < sarea
->last_frame
)
406 UNLOCK_HARDWARE( rmesa
);
407 r200WaitIrq( rmesa
);
408 LOCK_HARDWARE( rmesa
);
410 rmesa
->irqsEmitted
= 10;
413 if (rmesa
->irqsEmitted
) {
414 r200EmitIrqLocked( rmesa
);
415 rmesa
->irqsEmitted
--;
419 while (r200GetLastFrame (rmesa
) < sarea
->last_frame
) {
420 UNLOCK_HARDWARE( rmesa
);
421 if (rmesa
->do_usleeps
)
423 LOCK_HARDWARE( rmesa
);
430 /* Copy the back color buffer to the front color buffer.
432 void r200CopyBuffer( const __DRIdrawablePrivate
*dPriv
)
434 r200ContextPtr rmesa
;
436 GLboolean missed_target
;
440 assert(dPriv
->driContextPriv
);
441 assert(dPriv
->driContextPriv
->driverPrivate
);
443 rmesa
= (r200ContextPtr
) dPriv
->driContextPriv
->driverPrivate
;
445 if ( R200_DEBUG
& DEBUG_IOCTL
) {
446 fprintf( stderr
, "\n%s( %p )\n\n", __FUNCTION__
, (void *)rmesa
->glCtx
);
449 R200_FIREVERTICES( rmesa
);
451 LOCK_HARDWARE( rmesa
);
454 /* Throttle the frame rate -- only allow one pending swap buffers
457 r200WaitForFrameCompletion( rmesa
);
458 UNLOCK_HARDWARE( rmesa
);
459 driWaitForVBlank( dPriv
, & rmesa
->vbl_seq
, rmesa
->vblank_flags
, & missed_target
);
460 LOCK_HARDWARE( rmesa
);
462 nbox
= dPriv
->numClipRects
; /* must be in locked region */
464 for ( i
= 0 ; i
< nbox
; ) {
465 GLint nr
= MIN2( i
+ RADEON_NR_SAREA_CLIPRECTS
, nbox
);
466 drm_clip_rect_t
*box
= dPriv
->pClipRects
;
467 drm_clip_rect_t
*b
= rmesa
->sarea
->boxes
;
470 for ( ; i
< nr
; i
++ ) {
474 rmesa
->sarea
->nbox
= n
;
476 ret
= drmCommandNone( rmesa
->dri
.fd
, DRM_RADEON_SWAP
);
479 fprintf( stderr
, "DRM_R200_SWAP_BUFFERS: return = %d\n", ret
);
480 UNLOCK_HARDWARE( rmesa
);
485 UNLOCK_HARDWARE( rmesa
);
486 rmesa
->hw
.all_dirty
= GL_TRUE
;
489 (*rmesa
->get_ust
)( & ust
);
490 if ( missed_target
) {
491 rmesa
->swap_missed_count
++;
492 rmesa
->swap_missed_ust
= ust
- rmesa
->swap_ust
;
495 rmesa
->swap_ust
= ust
;
500 void r200PageFlip( const __DRIdrawablePrivate
*dPriv
)
502 r200ContextPtr rmesa
;
504 GLboolean missed_target
;
507 assert(dPriv
->driContextPriv
);
508 assert(dPriv
->driContextPriv
->driverPrivate
);
510 rmesa
= (r200ContextPtr
) dPriv
->driContextPriv
->driverPrivate
;
512 if ( R200_DEBUG
& DEBUG_IOCTL
) {
513 fprintf(stderr
, "%s: pfCurrentPage: %d\n", __FUNCTION__
,
514 rmesa
->sarea
->pfCurrentPage
);
517 R200_FIREVERTICES( rmesa
);
518 LOCK_HARDWARE( rmesa
);
520 if (!dPriv
->numClipRects
) {
521 UNLOCK_HARDWARE( rmesa
);
522 usleep( 10000 ); /* throttle invisible client 10ms */
526 /* Need to do this for the perf box placement:
529 drm_clip_rect_t
*box
= dPriv
->pClipRects
;
530 drm_clip_rect_t
*b
= rmesa
->sarea
->boxes
;
532 rmesa
->sarea
->nbox
= 1;
535 /* Throttle the frame rate -- only allow a few pending swap buffers
538 r200WaitForFrameCompletion( rmesa
);
539 UNLOCK_HARDWARE( rmesa
);
540 driWaitForVBlank( dPriv
, & rmesa
->vbl_seq
, rmesa
->vblank_flags
, & missed_target
);
541 if ( missed_target
) {
542 rmesa
->swap_missed_count
++;
543 (void) (*rmesa
->get_ust
)( & rmesa
->swap_missed_ust
);
545 LOCK_HARDWARE( rmesa
);
547 ret
= drmCommandNone( rmesa
->dri
.fd
, DRM_RADEON_FLIP
);
549 UNLOCK_HARDWARE( rmesa
);
552 fprintf( stderr
, "DRM_RADEON_FLIP: return = %d\n", ret
);
557 (void) (*rmesa
->get_ust
)( & rmesa
->swap_ust
);
559 if ( rmesa
->sarea
->pfCurrentPage
== 1 ) {
560 rmesa
->state
.color
.drawOffset
= rmesa
->r200Screen
->frontOffset
;
561 rmesa
->state
.color
.drawPitch
= rmesa
->r200Screen
->frontPitch
;
563 rmesa
->state
.color
.drawOffset
= rmesa
->r200Screen
->backOffset
;
564 rmesa
->state
.color
.drawPitch
= rmesa
->r200Screen
->backPitch
;
567 R200_STATECHANGE( rmesa
, ctx
);
568 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = rmesa
->state
.color
.drawOffset
569 + rmesa
->r200Screen
->fbLocation
;
570 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = rmesa
->state
.color
.drawPitch
;
571 if (rmesa
->sarea
->tiling_enabled
) {
572 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] |= R200_COLOR_TILE_ENABLE
;
577 /* ================================================================
580 static void r200Clear( GLcontext
*ctx
, GLbitfield mask
, GLboolean all
,
581 GLint cx
, GLint cy
, GLint cw
, GLint ch
)
583 r200ContextPtr rmesa
= R200_CONTEXT(ctx
);
584 __DRIdrawablePrivate
*dPriv
= rmesa
->dri
.drawable
;
586 GLuint color_mask
= 0;
589 if ( R200_DEBUG
& DEBUG_IOCTL
) {
590 fprintf( stderr
, "%s: all=%d cx=%d cy=%d cw=%d ch=%d\n",
591 __FUNCTION__
, all
, cx
, cy
, cw
, ch
);
595 LOCK_HARDWARE( rmesa
);
596 UNLOCK_HARDWARE( rmesa
);
597 if ( dPriv
->numClipRects
== 0 )
603 if ( mask
& DD_FRONT_LEFT_BIT
) {
604 flags
|= RADEON_FRONT
;
605 color_mask
= rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
];
606 mask
&= ~DD_FRONT_LEFT_BIT
;
609 if ( mask
& DD_BACK_LEFT_BIT
) {
610 flags
|= RADEON_BACK
;
611 color_mask
= rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
];
612 mask
&= ~DD_BACK_LEFT_BIT
;
615 if ( mask
& DD_DEPTH_BIT
) {
616 flags
|= RADEON_DEPTH
;
617 mask
&= ~DD_DEPTH_BIT
;
620 if ( (mask
& DD_STENCIL_BIT
) && rmesa
->state
.stencil
.hwBuffer
) {
621 flags
|= RADEON_STENCIL
;
622 mask
&= ~DD_STENCIL_BIT
;
626 if (R200_DEBUG
& DEBUG_FALLBACKS
)
627 fprintf(stderr
, "%s: swrast clear, mask: %x\n", __FUNCTION__
, mask
);
628 _swrast_Clear( ctx
, mask
, all
, cx
, cy
, cw
, ch
);
634 if (rmesa
->using_hyperz
) {
635 flags
|= RADEON_USE_COMP_ZBUF
;
636 /* if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200)
637 flags |= RADEON_USE_HIERZ; */
638 if (!(rmesa
->state
.stencil
.hwBuffer
) ||
639 ((flags
& RADEON_DEPTH
) && (flags
& RADEON_STENCIL
) &&
640 ((rmesa
->state
.stencil
.clear
& R200_STENCIL_WRITE_MASK
) == R200_STENCIL_WRITE_MASK
))) {
641 flags
|= RADEON_CLEAR_FASTZ
;
645 /* Flip top to bottom */
647 cy
= dPriv
->y
+ dPriv
->h
- cy
- ch
;
649 LOCK_HARDWARE( rmesa
);
651 /* Throttle the number of clear ioctls we do.
654 drm_radeon_getparam_t gp
;
658 gp
.param
= RADEON_PARAM_LAST_CLEAR
;
659 gp
.value
= (int *)&clear
;
660 ret
= drmCommandWriteRead( rmesa
->dri
.fd
,
661 DRM_RADEON_GETPARAM
, &gp
, sizeof(gp
) );
664 fprintf( stderr
, "%s: drmRadeonGetParam: %d\n", __FUNCTION__
, ret
);
668 /* Clear throttling needs more thought.
670 if ( rmesa
->sarea
->last_clear
- clear
<= 25 ) {
674 if (rmesa
->do_usleeps
) {
675 UNLOCK_HARDWARE( rmesa
);
677 LOCK_HARDWARE( rmesa
);
681 /* Send current state to the hardware */
682 r200FlushCmdBufLocked( rmesa
, __FUNCTION__
);
684 for ( i
= 0 ; i
< dPriv
->numClipRects
; ) {
685 GLint nr
= MIN2( i
+ RADEON_NR_SAREA_CLIPRECTS
, dPriv
->numClipRects
);
686 drm_clip_rect_t
*box
= dPriv
->pClipRects
;
687 drm_clip_rect_t
*b
= rmesa
->sarea
->boxes
;
688 drm_radeon_clear_t clear
;
689 drm_radeon_clear_rect_t depth_boxes
[RADEON_NR_SAREA_CLIPRECTS
];
693 for ( ; i
< nr
; i
++ ) {
696 GLint w
= box
[i
].x2
- x
;
697 GLint h
= box
[i
].y2
- y
;
699 if ( x
< cx
) w
-= cx
- x
, x
= cx
;
700 if ( y
< cy
) h
-= cy
- y
, y
= cy
;
701 if ( x
+ w
> cx
+ cw
) w
= cx
+ cw
- x
;
702 if ( y
+ h
> cy
+ ch
) h
= cy
+ ch
- y
;
703 if ( w
<= 0 ) continue;
704 if ( h
<= 0 ) continue;
714 for ( ; i
< nr
; i
++ ) {
720 rmesa
->sarea
->nbox
= n
;
723 clear
.clear_color
= rmesa
->state
.color
.clear
;
724 clear
.clear_depth
= rmesa
->state
.depth
.clear
; /* needed for hyperz */
725 clear
.color_mask
= rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
];
726 clear
.depth_mask
= rmesa
->state
.stencil
.clear
;
727 clear
.depth_boxes
= depth_boxes
;
730 b
= rmesa
->sarea
->boxes
;
731 for ( ; n
>= 0 ; n
-- ) {
732 depth_boxes
[n
].f
[CLEAR_X1
] = (float)b
[n
].x1
;
733 depth_boxes
[n
].f
[CLEAR_Y1
] = (float)b
[n
].y1
;
734 depth_boxes
[n
].f
[CLEAR_X2
] = (float)b
[n
].x2
;
735 depth_boxes
[n
].f
[CLEAR_Y2
] = (float)b
[n
].y2
;
736 depth_boxes
[n
].f
[CLEAR_DEPTH
] = ctx
->Depth
.Clear
;
739 ret
= drmCommandWrite( rmesa
->dri
.fd
, DRM_RADEON_CLEAR
,
740 &clear
, sizeof(clear
));
744 UNLOCK_HARDWARE( rmesa
);
745 fprintf( stderr
, "DRM_RADEON_CLEAR: return = %d\n", ret
);
750 UNLOCK_HARDWARE( rmesa
);
751 rmesa
->hw
.all_dirty
= GL_TRUE
;
755 void r200WaitForIdleLocked( r200ContextPtr rmesa
)
761 ret
= drmCommandNone( rmesa
->dri
.fd
, DRM_RADEON_CP_IDLE
);
764 } while (ret
&& ++i
< 100);
767 UNLOCK_HARDWARE( rmesa
);
768 fprintf( stderr
, "Error: R200 timed out... exiting\n" );
774 static void r200WaitForIdle( r200ContextPtr rmesa
)
776 LOCK_HARDWARE(rmesa
);
777 r200WaitForIdleLocked( rmesa
);
778 UNLOCK_HARDWARE(rmesa
);
782 void r200Flush( GLcontext
*ctx
)
784 r200ContextPtr rmesa
= R200_CONTEXT( ctx
);
786 if (R200_DEBUG
& DEBUG_IOCTL
)
787 fprintf(stderr
, "%s\n", __FUNCTION__
);
789 if (rmesa
->dma
.flush
)
790 rmesa
->dma
.flush( rmesa
);
792 r200EmitState( rmesa
);
794 if (rmesa
->store
.cmd_used
)
795 r200FlushCmdBuf( rmesa
, __FUNCTION__
);
798 /* Make sure all commands have been sent to the hardware and have
799 * completed processing.
801 void r200Finish( GLcontext
*ctx
)
803 r200ContextPtr rmesa
= R200_CONTEXT(ctx
);
806 if (rmesa
->do_irqs
) {
807 LOCK_HARDWARE( rmesa
);
808 r200EmitIrqLocked( rmesa
);
809 UNLOCK_HARDWARE( rmesa
);
810 r200WaitIrq( rmesa
);
813 r200WaitForIdle( rmesa
);
817 /* This version of AllocateMemoryMESA allocates only GART memory, and
818 * only does so after the point at which the driver has been
821 * Theoretically a valid context isn't required. However, in this
822 * implementation, it is, as I'm using the hardware lock to protect
823 * the kernel data structures, and the current context to get the
826 void *r200AllocateMemoryMESA(__DRInativeDisplay
*dpy
, int scrn
, GLsizei size
,
827 GLfloat readfreq
, GLfloat writefreq
,
830 GET_CURRENT_CONTEXT(ctx
);
831 r200ContextPtr rmesa
;
833 drm_radeon_mem_alloc_t alloc
;
836 if (R200_DEBUG
& DEBUG_IOCTL
)
837 fprintf(stderr
, "%s sz %d %f/%f/%f\n", __FUNCTION__
, size
, readfreq
,
838 writefreq
, priority
);
840 if (!ctx
|| !(rmesa
= R200_CONTEXT(ctx
)) || !rmesa
->r200Screen
->gartTextures
.map
)
843 if (getenv("R200_NO_ALLOC"))
846 if (rmesa
->dri
.drmMinor
< 6)
849 alloc
.region
= RADEON_MEM_REGION_GART
;
852 alloc
.region_offset
= ®ion_offset
;
854 ret
= drmCommandWriteRead( rmesa
->r200Screen
->driScreen
->fd
,
856 &alloc
, sizeof(alloc
));
859 fprintf(stderr
, "%s: DRM_RADEON_ALLOC ret %d\n", __FUNCTION__
, ret
);
864 char *region_start
= (char *)rmesa
->r200Screen
->gartTextures
.map
;
865 return (void *)(region_start
+ region_offset
);
870 /* Called via glXFreeMemoryMESA() */
871 void r200FreeMemoryMESA(__DRInativeDisplay
*dpy
, int scrn
, GLvoid
*pointer
)
873 GET_CURRENT_CONTEXT(ctx
);
874 r200ContextPtr rmesa
;
875 ptrdiff_t region_offset
;
876 drm_radeon_mem_free_t memfree
;
879 if (R200_DEBUG
& DEBUG_IOCTL
)
880 fprintf(stderr
, "%s %p\n", __FUNCTION__
, pointer
);
882 if (!ctx
|| !(rmesa
= R200_CONTEXT(ctx
)) || !rmesa
->r200Screen
->gartTextures
.map
) {
883 fprintf(stderr
, "%s: no context\n", __FUNCTION__
);
887 if (rmesa
->dri
.drmMinor
< 6)
890 region_offset
= (char *)pointer
- (char *)rmesa
->r200Screen
->gartTextures
.map
;
892 if (region_offset
< 0 ||
893 region_offset
> rmesa
->r200Screen
->gartTextures
.size
) {
894 fprintf(stderr
, "offset %d outside range 0..%d\n", region_offset
,
895 rmesa
->r200Screen
->gartTextures
.size
);
899 memfree
.region
= RADEON_MEM_REGION_GART
;
900 memfree
.region_offset
= region_offset
;
902 ret
= drmCommandWrite( rmesa
->r200Screen
->driScreen
->fd
,
904 &memfree
, sizeof(memfree
));
907 fprintf(stderr
, "%s: DRM_RADEON_FREE ret %d\n", __FUNCTION__
, ret
);
910 /* Called via glXGetMemoryOffsetMESA() */
911 GLuint
r200GetMemoryOffsetMESA(__DRInativeDisplay
*dpy
, int scrn
, const GLvoid
*pointer
)
913 GET_CURRENT_CONTEXT(ctx
);
914 r200ContextPtr rmesa
;
917 if (!ctx
|| !(rmesa
= R200_CONTEXT(ctx
)) ) {
918 fprintf(stderr
, "%s: no context\n", __FUNCTION__
);
922 if (!r200IsGartMemory( rmesa
, pointer
, 0 ))
925 if (rmesa
->dri
.drmMinor
< 6)
928 card_offset
= r200GartOffsetFromVirtual( rmesa
, pointer
);
930 return card_offset
- rmesa
->r200Screen
->gart_base
;
933 GLboolean
r200IsGartMemory( r200ContextPtr rmesa
, const GLvoid
*pointer
,
936 ptrdiff_t offset
= (char *)pointer
- (char *)rmesa
->r200Screen
->gartTextures
.map
;
937 int valid
= (size
>= 0 &&
939 offset
+ size
< rmesa
->r200Screen
->gartTextures
.size
);
941 if (R200_DEBUG
& DEBUG_IOCTL
)
942 fprintf(stderr
, "r200IsGartMemory( %p ) : %d\n", pointer
, valid
);
948 GLuint
r200GartOffsetFromVirtual( r200ContextPtr rmesa
, const GLvoid
*pointer
)
950 ptrdiff_t offset
= (char *)pointer
- (char *)rmesa
->r200Screen
->gartTextures
.map
;
952 if (offset
< 0 || offset
> rmesa
->r200Screen
->gartTextures
.size
)
955 return rmesa
->r200Screen
->gart_texture_offset
+ offset
;
960 void r200InitIoctlFuncs( struct dd_function_table
*functions
)
962 functions
->Clear
= r200Clear
;
963 functions
->Finish
= r200Finish
;
964 functions
->Flush
= r200Flush
;