src/mesa/drivers/dri/r200/r200_ioctl.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #ifndef __R200_IOCTL_H__
  36 #define __R200_IOCTL_H__
  37
  38 #include "main/simple_list.h"
  39 #include "radeon_dri.h"
  40 #include "r200_lock.h"
  41
  42 #include "radeon_cs_legacy.h"
  43
  44 #include "xf86drm.h"
  45 #include "drm.h"
  46 #include "radeon_drm.h"
  47
  48 #include "common_cmdbuf.h"
  49
  50 extern void r200EmitState( r200ContextPtr rmesa );
  51 extern void r200EmitVertexAOS( r200ContextPtr rmesa,
  52                                GLuint vertex_size,
  53                                struct radeon_bo *bo,
  54                                GLuint offset );
  55
  56 extern void r200EmitVbufPrim( r200ContextPtr rmesa,
  57                                 GLuint primitive,
  58                                 GLuint vertex_nr );
  59
  60 extern void r200FlushElts(GLcontext *ctx);
  61
  62 extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
  63                                            GLuint primitive,
  64                                            GLuint min_nr );
  65
  66 extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset);
  67
  68 extern void r200Flush( GLcontext *ctx );
  69 extern void r200Finish( GLcontext *ctx );
  70 extern void r200InitIoctlFuncs( struct dd_function_table *functions );
  71
  72 extern void *r200AllocateMemoryMESA( __DRIscreen *screen, GLsizei size, GLfloat readfreq,
  73                                    GLfloat writefreq, GLfloat priority );
  74 extern void r200FreeMemoryMESA( __DRIscreen *screen, GLvoid *pointer );
  75 extern GLuint r200GetMemoryOffsetMESA( __DRIscreen *screen, const GLvoid *pointer );
  76
  77 extern GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer,
  78                                    GLint size );
  79
  80 extern GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa,
  81                                          const GLvoid *pointer );
  82
  83 void r200SetUpAtomList( r200ContextPtr rmesa );
  84
  85 /* ================================================================
  86  * Helper macros:
  87  */
  88
  89 /* Close off the last primitive, if it exists.
  90  */
  91 #define R200_NEWPRIM( rmesa )                   \
  92 do {                                            \
  93    if ( rmesa->radeon.dma.flush )                       \
  94       rmesa->radeon.dma.flush( rmesa->radeon.glCtx );   \
  95 } while (0)
  96
  97 /* Can accomodate several state changes and primitive changes without
  98  * actually firing the buffer.
  99  */
 100 #define R200_STATECHANGE( rmesa, ATOM )                 \
 101 do {                                                            \
 102    R200_NEWPRIM( rmesa );                                       \
 103    rmesa->hw.ATOM.dirty = GL_TRUE;                              \
 104    rmesa->hw.is_dirty = GL_TRUE;                                \
 105 } while (0)
 106
 107 #define R200_DB_STATE( ATOM )                           \
 108    memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd,  \
 109            rmesa->hw.ATOM.cmd_size * 4)
 110
 111 static INLINE int R200_DB_STATECHANGE(
 112    r200ContextPtr rmesa,
 113    struct radeon_state_atom *atom )
 114 {
 115    if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) {
 116       GLuint *tmp;
 117       R200_NEWPRIM( rmesa );
 118       atom->dirty = GL_TRUE;
 119       rmesa->hw.is_dirty = GL_TRUE;
 120       tmp = atom->cmd;
 121       atom->cmd = atom->lastcmd;
 122       atom->lastcmd = tmp;
 123       return 1;
 124    }
 125    else
 126       return 0;
 127 }
 128
 129
 130 /* Fire the buffered vertices no matter what.
 131  */
 132 #define R200_FIREVERTICES( rmesa )                      \
 133 do {                                                    \
 134    if ( rmesa->radeon.cmdbuf.cs->cdw || rmesa->radeon.dma.flush ) {     \
 135       r200Flush( rmesa->radeon.glCtx );                 \
 136    }                                                    \
 137 } while (0)
 138
 139 /* Command lengths.  Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ
 140  * are available, you will also be adding an rmesa->state.max_state_size because
 141  * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts.
 142  */
 143 #define AOS_BUFSZ(nr)   ((3 + ((nr / 2) * 3) + ((nr & 1) * 2)) * sizeof(int))
 144 #define VERT_AOS_BUFSZ  (5 * sizeof(int))
 145 #define ELTS_BUFSZ(nr)  (12 + nr * 2)
 146 #define VBUF_BUFSZ      (3 * sizeof(int))
 147
 148 static inline uint32_t cmdpacket3(int cmd_type)
 149 {
 150   drm_radeon_cmd_header_t cmd;
 151
 152   cmd.i = 0;
 153   cmd.header.cmd_type = cmd_type;
 154
 155   return (uint32_t)cmd.i;
 156
 157 }
 158
 159 #define OUT_BATCH_PACKET3(packet, num_extra) do {             \
 160     if (!b_l_rmesa->radeonScreen->kernel_mm) {                \
 161       OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3));                                      \
 162       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 163     } else {                                                  \
 164       OUT_BATCH(CP_PACKET2);                                  \
 165       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 166     }                                                         \
 167   } while(0)
 168
 169 #define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do {        \
 170     if (!b_l_rmesa->radeonScreen->kernel_mm) {                \
 171       OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3_CLIP));         \
 172       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 173     } else {                                                  \
 174       OUT_BATCH(CP_PACKET2);                                  \
 175       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 176     }                                                         \
 177   } while(0)
 178
 179
 180 #endif /* __R200_IOCTL_H__ */