src/mesa/drivers/dri/r200/r200_ioctl.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #ifndef __R200_IOCTL_H__
  36 #define __R200_IOCTL_H__
  37
  38 #include "main/simple_list.h"
  39 #include "radeon_dri.h"
  40 #include "r200_lock.h"
  41
  42 #include "radeon_cs_legacy.h"
  43
  44 #include "xf86drm.h"
  45 #include "drm.h"
  46 #include "radeon_drm.h"
  47
  48 #include "common_cmdbuf.h"
  49
  50 extern void r200EmitVertexAOS( r200ContextPtr rmesa,
  51                                GLuint vertex_size,
  52                                struct radeon_bo *bo,
  53                                GLuint offset );
  54
  55 extern void r200EmitVbufPrim( r200ContextPtr rmesa,
  56                                 GLuint primitive,
  57                                 GLuint vertex_nr );
  58
  59 extern void r200FlushElts(GLcontext *ctx);
  60
  61 extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
  62                                            GLuint primitive,
  63                                            GLuint min_nr );
  64
  65 extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset);
  66
  67 extern void r200Flush( GLcontext *ctx );
  68 extern void r200Finish( GLcontext *ctx );
  69 extern void r200InitIoctlFuncs( struct dd_function_table *functions );
  70
  71 extern void *r200AllocateMemoryMESA( __DRIscreen *screen, GLsizei size, GLfloat readfreq,
  72                                    GLfloat writefreq, GLfloat priority );
  73 extern void r200FreeMemoryMESA( __DRIscreen *screen, GLvoid *pointer );
  74 extern GLuint r200GetMemoryOffsetMESA( __DRIscreen *screen, const GLvoid *pointer );
  75
  76 extern GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer,
  77                                    GLint size );
  78
  79 extern GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa,
  80                                          const GLvoid *pointer );
  81
  82 void r200SetUpAtomList( r200ContextPtr rmesa );
  83
  84 /* ================================================================
  85  * Helper macros:
  86  */
  87
  88 /* Close off the last primitive, if it exists.
  89  */
  90 #define R200_NEWPRIM( rmesa )                   \
  91 do {                                            \
  92    if ( rmesa->radeon.dma.flush )                       \
  93       rmesa->radeon.dma.flush( rmesa->radeon.glCtx );   \
  94 } while (0)
  95
  96 /* Can accomodate several state changes and primitive changes without
  97  * actually firing the buffer.
  98  */
  99 #define R200_STATECHANGE( rmesa, ATOM )                 \
 100 do {                                                            \
 101    R200_NEWPRIM( rmesa );                                       \
 102    rmesa->hw.ATOM.dirty = GL_TRUE;                              \
 103    rmesa->radeon.hw.is_dirty = GL_TRUE;                         \
 104 } while (0)
 105
 106 #define R200_DB_STATE( ATOM )                           \
 107    memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd,  \
 108            rmesa->hw.ATOM.cmd_size * 4)
 109
 110 static INLINE int R200_DB_STATECHANGE(
 111    r200ContextPtr rmesa,
 112    struct radeon_state_atom *atom )
 113 {
 114    if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) {
 115       GLuint *tmp;
 116       R200_NEWPRIM( rmesa );
 117       atom->dirty = GL_TRUE;
 118       rmesa->radeon.hw.is_dirty = GL_TRUE;
 119       tmp = atom->cmd;
 120       atom->cmd = atom->lastcmd;
 121       atom->lastcmd = tmp;
 122       return 1;
 123    }
 124    else
 125       return 0;
 126 }
 127
 128
 129 /* Command lengths.  Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ
 130  * are available, you will also be adding an rmesa->state.max_state_size because
 131  * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts.
 132  */
 133 #define AOS_BUFSZ(nr)   ((3 + ((nr / 2) * 3) + ((nr & 1) * 2)) * sizeof(int))
 134 #define VERT_AOS_BUFSZ  (5 * sizeof(int))
 135 #define ELTS_BUFSZ(nr)  (12 + nr * 2)
 136 #define VBUF_BUFSZ      (3 * sizeof(int))
 137
 138 static inline uint32_t cmdpacket3(int cmd_type)
 139 {
 140   drm_radeon_cmd_header_t cmd;
 141
 142   cmd.i = 0;
 143   cmd.header.cmd_type = cmd_type;
 144
 145   return (uint32_t)cmd.i;
 146
 147 }
 148
 149 #define OUT_BATCH_PACKET3(packet, num_extra) do {             \
 150     if (!b_l_rmesa->radeonScreen->kernel_mm) {                \
 151       OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3));                                      \
 152       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 153     } else {                                                  \
 154       OUT_BATCH(CP_PACKET2);                                  \
 155       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 156     }                                                         \
 157   } while(0)
 158
 159 #define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do {        \
 160     if (!b_l_rmesa->radeonScreen->kernel_mm) {                \
 161       OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3_CLIP));         \
 162       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 163     } else {                                                  \
 164       OUT_BATCH(CP_PACKET2);                                  \
 165       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 166     }                                                         \
 167   } while(0)
 168
 169
 170 #endif /* __R200_IOCTL_H__ */