src/mesa/drivers/dri/r200/r200_ioctl.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #ifndef __R200_IOCTL_H__
  36 #define __R200_IOCTL_H__
  37
  38 #include "main/simple_list.h"
  39 #include "radeon_dri.h"
  40
  41 #include "radeon_bocs_wrapper.h"
  42
  43 #include "xf86drm.h"
  44 #include "drm.h"
  45 #include "radeon_drm.h"
  46
  47 extern void r200EmitMaxVtxIndex(r200ContextPtr rmesa, int count);
  48 extern void r200EmitVertexAOS( r200ContextPtr rmesa,
  49                                GLuint vertex_size,
  50                                struct radeon_bo *bo,
  51                                GLuint offset );
  52
  53 extern void r200EmitVbufPrim( r200ContextPtr rmesa,
  54                                 GLuint primitive,
  55                                 GLuint vertex_nr );
  56
  57 extern void r200FlushElts(GLcontext *ctx);
  58
  59 extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
  60                                            GLuint primitive,
  61                                            GLuint min_nr );
  62
  63 extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset);
  64
  65 extern void r200InitIoctlFuncs( struct dd_function_table *functions );
  66
  67 extern void *r200AllocateMemoryMESA( __DRIscreen *screen, GLsizei size, GLfloat readfreq,
  68                                    GLfloat writefreq, GLfloat priority );
  69 extern void r200FreeMemoryMESA( __DRIscreen *screen, GLvoid *pointer );
  70 extern GLuint r200GetMemoryOffsetMESA( __DRIscreen *screen, const GLvoid *pointer );
  71
  72 extern GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer,
  73                                    GLint size );
  74
  75 extern GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa,
  76                                          const GLvoid *pointer );
  77
  78 void r200SetUpAtomList( r200ContextPtr rmesa );
  79
  80 /* ================================================================
  81  * Helper macros:
  82  */
  83
  84 /* Close off the last primitive, if it exists.
  85  */
  86 #define R200_NEWPRIM( rmesa )                   \
  87 do {                                            \
  88    if ( rmesa->radeon.dma.flush )                       \
  89       rmesa->radeon.dma.flush( rmesa->radeon.glCtx );   \
  90 } while (0)
  91
  92 /* Can accomodate several state changes and primitive changes without
  93  * actually firing the buffer.
  94  */
  95 #define R200_STATECHANGE( rmesa, ATOM )                 \
  96 do {                                                            \
  97    R200_NEWPRIM( rmesa );                                       \
  98    rmesa->hw.ATOM.dirty = GL_TRUE;                              \
  99    rmesa->radeon.hw.is_dirty = GL_TRUE;                         \
 100 } while (0)
 101
 102 #define R200_SET_STATE( rmesa, ATOM, index, newvalue )  \
 103   do {  \
 104     uint32_t __index = (index); \
 105     uint32_t __dword = (newvalue); \
 106     if (__dword != (rmesa)->hw.ATOM.cmd[__index]) { \
 107       R200_STATECHANGE( (rmesa), ATOM ); \
 108       (rmesa)->hw.ATOM.cmd[__index] = __dword; \
 109     } \
 110   } while(0)
 111
 112 #define R200_DB_STATE( ATOM )                           \
 113    memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd,  \
 114            rmesa->hw.ATOM.cmd_size * 4)
 115
 116 static INLINE int R200_DB_STATECHANGE(
 117    r200ContextPtr rmesa,
 118    struct radeon_state_atom *atom )
 119 {
 120    if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) {
 121       GLuint *tmp;
 122       R200_NEWPRIM( rmesa );
 123       atom->dirty = GL_TRUE;
 124       rmesa->radeon.hw.is_dirty = GL_TRUE;
 125       tmp = atom->cmd;
 126       atom->cmd = atom->lastcmd;
 127       atom->lastcmd = tmp;
 128       return 1;
 129    }
 130    else
 131       return 0;
 132 }
 133
 134
 135 /* Command lengths.  Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ
 136  * are available, you will also be adding an rmesa->state.max_state_size because
 137  * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts.
 138  */
 139 #define AOS_BUFSZ(nr)   ((3 + ((nr / 2) * 3) + ((nr & 1) * 2) + nr*2))
 140 #define VERT_AOS_BUFSZ  (5)
 141 #define ELTS_BUFSZ(nr)  (12 + nr * 2)
 142 #define VBUF_BUFSZ      (3)
 143 #define SCISSOR_BUFSZ   (8)
 144 #define INDEX_BUFSZ     (8+2)
 145
 146 static inline uint32_t cmdpacket3(int cmd_type)
 147 {
 148   drm_radeon_cmd_header_t cmd;
 149
 150   cmd.i = 0;
 151   cmd.header.cmd_type = cmd_type;
 152
 153   return (uint32_t)cmd.i;
 154
 155 }
 156
 157 #define OUT_BATCH_PACKET3(packet, num_extra) do {             \
 158     if (!b_l_rmesa->radeonScreen->kernel_mm) {                \
 159       OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3));                                      \
 160       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 161     } else {                                                  \
 162       OUT_BATCH(CP_PACKET2);                                  \
 163       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 164     }                                                         \
 165   } while(0)
 166
 167 #define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do {        \
 168     if (!b_l_rmesa->radeonScreen->kernel_mm) {                \
 169       OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3_CLIP));         \
 170       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 171     } else {                                                  \
 172       OUT_BATCH(CP_PACKET2);                                  \
 173       OUT_BATCH(CP_PACKET3((packet), (num_extra)));           \
 174     }                                                         \
 175   } while(0)
 176
 177
 178 #endif /* __R200_IOCTL_H__ */