src/mesa/drivers/dri/r200/r200_sanity.c

   1 /* $XFree86$ */
   2 /**************************************************************************
   3
   4 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
   5                      Tungsten Graphics Inc, Cedar Park, TX.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining a
  10 copy of this software and associated documentation files (the "Software"),
  11 to deal in the Software without restriction, including without limitation
  12 on the rights to use, copy, modify, merge, publish, distribute, sub
  13 license, and/or sell copies of the Software, and to permit persons to whom
  14 the Software is furnished to do so, subject to the following conditions:
  15
  16 The above copyright notice and this permission notice (including the next
  17 paragraph) shall be included in all copies or substantial portions of the
  18 Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  23 ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  24 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  25 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  26 USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *
  34  */
  35 #include <errno.h>
  36
  37 #include "glheader.h"
  38 #include "imports.h"
  39
  40 #include "r200_context.h"
  41 #include "r200_ioctl.h"
  42 #include "r200_sanity.h"
  43 #include "radeon_reg.h"
  44 #include "r200_reg.h"
  45
  46 /* Set this '1' to get more verbiage.
  47  */
  48 #define MORE_VERBOSE 1
  49
  50 #if MORE_VERBOSE
  51 #define VERBOSE (R200_DEBUG & DEBUG_VERBOSE)
  52 #define NORMAL  (1)
  53 #else
  54 #define VERBOSE 0
  55 #define NORMAL  (R200_DEBUG & DEBUG_VERBOSE)
  56 #endif
  57
  58
  59 /* New (1.3) state mechanism.  3 commands (packet, scalar, vector) in
  60  * 1.3 cmdbuffers allow all previous state to be updated as well as
  61  * the tcl scalar and vector areas.
  62  */
  63 static struct {
  64    int start;
  65    int len;
  66    const char *name;
  67 } packet[RADEON_MAX_STATE_PACKETS] = {
  68    { RADEON_PP_MISC,7,"RADEON_PP_MISC" },
  69    { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
  70    { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
  71    { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
  72    { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
  73    { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
  74    { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
  75    { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
  76    { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
  77    { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
  78    { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
  79    { RADEON_RE_MISC,1,"RADEON_RE_MISC" },
  80    { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
  81    { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
  82    { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
  83    { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
  84    { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
  85    { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
  86    { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
  87    { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
  88    { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
  89    { R200_PP_TXCBLEND_0, 4, "R200_EMIT_PP_TXCBLEND_0" },
  90    { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" },
  91    { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" },
  92    { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" },
  93    { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" },
  94    { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" },
  95    { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" },
  96    { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" },
  97    { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
  98    { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" },
  99    { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" },
 100    { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" },
 101    { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" },
 102    { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
 103    { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
 104    { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" },
 105    { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" },
 106    { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" },
 107    { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" },
 108    { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" },
 109    { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" },
 110    { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" },
 111    { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" },
 112    { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" },
 113    { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" },
 114    { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" },
 115    { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" },
 116    { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" },
 117    { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
 118    { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" },
 119    { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" },
 120    { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" },
 121    { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" },
 122    { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" },
 123    { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" },
 124    { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" },
 125    { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" },
 126    { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" },
 127    { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" },
 128    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
 129    { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */
 130    { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */
 131    { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" },
 132    { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" },
 133    { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" },
 134    { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" },
 135    { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" },
 136    { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" },
 137    { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" },
 138    { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
 139    { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
 140    { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
 141 };
 142
 143 struct reg_names {
 144    int idx;
 145    const char *name;
 146 };
 147
 148 static struct reg_names reg_names[] = {
 149    { R200_PP_MISC, "R200_PP_MISC" },
 150    { R200_PP_FOG_COLOR, "R200_PP_FOG_COLOR" },
 151    { R200_RE_SOLID_COLOR, "R200_RE_SOLID_COLOR" },
 152    { R200_RB3D_BLENDCNTL, "R200_RB3D_BLENDCNTL" },
 153    { R200_RB3D_DEPTHOFFSET, "R200_RB3D_DEPTHOFFSET" },
 154    { R200_RB3D_DEPTHPITCH, "R200_RB3D_DEPTHPITCH" },
 155    { R200_RB3D_ZSTENCILCNTL, "R200_RB3D_ZSTENCILCNTL" },
 156    { R200_PP_CNTL, "R200_PP_CNTL" },
 157    { R200_RB3D_CNTL, "R200_RB3D_CNTL" },
 158    { R200_RB3D_COLOROFFSET, "R200_RB3D_COLOROFFSET" },
 159    { R200_RE_WIDTH_HEIGHT, "R200_RE_WIDTH_HEIGHT" },
 160    { R200_RB3D_COLORPITCH, "R200_RB3D_COLORPITCH" },
 161    { R200_SE_CNTL, "R200_SE_CNTL" },
 162    { R200_RE_CNTL, "R200_RE_CNTL" },
 163    { R200_RE_MISC, "R200_RE_MISC" },
 164    { R200_RE_STIPPLE_ADDR, "R200_RE_STIPPLE_ADDR" },
 165    { R200_RE_STIPPLE_DATA, "R200_RE_STIPPLE_DATA" },
 166    { R200_RE_LINE_PATTERN, "R200_RE_LINE_PATTERN" },
 167    { R200_RE_LINE_STATE, "R200_RE_LINE_STATE" },
 168    { R200_RE_SCISSOR_TL_0, "R200_RE_SCISSOR_TL_0" },
 169    { R200_RE_SCISSOR_BR_0, "R200_RE_SCISSOR_BR_0" },
 170    { R200_RE_SCISSOR_TL_1, "R200_RE_SCISSOR_TL_1" },
 171    { R200_RE_SCISSOR_BR_1, "R200_RE_SCISSOR_BR_1" },
 172    { R200_RE_SCISSOR_TL_2, "R200_RE_SCISSOR_TL_2" },
 173    { R200_RE_SCISSOR_BR_2, "R200_RE_SCISSOR_BR_2" },
 174    { R200_RB3D_DEPTHXY_OFFSET, "R200_RB3D_DEPTHXY_OFFSET" },
 175    { R200_RB3D_STENCILREFMASK, "R200_RB3D_STENCILREFMASK" },
 176    { R200_RB3D_ROPCNTL, "R200_RB3D_ROPCNTL" },
 177    { R200_RB3D_PLANEMASK, "R200_RB3D_PLANEMASK" },
 178    { R200_SE_VPORT_XSCALE, "R200_SE_VPORT_XSCALE" },
 179    { R200_SE_VPORT_XOFFSET, "R200_SE_VPORT_XOFFSET" },
 180    { R200_SE_VPORT_YSCALE, "R200_SE_VPORT_YSCALE" },
 181    { R200_SE_VPORT_YOFFSET, "R200_SE_VPORT_YOFFSET" },
 182    { R200_SE_VPORT_ZSCALE, "R200_SE_VPORT_ZSCALE" },
 183    { R200_SE_VPORT_ZOFFSET, "R200_SE_VPORT_ZOFFSET" },
 184    { R200_SE_ZBIAS_FACTOR, "R200_SE_ZBIAS_FACTOR" },
 185    { R200_SE_ZBIAS_CONSTANT, "R200_SE_ZBIAS_CONSTANT" },
 186    { R200_SE_LINE_WIDTH, "R200_SE_LINE_WIDTH" },
 187    { R200_SE_VAP_CNTL, "R200_SE_VAP_CNTL" },
 188    { R200_SE_VF_CNTL, "R200_SE_VF_CNTL" },
 189    { R200_SE_VTX_FMT_0, "R200_SE_VTX_FMT_0" },
 190    { R200_SE_VTX_FMT_1, "R200_SE_VTX_FMT_1" },
 191    { R200_SE_TCL_OUTPUT_VTX_FMT_0, "R200_SE_TCL_OUTPUT_VTX_FMT_0" },
 192    { R200_SE_TCL_OUTPUT_VTX_FMT_1, "R200_SE_TCL_OUTPUT_VTX_FMT_1" },
 193    { R200_SE_VTE_CNTL, "R200_SE_VTE_CNTL" },
 194    { R200_SE_VTX_NUM_ARRAYS, "R200_SE_VTX_NUM_ARRAYS" },
 195    { R200_SE_VTX_AOS_ATTR01, "R200_SE_VTX_AOS_ATTR01" },
 196    { R200_SE_VTX_AOS_ADDR0, "R200_SE_VTX_AOS_ADDR0" },
 197    { R200_SE_VTX_AOS_ADDR1, "R200_SE_VTX_AOS_ADDR1" },
 198    { R200_SE_VTX_AOS_ATTR23, "R200_SE_VTX_AOS_ATTR23" },
 199    { R200_SE_VTX_AOS_ADDR2, "R200_SE_VTX_AOS_ADDR2" },
 200    { R200_SE_VTX_AOS_ADDR3, "R200_SE_VTX_AOS_ADDR3" },
 201    { R200_SE_VTX_AOS_ATTR45, "R200_SE_VTX_AOS_ATTR45" },
 202    { R200_SE_VTX_AOS_ADDR4, "R200_SE_VTX_AOS_ADDR4" },
 203    { R200_SE_VTX_AOS_ADDR5, "R200_SE_VTX_AOS_ADDR5" },
 204    { R200_SE_VTX_AOS_ATTR67, "R200_SE_VTX_AOS_ATTR67" },
 205    { R200_SE_VTX_AOS_ADDR6, "R200_SE_VTX_AOS_ADDR6" },
 206    { R200_SE_VTX_AOS_ADDR7, "R200_SE_VTX_AOS_ADDR7" },
 207    { R200_SE_VTX_AOS_ATTR89, "R200_SE_VTX_AOS_ATTR89" },
 208    { R200_SE_VTX_AOS_ADDR8, "R200_SE_VTX_AOS_ADDR8" },
 209    { R200_SE_VTX_AOS_ADDR9, "R200_SE_VTX_AOS_ADDR9" },
 210    { R200_SE_VTX_AOS_ATTR1011, "R200_SE_VTX_AOS_ATTR1011" },
 211    { R200_SE_VTX_AOS_ADDR10, "R200_SE_VTX_AOS_ADDR10" },
 212    { R200_SE_VTX_AOS_ADDR11, "R200_SE_VTX_AOS_ADDR11" },
 213    { R200_SE_VF_MAX_VTX_INDX, "R200_SE_VF_MAX_VTX_INDX" },
 214    { R200_SE_VF_MIN_VTX_INDX, "R200_SE_VF_MIN_VTX_INDX" },
 215    { R200_SE_VTX_STATE_CNTL, "R200_SE_VTX_STATE_CNTL" },
 216    { R200_SE_TCL_VECTOR_INDX_REG, "R200_SE_TCL_VECTOR_INDX_REG" },
 217    { R200_SE_TCL_VECTOR_DATA_REG, "R200_SE_TCL_VECTOR_DATA_REG" },
 218    { R200_SE_TCL_SCALAR_INDX_REG, "R200_SE_TCL_SCALAR_INDX_REG" },
 219    { R200_SE_TCL_SCALAR_DATA_REG, "R200_SE_TCL_SCALAR_DATA_REG" },
 220    { R200_SE_TCL_MATRIX_SEL_0, "R200_SE_TCL_MATRIX_SEL_0" },
 221    { R200_SE_TCL_MATRIX_SEL_1, "R200_SE_TCL_MATRIX_SEL_1" },
 222    { R200_SE_TCL_MATRIX_SEL_2, "R200_SE_TCL_MATRIX_SEL_2" },
 223    { R200_SE_TCL_MATRIX_SEL_3, "R200_SE_TCL_MATRIX_SEL_3" },
 224    { R200_SE_TCL_MATRIX_SEL_4, "R200_SE_TCL_MATRIX_SEL_4" },
 225    { R200_SE_TCL_LIGHT_MODEL_CTL_0, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
 226    { R200_SE_TCL_LIGHT_MODEL_CTL_1, "R200_SE_TCL_LIGHT_MODEL_CTL_1" },
 227    { R200_SE_TCL_PER_LIGHT_CTL_0, "R200_SE_TCL_PER_LIGHT_CTL_0" },
 228    { R200_SE_TCL_PER_LIGHT_CTL_1, "R200_SE_TCL_PER_LIGHT_CTL_1" },
 229    { R200_SE_TCL_PER_LIGHT_CTL_2, "R200_SE_TCL_PER_LIGHT_CTL_2" },
 230    { R200_SE_TCL_PER_LIGHT_CTL_3, "R200_SE_TCL_PER_LIGHT_CTL_3" },
 231    { R200_SE_TCL_TEX_PROC_CTL_2, "R200_SE_TCL_TEX_PROC_CTL_2" },
 232    { R200_SE_TCL_TEX_PROC_CTL_3, "R200_SE_TCL_TEX_PROC_CTL_3" },
 233    { R200_SE_TCL_TEX_PROC_CTL_0, "R200_SE_TCL_TEX_PROC_CTL_0" },
 234    { R200_SE_TCL_TEX_PROC_CTL_1, "R200_SE_TCL_TEX_PROC_CTL_1" },
 235    { R200_SE_TC_TEX_CYL_WRAP_CTL, "R200_SE_TC_TEX_CYL_WRAP_CTL" },
 236    { R200_SE_TCL_UCP_VERT_BLEND_CTL, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
 237    { R200_SE_TCL_POINT_SPRITE_CNTL, "R200_SE_TCL_POINT_SPRITE_CNTL" },
 238    { R200_SE_VTX_ST_POS_0_X_4, "R200_SE_VTX_ST_POS_0_X_4" },
 239    { R200_SE_VTX_ST_POS_0_Y_4, "R200_SE_VTX_ST_POS_0_Y_4" },
 240    { R200_SE_VTX_ST_POS_0_Z_4, "R200_SE_VTX_ST_POS_0_Z_4" },
 241    { R200_SE_VTX_ST_POS_0_W_4, "R200_SE_VTX_ST_POS_0_W_4" },
 242    { R200_SE_VTX_ST_NORM_0_X, "R200_SE_VTX_ST_NORM_0_X" },
 243    { R200_SE_VTX_ST_NORM_0_Y, "R200_SE_VTX_ST_NORM_0_Y" },
 244    { R200_SE_VTX_ST_NORM_0_Z, "R200_SE_VTX_ST_NORM_0_Z" },
 245    { R200_SE_VTX_ST_PVMS, "R200_SE_VTX_ST_PVMS" },
 246    { R200_SE_VTX_ST_CLR_0_R, "R200_SE_VTX_ST_CLR_0_R" },
 247    { R200_SE_VTX_ST_CLR_0_G, "R200_SE_VTX_ST_CLR_0_G" },
 248    { R200_SE_VTX_ST_CLR_0_B, "R200_SE_VTX_ST_CLR_0_B" },
 249    { R200_SE_VTX_ST_CLR_0_A, "R200_SE_VTX_ST_CLR_0_A" },
 250    { R200_SE_VTX_ST_CLR_1_R, "R200_SE_VTX_ST_CLR_1_R" },
 251    { R200_SE_VTX_ST_CLR_1_G, "R200_SE_VTX_ST_CLR_1_G" },
 252    { R200_SE_VTX_ST_CLR_1_B, "R200_SE_VTX_ST_CLR_1_B" },
 253    { R200_SE_VTX_ST_CLR_1_A, "R200_SE_VTX_ST_CLR_1_A" },
 254    { R200_SE_VTX_ST_CLR_2_R, "R200_SE_VTX_ST_CLR_2_R" },
 255    { R200_SE_VTX_ST_CLR_2_G, "R200_SE_VTX_ST_CLR_2_G" },
 256    { R200_SE_VTX_ST_CLR_2_B, "R200_SE_VTX_ST_CLR_2_B" },
 257    { R200_SE_VTX_ST_CLR_2_A, "R200_SE_VTX_ST_CLR_2_A" },
 258    { R200_SE_VTX_ST_CLR_3_R, "R200_SE_VTX_ST_CLR_3_R" },
 259    { R200_SE_VTX_ST_CLR_3_G, "R200_SE_VTX_ST_CLR_3_G" },
 260    { R200_SE_VTX_ST_CLR_3_B, "R200_SE_VTX_ST_CLR_3_B" },
 261    { R200_SE_VTX_ST_CLR_3_A, "R200_SE_VTX_ST_CLR_3_A" },
 262    { R200_SE_VTX_ST_CLR_4_R, "R200_SE_VTX_ST_CLR_4_R" },
 263    { R200_SE_VTX_ST_CLR_4_G, "R200_SE_VTX_ST_CLR_4_G" },
 264    { R200_SE_VTX_ST_CLR_4_B, "R200_SE_VTX_ST_CLR_4_B" },
 265    { R200_SE_VTX_ST_CLR_4_A, "R200_SE_VTX_ST_CLR_4_A" },
 266    { R200_SE_VTX_ST_CLR_5_R, "R200_SE_VTX_ST_CLR_5_R" },
 267    { R200_SE_VTX_ST_CLR_5_G, "R200_SE_VTX_ST_CLR_5_G" },
 268    { R200_SE_VTX_ST_CLR_5_B, "R200_SE_VTX_ST_CLR_5_B" },
 269    { R200_SE_VTX_ST_CLR_5_A, "R200_SE_VTX_ST_CLR_5_A" },
 270    { R200_SE_VTX_ST_CLR_6_R, "R200_SE_VTX_ST_CLR_6_R" },
 271    { R200_SE_VTX_ST_CLR_6_G, "R200_SE_VTX_ST_CLR_6_G" },
 272    { R200_SE_VTX_ST_CLR_6_B, "R200_SE_VTX_ST_CLR_6_B" },
 273    { R200_SE_VTX_ST_CLR_6_A, "R200_SE_VTX_ST_CLR_6_A" },
 274    { R200_SE_VTX_ST_CLR_7_R, "R200_SE_VTX_ST_CLR_7_R" },
 275    { R200_SE_VTX_ST_CLR_7_G, "R200_SE_VTX_ST_CLR_7_G" },
 276    { R200_SE_VTX_ST_CLR_7_B, "R200_SE_VTX_ST_CLR_7_B" },
 277    { R200_SE_VTX_ST_CLR_7_A, "R200_SE_VTX_ST_CLR_7_A" },
 278    { R200_SE_VTX_ST_TEX_0_S, "R200_SE_VTX_ST_TEX_0_S" },
 279    { R200_SE_VTX_ST_TEX_0_T, "R200_SE_VTX_ST_TEX_0_T" },
 280    { R200_SE_VTX_ST_TEX_0_R, "R200_SE_VTX_ST_TEX_0_R" },
 281    { R200_SE_VTX_ST_TEX_0_Q, "R200_SE_VTX_ST_TEX_0_Q" },
 282    { R200_SE_VTX_ST_TEX_1_S, "R200_SE_VTX_ST_TEX_1_S" },
 283    { R200_SE_VTX_ST_TEX_1_T, "R200_SE_VTX_ST_TEX_1_T" },
 284    { R200_SE_VTX_ST_TEX_1_R, "R200_SE_VTX_ST_TEX_1_R" },
 285    { R200_SE_VTX_ST_TEX_1_Q, "R200_SE_VTX_ST_TEX_1_Q" },
 286    { R200_SE_VTX_ST_TEX_2_S, "R200_SE_VTX_ST_TEX_2_S" },
 287    { R200_SE_VTX_ST_TEX_2_T, "R200_SE_VTX_ST_TEX_2_T" },
 288    { R200_SE_VTX_ST_TEX_2_R, "R200_SE_VTX_ST_TEX_2_R" },
 289    { R200_SE_VTX_ST_TEX_2_Q, "R200_SE_VTX_ST_TEX_2_Q" },
 290    { R200_SE_VTX_ST_TEX_3_S, "R200_SE_VTX_ST_TEX_3_S" },
 291    { R200_SE_VTX_ST_TEX_3_T, "R200_SE_VTX_ST_TEX_3_T" },
 292    { R200_SE_VTX_ST_TEX_3_R, "R200_SE_VTX_ST_TEX_3_R" },
 293    { R200_SE_VTX_ST_TEX_3_Q, "R200_SE_VTX_ST_TEX_3_Q" },
 294    { R200_SE_VTX_ST_TEX_4_S, "R200_SE_VTX_ST_TEX_4_S" },
 295    { R200_SE_VTX_ST_TEX_4_T, "R200_SE_VTX_ST_TEX_4_T" },
 296    { R200_SE_VTX_ST_TEX_4_R, "R200_SE_VTX_ST_TEX_4_R" },
 297    { R200_SE_VTX_ST_TEX_4_Q, "R200_SE_VTX_ST_TEX_4_Q" },
 298    { R200_SE_VTX_ST_TEX_5_S, "R200_SE_VTX_ST_TEX_5_S" },
 299    { R200_SE_VTX_ST_TEX_5_T, "R200_SE_VTX_ST_TEX_5_T" },
 300    { R200_SE_VTX_ST_TEX_5_R, "R200_SE_VTX_ST_TEX_5_R" },
 301    { R200_SE_VTX_ST_TEX_5_Q, "R200_SE_VTX_ST_TEX_5_Q" },
 302    { R200_SE_VTX_ST_PNT_SPRT_SZ, "R200_SE_VTX_ST_PNT_SPRT_SZ" },
 303    { R200_SE_VTX_ST_DISC_FOG, "R200_SE_VTX_ST_DISC_FOG" },
 304    { R200_SE_VTX_ST_SHININESS_0, "R200_SE_VTX_ST_SHININESS_0" },
 305    { R200_SE_VTX_ST_SHININESS_1, "R200_SE_VTX_ST_SHININESS_1" },
 306    { R200_SE_VTX_ST_BLND_WT_0, "R200_SE_VTX_ST_BLND_WT_0" },
 307    { R200_SE_VTX_ST_BLND_WT_1, "R200_SE_VTX_ST_BLND_WT_1" },
 308    { R200_SE_VTX_ST_BLND_WT_2, "R200_SE_VTX_ST_BLND_WT_2" },
 309    { R200_SE_VTX_ST_BLND_WT_3, "R200_SE_VTX_ST_BLND_WT_3" },
 310    { R200_SE_VTX_ST_POS_1_X, "R200_SE_VTX_ST_POS_1_X" },
 311    { R200_SE_VTX_ST_POS_1_Y, "R200_SE_VTX_ST_POS_1_Y" },
 312    { R200_SE_VTX_ST_POS_1_Z, "R200_SE_VTX_ST_POS_1_Z" },
 313    { R200_SE_VTX_ST_POS_1_W, "R200_SE_VTX_ST_POS_1_W" },
 314    { R200_SE_VTX_ST_NORM_1_X, "R200_SE_VTX_ST_NORM_1_X" },
 315    { R200_SE_VTX_ST_NORM_1_Y, "R200_SE_VTX_ST_NORM_1_Y" },
 316    { R200_SE_VTX_ST_NORM_1_Z, "R200_SE_VTX_ST_NORM_1_Z" },
 317    { R200_SE_VTX_ST_USR_CLR_0_R, "R200_SE_VTX_ST_USR_CLR_0_R" },
 318    { R200_SE_VTX_ST_USR_CLR_0_G, "R200_SE_VTX_ST_USR_CLR_0_G" },
 319    { R200_SE_VTX_ST_USR_CLR_0_B, "R200_SE_VTX_ST_USR_CLR_0_B" },
 320    { R200_SE_VTX_ST_USR_CLR_0_A, "R200_SE_VTX_ST_USR_CLR_0_A" },
 321    { R200_SE_VTX_ST_USR_CLR_1_R, "R200_SE_VTX_ST_USR_CLR_1_R" },
 322    { R200_SE_VTX_ST_USR_CLR_1_G, "R200_SE_VTX_ST_USR_CLR_1_G" },
 323    { R200_SE_VTX_ST_USR_CLR_1_B, "R200_SE_VTX_ST_USR_CLR_1_B" },
 324    { R200_SE_VTX_ST_USR_CLR_1_A, "R200_SE_VTX_ST_USR_CLR_1_A" },
 325    { R200_SE_VTX_ST_CLR_0_PKD, "R200_SE_VTX_ST_CLR_0_PKD" },
 326    { R200_SE_VTX_ST_CLR_1_PKD, "R200_SE_VTX_ST_CLR_1_PKD" },
 327    { R200_SE_VTX_ST_CLR_2_PKD, "R200_SE_VTX_ST_CLR_2_PKD" },
 328    { R200_SE_VTX_ST_CLR_3_PKD, "R200_SE_VTX_ST_CLR_3_PKD" },
 329    { R200_SE_VTX_ST_CLR_4_PKD, "R200_SE_VTX_ST_CLR_4_PKD" },
 330    { R200_SE_VTX_ST_CLR_5_PKD, "R200_SE_VTX_ST_CLR_5_PKD" },
 331    { R200_SE_VTX_ST_CLR_6_PKD, "R200_SE_VTX_ST_CLR_6_PKD" },
 332    { R200_SE_VTX_ST_CLR_7_PKD, "R200_SE_VTX_ST_CLR_7_PKD" },
 333    { R200_SE_VTX_ST_POS_0_X_2, "R200_SE_VTX_ST_POS_0_X_2" },
 334    { R200_SE_VTX_ST_POS_0_Y_2, "R200_SE_VTX_ST_POS_0_Y_2" },
 335    { R200_SE_VTX_ST_PAR_CLR_LD, "R200_SE_VTX_ST_PAR_CLR_LD" },
 336    { R200_SE_VTX_ST_USR_CLR_PKD, "R200_SE_VTX_ST_USR_CLR_PKD" },
 337    { R200_SE_VTX_ST_POS_0_X_3, "R200_SE_VTX_ST_POS_0_X_3" },
 338    { R200_SE_VTX_ST_POS_0_Y_3, "R200_SE_VTX_ST_POS_0_Y_3" },
 339    { R200_SE_VTX_ST_POS_0_Z_3, "R200_SE_VTX_ST_POS_0_Z_3" },
 340    { R200_SE_VTX_ST_END_OF_PKT, "R200_SE_VTX_ST_END_OF_PKT" },
 341    { R200_RE_POINTSIZE, "R200_RE_POINTSIZE" },
 342    { R200_RE_TOP_LEFT, "R200_RE_TOP_LEFT" },
 343    { R200_RE_AUX_SCISSOR_CNTL, "R200_RE_AUX_SCISSOR_CNTL" },
 344    { R200_PP_TXFILTER_0, "R200_PP_TXFILTER_0" },
 345    { R200_PP_TXFORMAT_0, "R200_PP_TXFORMAT_0" },
 346    { R200_PP_TXSIZE_0, "R200_PP_TXSIZE_0" },
 347    { R200_PP_TXFORMAT_X_0, "R200_PP_TXFORMAT_X_0" },
 348    { R200_PP_TXPITCH_0, "R200_PP_TXPITCH_0" },
 349    { R200_PP_BORDER_COLOR_0, "R200_PP_BORDER_COLOR_0" },
 350    { R200_PP_CUBIC_FACES_0, "R200_PP_CUBIC_FACES_0" },
 351    { R200_PP_TXFILTER_1, "R200_PP_TXFILTER_1" },
 352    { R200_PP_TXFORMAT_1, "R200_PP_TXFORMAT_1" },
 353    { R200_PP_TXSIZE_1, "R200_PP_TXSIZE_1" },
 354    { R200_PP_TXFORMAT_X_1, "R200_PP_TXFORMAT_X_1" },
 355    { R200_PP_TXPITCH_1, "R200_PP_TXPITCH_1" },
 356    { R200_PP_BORDER_COLOR_1, "R200_PP_BORDER_COLOR_1" },
 357    { R200_PP_CUBIC_FACES_1, "R200_PP_CUBIC_FACES_1" },
 358    { R200_PP_TXFILTER_2, "R200_PP_TXFILTER_2" },
 359    { R200_PP_TXFORMAT_2, "R200_PP_TXFORMAT_2" },
 360    { R200_PP_TXSIZE_2, "R200_PP_TXSIZE_2" },
 361    { R200_PP_TXFORMAT_X_2, "R200_PP_TXFORMAT_X_2" },
 362    { R200_PP_TXPITCH_2, "R200_PP_TXPITCH_2" },
 363    { R200_PP_BORDER_COLOR_2, "R200_PP_BORDER_COLOR_2" },
 364    { R200_PP_CUBIC_FACES_2, "R200_PP_CUBIC_FACES_2" },
 365    { R200_PP_TXFILTER_3, "R200_PP_TXFILTER_3" },
 366    { R200_PP_TXFORMAT_3, "R200_PP_TXFORMAT_3" },
 367    { R200_PP_TXSIZE_3, "R200_PP_TXSIZE_3" },
 368    { R200_PP_TXFORMAT_X_3, "R200_PP_TXFORMAT_X_3" },
 369    { R200_PP_TXPITCH_3, "R200_PP_TXPITCH_3" },
 370    { R200_PP_BORDER_COLOR_3, "R200_PP_BORDER_COLOR_3" },
 371    { R200_PP_CUBIC_FACES_3, "R200_PP_CUBIC_FACES_3" },
 372    { R200_PP_TXFILTER_4, "R200_PP_TXFILTER_4" },
 373    { R200_PP_TXFORMAT_4, "R200_PP_TXFORMAT_4" },
 374    { R200_PP_TXSIZE_4, "R200_PP_TXSIZE_4" },
 375    { R200_PP_TXFORMAT_X_4, "R200_PP_TXFORMAT_X_4" },
 376    { R200_PP_TXPITCH_4, "R200_PP_TXPITCH_4" },
 377    { R200_PP_BORDER_COLOR_4, "R200_PP_BORDER_COLOR_4" },
 378    { R200_PP_CUBIC_FACES_4, "R200_PP_CUBIC_FACES_4" },
 379    { R200_PP_TXFILTER_5, "R200_PP_TXFILTER_5" },
 380    { R200_PP_TXFORMAT_5, "R200_PP_TXFORMAT_5" },
 381    { R200_PP_TXSIZE_5, "R200_PP_TXSIZE_5" },
 382    { R200_PP_TXFORMAT_X_5, "R200_PP_TXFORMAT_X_5" },
 383    { R200_PP_TXPITCH_5, "R200_PP_TXPITCH_5" },
 384    { R200_PP_BORDER_COLOR_5, "R200_PP_BORDER_COLOR_5" },
 385    { R200_PP_CUBIC_FACES_5, "R200_PP_CUBIC_FACES_5" },
 386    { R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" },
 387    { R200_PP_CUBIC_OFFSET_F1_0, "R200_PP_CUBIC_OFFSET_F1_0" },
 388    { R200_PP_CUBIC_OFFSET_F2_0, "R200_PP_CUBIC_OFFSET_F2_0" },
 389    { R200_PP_CUBIC_OFFSET_F3_0, "R200_PP_CUBIC_OFFSET_F3_0" },
 390    { R200_PP_CUBIC_OFFSET_F4_0, "R200_PP_CUBIC_OFFSET_F4_0" },
 391    { R200_PP_CUBIC_OFFSET_F5_0, "R200_PP_CUBIC_OFFSET_F5_0" },
 392    { R200_PP_TXOFFSET_1, "R200_PP_TXOFFSET_1" },
 393    { R200_PP_CUBIC_OFFSET_F1_1, "R200_PP_CUBIC_OFFSET_F1_1" },
 394    { R200_PP_CUBIC_OFFSET_F2_1, "R200_PP_CUBIC_OFFSET_F2_1" },
 395    { R200_PP_CUBIC_OFFSET_F3_1, "R200_PP_CUBIC_OFFSET_F3_1" },
 396    { R200_PP_CUBIC_OFFSET_F4_1, "R200_PP_CUBIC_OFFSET_F4_1" },
 397    { R200_PP_CUBIC_OFFSET_F5_1, "R200_PP_CUBIC_OFFSET_F5_1" },
 398    { R200_PP_TXOFFSET_2, "R200_PP_TXOFFSET_2" },
 399    { R200_PP_CUBIC_OFFSET_F1_2, "R200_PP_CUBIC_OFFSET_F1_2" },
 400    { R200_PP_CUBIC_OFFSET_F2_2, "R200_PP_CUBIC_OFFSET_F2_2" },
 401    { R200_PP_CUBIC_OFFSET_F3_2, "R200_PP_CUBIC_OFFSET_F3_2" },
 402    { R200_PP_CUBIC_OFFSET_F4_2, "R200_PP_CUBIC_OFFSET_F4_2" },
 403    { R200_PP_CUBIC_OFFSET_F5_2, "R200_PP_CUBIC_OFFSET_F5_2" },
 404    { R200_PP_TXOFFSET_3, "R200_PP_TXOFFSET_3" },
 405    { R200_PP_CUBIC_OFFSET_F1_3, "R200_PP_CUBIC_OFFSET_F1_3" },
 406    { R200_PP_CUBIC_OFFSET_F2_3, "R200_PP_CUBIC_OFFSET_F2_3" },
 407    { R200_PP_CUBIC_OFFSET_F3_3, "R200_PP_CUBIC_OFFSET_F3_3" },
 408    { R200_PP_CUBIC_OFFSET_F4_3, "R200_PP_CUBIC_OFFSET_F4_3" },
 409    { R200_PP_CUBIC_OFFSET_F5_3, "R200_PP_CUBIC_OFFSET_F5_3" },
 410    { R200_PP_TXOFFSET_4, "R200_PP_TXOFFSET_4" },
 411    { R200_PP_CUBIC_OFFSET_F1_4, "R200_PP_CUBIC_OFFSET_F1_4" },
 412    { R200_PP_CUBIC_OFFSET_F2_4, "R200_PP_CUBIC_OFFSET_F2_4" },
 413    { R200_PP_CUBIC_OFFSET_F3_4, "R200_PP_CUBIC_OFFSET_F3_4" },
 414    { R200_PP_CUBIC_OFFSET_F4_4, "R200_PP_CUBIC_OFFSET_F4_4" },
 415    { R200_PP_CUBIC_OFFSET_F5_4, "R200_PP_CUBIC_OFFSET_F5_4" },
 416    { R200_PP_TXOFFSET_5, "R200_PP_TXOFFSET_5" },
 417    { R200_PP_CUBIC_OFFSET_F1_5, "R200_PP_CUBIC_OFFSET_F1_5" },
 418    { R200_PP_CUBIC_OFFSET_F2_5, "R200_PP_CUBIC_OFFSET_F2_5" },
 419    { R200_PP_CUBIC_OFFSET_F3_5, "R200_PP_CUBIC_OFFSET_F3_5" },
 420    { R200_PP_CUBIC_OFFSET_F4_5, "R200_PP_CUBIC_OFFSET_F4_5" },
 421    { R200_PP_CUBIC_OFFSET_F5_5, "R200_PP_CUBIC_OFFSET_F5_5" },
 422    { R200_PP_TAM_DEBUG3, "R200_PP_TAM_DEBUG3" },
 423    { R200_PP_TFACTOR_0, "R200_PP_TFACTOR_0" },
 424    { R200_PP_TFACTOR_1, "R200_PP_TFACTOR_1" },
 425    { R200_PP_TFACTOR_2, "R200_PP_TFACTOR_2" },
 426    { R200_PP_TFACTOR_3, "R200_PP_TFACTOR_3" },
 427    { R200_PP_TFACTOR_4, "R200_PP_TFACTOR_4" },
 428    { R200_PP_TFACTOR_5, "R200_PP_TFACTOR_5" },
 429    { R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" },
 430    { R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" },
 431    { R200_PP_TXABLEND_0, "R200_PP_TXABLEND_0" },
 432    { R200_PP_TXABLEND2_0, "R200_PP_TXABLEND2_0" },
 433    { R200_PP_TXCBLEND_1, "R200_PP_TXCBLEND_1" },
 434    { R200_PP_TXCBLEND2_1, "R200_PP_TXCBLEND2_1" },
 435    { R200_PP_TXABLEND_1, "R200_PP_TXABLEND_1" },
 436    { R200_PP_TXABLEND2_1, "R200_PP_TXABLEND2_1" },
 437    { R200_PP_TXCBLEND_2, "R200_PP_TXCBLEND_2" },
 438    { R200_PP_TXCBLEND2_2, "R200_PP_TXCBLEND2_2" },
 439    { R200_PP_TXABLEND_2, "R200_PP_TXABLEND_2" },
 440    { R200_PP_TXABLEND2_2, "R200_PP_TXABLEND2_2" },
 441    { R200_PP_TXCBLEND_3, "R200_PP_TXCBLEND_3" },
 442    { R200_PP_TXCBLEND2_3, "R200_PP_TXCBLEND2_3" },
 443    { R200_PP_TXABLEND_3, "R200_PP_TXABLEND_3" },
 444    { R200_PP_TXABLEND2_3, "R200_PP_TXABLEND2_3" },
 445    { R200_PP_TXCBLEND_4, "R200_PP_TXCBLEND_4" },
 446    { R200_PP_TXCBLEND2_4, "R200_PP_TXCBLEND2_4" },
 447    { R200_PP_TXABLEND_4, "R200_PP_TXABLEND_4" },
 448    { R200_PP_TXABLEND2_4, "R200_PP_TXABLEND2_4" },
 449    { R200_PP_TXCBLEND_5, "R200_PP_TXCBLEND_5" },
 450    { R200_PP_TXCBLEND2_5, "R200_PP_TXCBLEND2_5" },
 451    { R200_PP_TXABLEND_5, "R200_PP_TXABLEND_5" },
 452    { R200_PP_TXABLEND2_5, "R200_PP_TXABLEND2_5" },
 453    { R200_PP_TXCBLEND_6, "R200_PP_TXCBLEND_6" },
 454    { R200_PP_TXCBLEND2_6, "R200_PP_TXCBLEND2_6" },
 455    { R200_PP_TXABLEND_6, "R200_PP_TXABLEND_6" },
 456    { R200_PP_TXABLEND2_6, "R200_PP_TXABLEND2_6" },
 457    { R200_PP_TXCBLEND_7, "R200_PP_TXCBLEND_7" },
 458    { R200_PP_TXCBLEND2_7, "R200_PP_TXCBLEND2_7" },
 459    { R200_PP_TXABLEND_7, "R200_PP_TXABLEND_7" },
 460    { R200_PP_TXABLEND2_7, "R200_PP_TXABLEND2_7" },
 461    { R200_RB3D_ABLENDCNTL, "R200_RB3D_ABLENDCNTL" },
 462    { R200_RB3D_CBLENDCNTL, "R200_RB3D_CBLENDCNTL" },
 463    { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
 464    { R200_PP_CNTL_X, "R200_PP_CNTL_X" },
 465    { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" },
 466    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
 467    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
 468    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
 469    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
 470 };
 471
 472 static struct reg_names scalar_names[] = {
 473    { R200_SS_LIGHT_DCD_ADDR, "R200_SS_LIGHT_DCD_ADDR" },
 474    { R200_SS_LIGHT_DCM_ADDR, "R200_SS_LIGHT_DCM_ADDR" },
 475    { R200_SS_LIGHT_SPOT_EXPONENT_ADDR, "R200_SS_LIGHT_SPOT_EXPONENT_ADDR" },
 476    { R200_SS_LIGHT_SPOT_CUTOFF_ADDR, "R200_SS_LIGHT_SPOT_CUTOFF_ADDR" },
 477    { R200_SS_LIGHT_SPECULAR_THRESH_ADDR, "R200_SS_LIGHT_SPECULAR_THRESH_ADDR" },
 478    { R200_SS_LIGHT_RANGE_CUTOFF_SQRD, "R200_SS_LIGHT_RANGE_CUTOFF_SQRD" },
 479    { R200_SS_LIGHT_RANGE_ATT_CONST, "R200_SS_LIGHT_RANGE_ATT_CONST" },
 480    { R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, "R200_SS_VERT_GUARD_CLIP_ADJ_ADDR" },
 481    { R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR, "R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR" },
 482    { R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR, "R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR" },
 483    { R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR, "R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR" },
 484    { R200_SS_MAT_0_SHININESS, "R200_SS_MAT_0_SHININESS" },
 485    { R200_SS_MAT_1_SHININESS, "R200_SS_MAT_1_SHININESS" },
 486    { 1000, "" },
 487 };
 488
 489 /* Puff these out to make them look like normal (dword) registers.
 490  */
 491 static struct reg_names vector_names[] = {
 492    { 0, "start" },
 493    { R200_VS_LIGHT_AMBIENT_ADDR, "R200_VS_LIGHT_AMBIENT_ADDR" },
 494    { R200_VS_LIGHT_DIFFUSE_ADDR, "R200_VS_LIGHT_DIFFUSE_ADDR" },
 495    { R200_VS_LIGHT_SPECULAR_ADDR, "R200_VS_LIGHT_SPECULAR_ADDR" },
 496    { R200_VS_LIGHT_DIRPOS_ADDR, "R200_VS_LIGHT_DIRPOS_ADDR" },
 497    { R200_VS_LIGHT_HWVSPOT_ADDR, "R200_VS_LIGHT_HWVSPOT_ADDR" },
 498    { R200_VS_LIGHT_ATTENUATION_ADDR, "R200_VS_LIGHT_ATTENUATION_ADDR" },
 499    { R200_VS_SPOT_DUAL_CONE, "R200_VS_SPOT_DUAL_CONE" },
 500    { R200_VS_GLOBAL_AMBIENT_ADDR, "R200_VS_GLOBAL_AMBIENT_ADDR" },
 501    { R200_VS_FOG_PARAM_ADDR, "R200_VS_FOG_PARAM_ADDR" },
 502    { R200_VS_EYE_VECTOR_ADDR, "R200_VS_EYE_VECTOR_ADDR" },
 503    { R200_VS_UCP_ADDR, "R200_VS_UCP_ADDR" },
 504    { R200_VS_PNT_SPRITE_VPORT_SCALE, "R200_VS_PNT_SPRITE_VPORT_SCALE" },
 505    { R200_VS_MATRIX_0_MV, "R200_VS_MATRIX_0_MV" },
 506    { R200_VS_MATRIX_1_INV_MV, "R200_VS_MATRIX_1_INV_MV" },
 507    { R200_VS_MATRIX_2_MVP, "R200_VS_MATRIX_2_MVP" },
 508    { R200_VS_MATRIX_3_TEX0, "R200_VS_MATRIX_3_TEX0" },
 509    { R200_VS_MATRIX_4_TEX1, "R200_VS_MATRIX_4_TEX1" },
 510    { R200_VS_MATRIX_5_TEX2, "R200_VS_MATRIX_5_TEX2" },
 511    { R200_VS_MATRIX_6_TEX3, "R200_VS_MATRIX_6_TEX3" },
 512    { R200_VS_MATRIX_7_TEX4, "R200_VS_MATRIX_7_TEX4" },
 513    { R200_VS_MATRIX_8_TEX5, "R200_VS_MATRIX_8_TEX5" },
 514    { R200_VS_MAT_0_EMISS, "R200_VS_MAT_0_EMISS" },
 515    { R200_VS_MAT_0_AMB, "R200_VS_MAT_0_AMB" },
 516    { R200_VS_MAT_0_DIF, "R200_VS_MAT_0_DIF" },
 517    { R200_VS_MAT_0_SPEC, "R200_VS_MAT_0_SPEC" },
 518    { R200_VS_MAT_1_EMISS, "R200_VS_MAT_1_EMISS" },
 519    { R200_VS_MAT_1_AMB, "R200_VS_MAT_1_AMB" },
 520    { R200_VS_MAT_1_DIF, "R200_VS_MAT_1_DIF" },
 521    { R200_VS_MAT_1_SPEC, "R200_VS_MAT_1_SPEC" },
 522    { R200_VS_EYE2CLIP_MTX, "R200_VS_EYE2CLIP_MTX" },
 523    { R200_VS_PNT_SPRITE_ATT_CONST, "R200_VS_PNT_SPRITE_ATT_CONST" },
 524    { R200_VS_PNT_SPRITE_EYE_IN_MODEL, "R200_VS_PNT_SPRITE_EYE_IN_MODEL" },
 525    { R200_VS_PNT_SPRITE_CLAMP, "R200_VS_PNT_SPRITE_CLAMP" },
 526    { R200_VS_MAX, "R200_VS_MAX" },
 527    { 1000, "" },
 528 };
 529
 530 union fi { float f; int i; };
 531
 532 #define ISVEC   1
 533 #define ISFLOAT 2
 534 #define TOUCHED 4
 535
 536 struct reg {
 537    int idx;
 538    struct reg_names *closest;
 539    int flags;
 540    union fi current;
 541    union fi *values;
 542    int nvalues;
 543    int nalloc;
 544    float vmin, vmax;
 545 };
 546
 547
 548 static struct reg regs[Elements(reg_names)+1];
 549 static struct reg scalars[512+1];
 550 static struct reg vectors[512*4+1];
 551
 552 static int total, total_changed, bufs;
 553
 554 static void init_regs( void )
 555 {
 556    struct reg_names *tmp;
 557    int i;
 558
 559    for (i = 0 ; i < Elements(regs) ; i++) {
 560       regs[i].idx = reg_names[i].idx;
 561       regs[i].closest = &reg_names[i];
 562       regs[i].flags = 0;
 563    }
 564
 565    for (i = 0, tmp = scalar_names ; i < Elements(scalars) ; i++) {
 566       if (tmp[1].idx == i) tmp++;
 567       scalars[i].idx = i;
 568       scalars[i].closest = tmp;
 569       scalars[i].flags = ISFLOAT;
 570    }
 571
 572    for (i = 0, tmp = vector_names ; i < Elements(vectors) ; i++) {
 573       if (tmp[1].idx*4 == i) tmp++;
 574       vectors[i].idx = i;
 575       vectors[i].closest = tmp;
 576       vectors[i].flags = ISFLOAT|ISVEC;
 577    }
 578
 579    regs[Elements(regs)-1].idx = -1;
 580    scalars[Elements(scalars)-1].idx = -1;
 581    vectors[Elements(vectors)-1].idx = -1;
 582 }
 583
 584 static int find_or_add_value( struct reg *reg, int val )
 585 {
 586    int j;
 587
 588    for ( j = 0 ; j < reg->nvalues ; j++)
 589       if ( val == reg->values[j].i )
 590          return 1;
 591
 592    if (j == reg->nalloc) {
 593       reg->nalloc += 5;
 594       reg->nalloc *= 2;
 595       reg->values = (union fi *) realloc( reg->values,
 596                                           reg->nalloc * sizeof(union fi) );
 597    }
 598
 599    reg->values[reg->nvalues++].i = val;
 600    return 0;
 601 }
 602
 603 static struct reg *lookup_reg( struct reg *tab, int reg )
 604 {
 605    int i;
 606
 607    for (i = 0 ; tab[i].idx != -1 ; i++) {
 608       if (tab[i].idx == reg)
 609          return &tab[i];
 610    }
 611
 612    fprintf(stderr, "*** unknown reg 0x%x\n", reg);
 613    return 0;
 614 }
 615
 616
 617 static const char *get_reg_name( struct reg *reg )
 618 {
 619    static char tmp[80];
 620
 621    if (reg->idx == reg->closest->idx)
 622       return reg->closest->name;
 623
 624
 625    if (reg->flags & ISVEC) {
 626       if (reg->idx/4 != reg->closest->idx)
 627          sprintf(tmp, "%s+%d[%d]",
 628                  reg->closest->name,
 629                  (reg->idx/4) - reg->closest->idx,
 630                  reg->idx%4);
 631       else
 632          sprintf(tmp, "%s[%d]", reg->closest->name, reg->idx%4);
 633    }
 634    else {
 635       if (reg->idx != reg->closest->idx)
 636          sprintf(tmp, "%s+%d", reg->closest->name, reg->idx - reg->closest->idx);
 637       else
 638          sprintf(tmp, "%s", reg->closest->name);
 639    }
 640
 641    return tmp;
 642 }
 643
 644 static int print_int_reg_assignment( struct reg *reg, int data )
 645 {
 646    int changed = (reg->current.i != data);
 647    int ever_seen = find_or_add_value( reg, data );
 648
 649    if (VERBOSE || (NORMAL && (changed || !ever_seen)))
 650        fprintf(stderr, "   %s <-- 0x%x", get_reg_name(reg), data);
 651
 652    if (NORMAL) {
 653       if (!ever_seen)
 654          fprintf(stderr, " *** BRAND NEW VALUE");
 655       else if (changed)
 656          fprintf(stderr, " *** CHANGED");
 657    }
 658
 659    reg->current.i = data;
 660
 661    if (VERBOSE || (NORMAL && (changed || !ever_seen)))
 662       fprintf(stderr, "\n");
 663
 664    return changed;
 665 }
 666
 667
 668 static int print_float_reg_assignment( struct reg *reg, float data )
 669 {
 670    int changed = (reg->current.f != data);
 671    int newmin = (data < reg->vmin);
 672    int newmax = (data > reg->vmax);
 673
 674    if (VERBOSE || (NORMAL && (newmin || newmax || changed)))
 675       fprintf(stderr, "   %s <-- %.3f", get_reg_name(reg), data);
 676
 677    if (NORMAL) {
 678       if (newmin) {
 679          fprintf(stderr, " *** NEW MIN (prev %.3f)", reg->vmin);
 680          reg->vmin = data;
 681       }
 682       else if (newmax) {
 683          fprintf(stderr, " *** NEW MAX (prev %.3f)", reg->vmax);
 684          reg->vmax = data;
 685       }
 686       else if (changed) {
 687          fprintf(stderr, " *** CHANGED");
 688       }
 689    }
 690
 691    reg->current.f = data;
 692
 693    if (VERBOSE || (NORMAL && (newmin || newmax || changed)))
 694       fprintf(stderr, "\n");
 695
 696    return changed;
 697 }
 698
 699 static int print_reg_assignment( struct reg *reg, int data )
 700 {
 701    reg->flags |= TOUCHED;
 702    if (reg->flags & ISFLOAT)
 703       return print_float_reg_assignment( reg, *(float *)&data );
 704    else
 705       return print_int_reg_assignment( reg, data );
 706 }
 707
 708 static void print_reg( struct reg *reg )
 709 {
 710    if (reg->flags & TOUCHED) {
 711       if (reg->flags & ISFLOAT) {
 712          fprintf(stderr, "   %s == %f\n", get_reg_name(reg), reg->current.f);
 713       } else {
 714          fprintf(stderr, "   %s == 0x%x\n", get_reg_name(reg), reg->current.i);
 715       }
 716    }
 717 }
 718
 719
 720 static void dump_state( void )
 721 {
 722    int i;
 723
 724    for (i = 0 ; i < Elements(regs) ; i++)
 725       print_reg( &regs[i] );
 726
 727    for (i = 0 ; i < Elements(scalars) ; i++)
 728       print_reg( &scalars[i] );
 729
 730    for (i = 0 ; i < Elements(vectors) ; i++)
 731       print_reg( &vectors[i] );
 732 }
 733
 734
 735
 736 static int radeon_emit_packets(
 737    drmRadeonCmdHeader header,
 738    drmRadeonCmdBuffer *cmdbuf )
 739 {
 740    int id = (int)header.packet.packet_id;
 741    int sz = packet[id].len;
 742    int *data = (int *)cmdbuf->buf;
 743    int i;
 744
 745    if (sz * sizeof(int) > cmdbuf->bufsz) {
 746       fprintf(stderr, "Packet overflows cmdbuf\n");
 747       return -EINVAL;
 748    }
 749
 750    if (!packet[id].name) {
 751       fprintf(stderr, "*** Unknown packet 0 nr %d\n", id );
 752       return -EINVAL;
 753    }
 754
 755
 756    if (VERBOSE)
 757       fprintf(stderr, "Packet 0 reg %s nr %d\n", packet[id].name, sz );
 758
 759    for ( i = 0 ; i < sz ; i++) {
 760       struct reg *reg = lookup_reg( regs, packet[id].start + i*4 );
 761       if (print_reg_assignment( reg, data[i] ))
 762          total_changed++;
 763       total++;
 764    }
 765
 766    cmdbuf->buf += sz * sizeof(int);
 767    cmdbuf->bufsz -= sz * sizeof(int);
 768    return 0;
 769 }
 770
 771
 772 static int radeon_emit_scalars(
 773    drmRadeonCmdHeader header,
 774    drmRadeonCmdBuffer *cmdbuf )
 775 {
 776    int sz = header.scalars.count;
 777    int *data = (int *)cmdbuf->buf;
 778    int start = header.scalars.offset;
 779    int stride = header.scalars.stride;
 780    int i;
 781
 782    if (VERBOSE)
 783       fprintf(stderr, "emit scalars, start %d stride %d nr %d (end %d)\n",
 784               start, stride, sz, start + stride * sz);
 785
 786
 787    for (i = 0 ; i < sz ; i++, start += stride) {
 788       struct reg *reg = lookup_reg( scalars, start );
 789       if (print_reg_assignment( reg, data[i] ))
 790          total_changed++;
 791       total++;
 792    }
 793
 794    cmdbuf->buf += sz * sizeof(int);
 795    cmdbuf->bufsz -= sz * sizeof(int);
 796    return 0;
 797 }
 798
 799
 800 static int radeon_emit_scalars2(
 801    drmRadeonCmdHeader header,
 802    drmRadeonCmdBuffer *cmdbuf )
 803 {
 804    int sz = header.scalars.count;
 805    int *data = (int *)cmdbuf->buf;
 806    int start = header.scalars.offset + 0x100;
 807    int stride = header.scalars.stride;
 808    int i;
 809
 810    if (VERBOSE)
 811       fprintf(stderr, "emit scalars2, start %d stride %d nr %d (end %d)\n",
 812               start, stride, sz, start + stride * sz);
 813
 814    if (start + stride * sz > 257) {
 815       fprintf(stderr, "emit scalars OVERFLOW %d/%d/%d\n", start, stride, sz);
 816       return -1;
 817    }
 818
 819    for (i = 0 ; i < sz ; i++, start += stride) {
 820       struct reg *reg = lookup_reg( scalars, start );
 821       if (print_reg_assignment( reg, data[i] ))
 822          total_changed++;
 823       total++;
 824    }
 825
 826    cmdbuf->buf += sz * sizeof(int);
 827    cmdbuf->bufsz -= sz * sizeof(int);
 828    return 0;
 829 }
 830
 831 /* Check: inf/nan/extreme-size?
 832  * Check: table start, end, nr, etc.
 833  */
 834 static int radeon_emit_vectors(
 835    drmRadeonCmdHeader header,
 836    drmRadeonCmdBuffer *cmdbuf )
 837 {
 838    int sz = header.vectors.count;
 839    int *data = (int *)cmdbuf->buf;
 840    int start = header.vectors.offset;
 841    int stride = header.vectors.stride;
 842    int i,j;
 843
 844    if (VERBOSE)
 845       fprintf(stderr, "emit vectors, start %d stride %d nr %d (end %d) (0x%x)\n",
 846               start, stride, sz, start + stride * sz, header.i);
 847
 848 /*    if (start + stride * (sz/4) > 128) { */
 849 /*       fprintf(stderr, "emit vectors OVERFLOW %d/%d/%d\n", start, stride, sz); */
 850 /*       return -1; */
 851 /*    } */
 852
 853    for (i = 0 ; i < sz ;  start += stride) {
 854       int changed = 0;
 855       for (j = 0 ; j < 4 ; i++,j++) {
 856          struct reg *reg = lookup_reg( vectors, start*4+j );
 857          if (print_reg_assignment( reg, data[i] ))
 858             changed = 1;
 859       }
 860       if (changed)
 861          total_changed += 4;
 862       total += 4;
 863    }
 864
 865
 866    cmdbuf->buf += sz * sizeof(int);
 867    cmdbuf->bufsz -= sz * sizeof(int);
 868    return 0;
 869 }
 870
 871 #if 0
 872 static int print_vertex_format( int vfmt )
 873 {
 874    if (NORMAL) {
 875       fprintf(stderr, "   %s(%x): %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 876               "vertex format",
 877               vfmt,
 878               "xy,",
 879               (vfmt & R200_VTX_Z0) ? "z," : "",
 880               (vfmt & R200_VTX_W0) ? "w0," : "",
 881               (vfmt & R200_VTX_FPCOLOR) ? "fpcolor," : "",
 882               (vfmt & R200_VTX_FPALPHA) ? "fpalpha," : "",
 883               (vfmt & R200_VTX_PKCOLOR) ? "pkcolor," : "",
 884               (vfmt & R200_VTX_FPSPEC) ? "fpspec," : "",
 885               (vfmt & R200_VTX_FPFOG) ? "fpfog," : "",
 886               (vfmt & R200_VTX_PKSPEC) ? "pkspec," : "",
 887               (vfmt & R200_VTX_ST0) ? "st0," : "",
 888               (vfmt & R200_VTX_ST1) ? "st1," : "",
 889               (vfmt & R200_VTX_Q1) ? "q1," : "",
 890               (vfmt & R200_VTX_ST2) ? "st2," : "",
 891               (vfmt & R200_VTX_Q2) ? "q2," : "",
 892               (vfmt & R200_VTX_ST3) ? "st3," : "",
 893               (vfmt & R200_VTX_Q3) ? "q3," : "",
 894               (vfmt & R200_VTX_Q0) ? "q0," : "",
 895               (vfmt & R200_VTX_N0) ? "n0," : "",
 896               (vfmt & R200_VTX_XY1) ? "xy1," : "",
 897               (vfmt & R200_VTX_Z1) ? "z1," : "",
 898               (vfmt & R200_VTX_W1) ? "w1," : "",
 899               (vfmt & R200_VTX_N1) ? "n1," : "");
 900
 901
 902       if (!find_or_add_value( &others[V_VTXFMT], vfmt ))
 903          fprintf(stderr, " *** NEW VALUE");
 904
 905       fprintf(stderr, "\n");
 906    }
 907
 908    return 0;
 909 }
 910 #endif
 911
 912 static char *primname[0x10] = {
 913    "NONE",
 914    "POINTS",
 915    "LINES",
 916    "LINE_STRIP",
 917    "TRIANGLES",
 918    "TRIANGLE_FAN",
 919    "TRIANGLE_STRIP",
 920    "RECT_LIST",
 921    0,
 922    "3VRT_POINTS",
 923    "3VRT_LINES",
 924    "POINT_SPRITES",
 925    "LINE_LOOP",
 926    "QUADS",
 927    "QUAD_STRIP",
 928    "POLYGON",
 929 };
 930
 931 static int print_prim_and_flags( int prim )
 932 {
 933    int numverts;
 934
 935    if (NORMAL)
 936       fprintf(stderr, "   %s(%x): %s%s%s%s%s%s\n",
 937               "prim flags",
 938               prim,
 939               ((prim & 0x30) == R200_VF_PRIM_WALK_IND) ? "IND," : "",
 940               ((prim & 0x30) == R200_VF_PRIM_WALK_LIST) ? "LIST," : "",
 941               ((prim & 0x30) == R200_VF_PRIM_WALK_RING) ? "RING," : "",
 942               (prim & R200_VF_COLOR_ORDER_RGBA) ? "RGBA," : "BGRA, ",
 943               (prim & R200_VF_INDEX_SZ_4) ? "INDX-32," : "",
 944               (prim & R200_VF_TCL_OUTPUT_VTX_ENABLE) ? "TCL_OUT_VTX," : "");
 945
 946    numverts = prim>>16;
 947
 948    if (NORMAL)
 949       fprintf(stderr, "   prim: %s numverts %d\n", primname[prim&0xf], numverts);
 950
 951    switch (prim & 0xf) {
 952    case R200_VF_PRIM_NONE:
 953    case R200_VF_PRIM_POINTS:
 954       if (numverts < 1) {
 955          fprintf(stderr, "Bad nr verts for line %d\n", numverts);
 956          return -1;
 957       }
 958       break;
 959    case R200_VF_PRIM_LINES:
 960    case R200_VF_PRIM_POINT_SPRITES:
 961       if ((numverts & 1) || numverts == 0) {
 962          fprintf(stderr, "Bad nr verts for line %d\n", numverts);
 963          return -1;
 964       }
 965       break;
 966    case R200_VF_PRIM_LINE_STRIP:
 967    case R200_VF_PRIM_LINE_LOOP:
 968       if (numverts < 2) {
 969          fprintf(stderr, "Bad nr verts for line_strip %d\n", numverts);
 970          return -1;
 971       }
 972       break;
 973    case R200_VF_PRIM_TRIANGLES:
 974    case R200_VF_PRIM_3VRT_POINTS:
 975    case R200_VF_PRIM_3VRT_LINES:
 976    case R200_VF_PRIM_RECT_LIST:
 977       if (numverts % 3 || numverts == 0) {
 978          fprintf(stderr, "Bad nr verts for tri %d\n", numverts);
 979          return -1;
 980       }
 981       break;
 982    case R200_VF_PRIM_TRIANGLE_FAN:
 983    case R200_VF_PRIM_TRIANGLE_STRIP:
 984    case R200_VF_PRIM_POLYGON:
 985       if (numverts < 3) {
 986          fprintf(stderr, "Bad nr verts for strip/fan %d\n", numverts);
 987          return -1;
 988       }
 989       break;
 990    case R200_VF_PRIM_QUADS:
 991       if (numverts % 4 || numverts == 0) {
 992          fprintf(stderr, "Bad nr verts for quad %d\n", numverts);
 993          return -1;
 994       }
 995       break;
 996    case R200_VF_PRIM_QUAD_STRIP:
 997       if (numverts % 2 || numverts < 4) {
 998          fprintf(stderr, "Bad nr verts for quadstrip %d\n", numverts);
 999          return -1;
1000       }
1001       break;
1002    default:
1003       fprintf(stderr, "Bad primitive\n");
1004       return -1;
1005    }
1006    return 0;
1007 }
1008
1009 /* build in knowledge about each packet type
1010  */
1011 static int radeon_emit_packet3( drmRadeonCmdBuffer *cmdbuf )
1012 {
1013    int cmdsz;
1014    int *cmd = (int *)cmdbuf->buf;
1015    int *tmp;
1016    int i, stride, size, start;
1017
1018    cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);
1019
1020    if ((cmd[0] & RADEON_CP_PACKET_MASK) != RADEON_CP_PACKET3 ||
1021        cmdsz * 4 > cmdbuf->bufsz ||
1022        cmdsz > RADEON_CP_PACKET_MAX_DWORDS) {
1023       fprintf(stderr, "Bad packet\n");
1024       return -EINVAL;
1025    }
1026
1027    switch( cmd[0] & ~RADEON_CP_PACKET_COUNT_MASK ) {
1028    case R200_CP_CMD_NOP:
1029       if (NORMAL)
1030          fprintf(stderr, "PACKET3_NOP, %d dwords\n", cmdsz);
1031       break;
1032    case R200_CP_CMD_NEXT_CHAR:
1033       if (NORMAL)
1034          fprintf(stderr, "PACKET3_NEXT_CHAR, %d dwords\n", cmdsz);
1035       break;
1036    case R200_CP_CMD_PLY_NEXTSCAN:
1037       if (NORMAL)
1038          fprintf(stderr, "PACKET3_PLY_NEXTSCAN, %d dwords\n", cmdsz);
1039       break;
1040    case R200_CP_CMD_SET_SCISSORS:
1041       if (NORMAL)
1042          fprintf(stderr, "PACKET3_SET_SCISSORS, %d dwords\n", cmdsz);
1043       break;
1044    case R200_CP_CMD_LOAD_MICROCODE:
1045       if (NORMAL)
1046          fprintf(stderr, "PACKET3_LOAD_MICROCODE, %d dwords\n", cmdsz);
1047       break;
1048    case R200_CP_CMD_WAIT_FOR_IDLE:
1049       if (NORMAL)
1050          fprintf(stderr, "PACKET3_WAIT_FOR_IDLE, %d dwords\n", cmdsz);
1051       break;
1052
1053    case R200_CP_CMD_3D_DRAW_VBUF:
1054       if (NORMAL)
1055          fprintf(stderr, "PACKET3_3D_DRAW_VBUF, %d dwords\n", cmdsz);
1056 /*       print_vertex_format(cmd[1]); */
1057       if (print_prim_and_flags(cmd[2]))
1058          return -EINVAL;
1059       break;
1060
1061    case R200_CP_CMD_3D_DRAW_IMMD:
1062       if (NORMAL)
1063          fprintf(stderr, "PACKET3_3D_DRAW_IMMD, %d dwords\n", cmdsz);
1064       break;
1065    case R200_CP_CMD_3D_DRAW_INDX: {
1066       int neltdwords;
1067       if (NORMAL)
1068          fprintf(stderr, "PACKET3_3D_DRAW_INDX, %d dwords\n", cmdsz);
1069 /*       print_vertex_format(cmd[1]); */
1070       if (print_prim_and_flags(cmd[2]))
1071          return -EINVAL;
1072       neltdwords = cmd[2]>>16;
1073       neltdwords += neltdwords & 1;
1074       neltdwords /= 2;
1075       if (neltdwords + 3 != cmdsz)
1076          fprintf(stderr, "Mismatch in DRAW_INDX, %d vs cmdsz %d\n",
1077                  neltdwords, cmdsz);
1078       break;
1079    }
1080    case R200_CP_CMD_LOAD_PALETTE:
1081       if (NORMAL)
1082          fprintf(stderr, "PACKET3_LOAD_PALETTE, %d dwords\n", cmdsz);
1083       break;
1084    case R200_CP_CMD_3D_LOAD_VBPNTR:
1085       if (NORMAL) {
1086          fprintf(stderr, "PACKET3_3D_LOAD_VBPNTR, %d dwords\n", cmdsz);
1087          fprintf(stderr, "   nr arrays: %d\n", cmd[1]);
1088       }
1089
1090       if (((cmd[1]/2)*3) + ((cmd[1]%2)*2) != cmdsz - 2) {
1091          fprintf(stderr, "  ****** MISMATCH %d/%d *******\n",
1092                  ((cmd[1]/2)*3) + ((cmd[1]%2)*2) + 2, cmdsz);
1093          return -EINVAL;
1094       }
1095
1096       if (NORMAL) {
1097          tmp = cmd+2;
1098          for (i = 0 ; i < cmd[1] ; i++) {
1099             if (i & 1) {
1100                stride = (tmp[0]>>24) & 0xff;
1101                size = (tmp[0]>>16) & 0xff;
1102                start = tmp[2];
1103                tmp += 3;
1104             }
1105             else {
1106                stride = (tmp[0]>>8) & 0xff;
1107                size = (tmp[0]) & 0xff;
1108                start = tmp[1];
1109             }
1110             fprintf(stderr, "   array %d: start 0x%x vsize %d vstride %d\n",
1111                     i, start, size, stride );
1112          }
1113       }
1114       break;
1115    case R200_CP_CMD_PAINT:
1116       if (NORMAL)
1117          fprintf(stderr, "PACKET3_CNTL_PAINT, %d dwords\n", cmdsz);
1118       break;
1119    case R200_CP_CMD_BITBLT:
1120       if (NORMAL)
1121          fprintf(stderr, "PACKET3_CNTL_BITBLT, %d dwords\n", cmdsz);
1122       break;
1123    case R200_CP_CMD_SMALLTEXT:
1124       if (NORMAL)
1125          fprintf(stderr, "PACKET3_CNTL_SMALLTEXT, %d dwords\n", cmdsz);
1126       break;
1127    case R200_CP_CMD_HOSTDATA_BLT:
1128       if (NORMAL)
1129          fprintf(stderr, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n",
1130               cmdsz);
1131       break;
1132    case R200_CP_CMD_POLYLINE:
1133       if (NORMAL)
1134          fprintf(stderr, "PACKET3_CNTL_POLYLINE, %d dwords\n", cmdsz);
1135       break;
1136    case R200_CP_CMD_POLYSCANLINES:
1137       if (NORMAL)
1138          fprintf(stderr, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n",
1139               cmdsz);
1140       break;
1141    case R200_CP_CMD_PAINT_MULTI:
1142       if (NORMAL)
1143          fprintf(stderr, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n",
1144               cmdsz);
1145       break;
1146    case R200_CP_CMD_BITBLT_MULTI:
1147       if (NORMAL)
1148          fprintf(stderr, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n",
1149               cmdsz);
1150       break;
1151    case R200_CP_CMD_TRANS_BITBLT:
1152       if (NORMAL)
1153          fprintf(stderr, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n",
1154               cmdsz);
1155       break;
1156    case R200_CP_CMD_3D_DRAW_VBUF_2:
1157       if (NORMAL)
1158          fprintf(stderr, "R200_CP_CMD_3D_DRAW_VBUF_2, %d dwords\n",
1159               cmdsz);
1160       if (print_prim_and_flags(cmd[1]))
1161          return -EINVAL;
1162       break;
1163    case R200_CP_CMD_3D_DRAW_IMMD_2:
1164       if (NORMAL)
1165          fprintf(stderr, "R200_CP_CMD_3D_DRAW_IMMD_2, %d dwords\n",
1166               cmdsz);
1167       if (print_prim_and_flags(cmd[1]))
1168          return -EINVAL;
1169       break;
1170    case R200_CP_CMD_3D_DRAW_INDX_2:
1171       if (NORMAL)
1172          fprintf(stderr, "R200_CP_CMD_3D_DRAW_INDX_2, %d dwords\n",
1173               cmdsz);
1174       if (print_prim_and_flags(cmd[1]))
1175          return -EINVAL;
1176       break;
1177    default:
1178       fprintf(stderr, "UNKNOWN PACKET, %d dwords\n", cmdsz);
1179       break;
1180    }
1181
1182    cmdbuf->buf += cmdsz * 4;
1183    cmdbuf->bufsz -= cmdsz * 4;
1184    return 0;
1185 }
1186
1187
1188 /* Check cliprects for bounds, then pass on to above:
1189  */
1190 static int radeon_emit_packet3_cliprect( drmRadeonCmdBuffer *cmdbuf )
1191 {
1192    XF86DRIClipRectRec *boxes = (XF86DRIClipRectRec *)cmdbuf->boxes;
1193    int i = 0;
1194
1195    if (VERBOSE && total_changed) {
1196       dump_state();
1197       total_changed = 0;
1198    }
1199
1200    if (NORMAL) {
1201       do {
1202          if ( i < cmdbuf->nbox ) {
1203             fprintf(stderr, "Emit box %d/%d %d,%d %d,%d\n",
1204                     i, cmdbuf->nbox,
1205                     boxes[i].x1, boxes[i].y1, boxes[i].x2, boxes[i].y2);
1206          }
1207       } while ( ++i < cmdbuf->nbox );
1208    }
1209
1210    if (cmdbuf->nbox == 1)
1211       cmdbuf->nbox = 0;
1212
1213    return radeon_emit_packet3( cmdbuf );
1214 }
1215
1216
1217 int r200SanityCmdBuffer( r200ContextPtr rmesa,
1218                            int nbox,
1219                            XF86DRIClipRectRec *boxes )
1220 {
1221    int idx;
1222    drmRadeonCmdBuffer cmdbuf;
1223    drmRadeonCmdHeader header;
1224    static int inited = 0;
1225
1226    if (!inited) {
1227       init_regs();
1228       inited = 1;
1229    }
1230
1231
1232    cmdbuf.buf = rmesa->store.cmd_buf;
1233    cmdbuf.bufsz = rmesa->store.cmd_used;
1234    cmdbuf.boxes = (drmClipRect *)boxes;
1235    cmdbuf.nbox = nbox;
1236
1237    while ( cmdbuf.bufsz >= sizeof(header) ) {
1238
1239       header.i = *(int *)cmdbuf.buf;
1240       cmdbuf.buf += sizeof(header);
1241       cmdbuf.bufsz -= sizeof(header);
1242
1243       switch (header.header.cmd_type) {
1244       case RADEON_CMD_PACKET:
1245          if (radeon_emit_packets( header, &cmdbuf )) {
1246             fprintf(stderr,"radeon_emit_packets failed\n");
1247             return -EINVAL;
1248          }
1249          break;
1250
1251       case RADEON_CMD_SCALARS:
1252          if (radeon_emit_scalars( header, &cmdbuf )) {
1253             fprintf(stderr,"radeon_emit_scalars failed\n");
1254             return -EINVAL;
1255          }
1256          break;
1257
1258       case RADEON_CMD_SCALARS2:
1259          if (radeon_emit_scalars2( header, &cmdbuf )) {
1260             fprintf(stderr,"radeon_emit_scalars failed\n");
1261             return -EINVAL;
1262          }
1263          break;
1264
1265       case RADEON_CMD_VECTORS:
1266          if (radeon_emit_vectors( header, &cmdbuf )) {
1267             fprintf(stderr,"radeon_emit_vectors failed\n");
1268             return -EINVAL;
1269          }
1270          break;
1271
1272       case RADEON_CMD_DMA_DISCARD:
1273          idx = header.dma.buf_idx;
1274          if (NORMAL)
1275             fprintf(stderr, "RADEON_CMD_DMA_DISCARD buf %d\n", idx);
1276          bufs++;
1277          break;
1278
1279       case RADEON_CMD_PACKET3:
1280          if (radeon_emit_packet3( &cmdbuf )) {
1281             fprintf(stderr,"radeon_emit_packet3 failed\n");
1282             return -EINVAL;
1283          }
1284          break;
1285
1286       case RADEON_CMD_PACKET3_CLIP:
1287          if (radeon_emit_packet3_cliprect( &cmdbuf )) {
1288             fprintf(stderr,"radeon_emit_packet3_clip failed\n");
1289             return -EINVAL;
1290          }
1291          break;
1292
1293       case RADEON_CMD_WAIT:
1294          break;
1295
1296       default:
1297          fprintf(stderr,"bad cmd_type %d at %p\n",
1298                    header.header.cmd_type,
1299                    cmdbuf.buf - sizeof(header));
1300          return -EINVAL;
1301       }
1302    }
1303
1304    if (0)
1305    {
1306       static int n = 0;
1307       n++;
1308       if (n == 10) {
1309          fprintf(stderr, "Bufs %d Total emitted %d real changes %d (%.2f%%)\n",
1310                  bufs,
1311                  total, total_changed,
1312                  ((float)total_changed/(float)total*100.0));
1313          fprintf(stderr, "Total emitted per buf: %.2f\n",
1314                  (float)total/(float)bufs);
1315          fprintf(stderr, "Real changes per buf: %.2f\n",
1316                  (float)total_changed/(float)bufs);
1317
1318          bufs = n = total = total_changed = 0;
1319       }
1320    }
1321
1322    fprintf(stderr, "leaving %s\n\n\n", __FUNCTION__);
1323
1324    return 0;
1325 }