src/mesa/drivers/dri/r200/r200_sanity.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_sanity.c,v 1.1 2002/10/30 12:51:52 alanh Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
   5                      Tungsten Graphics Inc, Cedar Park, TX.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining a
  10 copy of this software and associated documentation files (the "Software"),
  11 to deal in the Software without restriction, including without limitation
  12 on the rights to use, copy, modify, merge, publish, distribute, sub
  13 license, and/or sell copies of the Software, and to permit persons to whom
  14 the Software is furnished to do so, subject to the following conditions:
  15
  16 The above copyright notice and this permission notice (including the next
  17 paragraph) shall be included in all copies or substantial portions of the
  18 Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  23 ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  24 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  25 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  26 USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *
  34  */
  35
  36 #include <errno.h>
  37
  38 #include "glheader.h"
  39 #include "imports.h"
  40
  41 #include "r200_context.h"
  42 #include "r200_ioctl.h"
  43 #include "r200_sanity.h"
  44 #include "radeon_reg.h"
  45 #include "r200_reg.h"
  46
  47 /* Set this '1' to get more verbiage.
  48  */
  49 #define MORE_VERBOSE 1
  50
  51 #if MORE_VERBOSE
  52 #define VERBOSE (R200_DEBUG & DEBUG_VERBOSE)
  53 #define NORMAL  (1)
  54 #else
  55 #define VERBOSE 0
  56 #define NORMAL  (R200_DEBUG & DEBUG_VERBOSE)
  57 #endif
  58
  59
  60 /* New (1.3) state mechanism.  3 commands (packet, scalar, vector) in
  61  * 1.3 cmdbuffers allow all previous state to be updated as well as
  62  * the tcl scalar and vector areas.
  63  */
  64 static struct {
  65    int start;
  66    int len;
  67    const char *name;
  68 } packet[RADEON_MAX_STATE_PACKETS] = {
  69    { RADEON_PP_MISC,7,"RADEON_PP_MISC" },
  70    { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
  71    { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
  72    { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
  73    { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
  74    { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
  75    { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
  76    { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
  77    { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
  78    { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
  79    { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
  80    { RADEON_RE_MISC,1,"RADEON_RE_MISC" },
  81    { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
  82    { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
  83    { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
  84    { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
  85    { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
  86    { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
  87    { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
  88    { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
  89    { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
  90    { R200_PP_TXCBLEND_0, 4, "R200_EMIT_PP_TXCBLEND_0" },
  91    { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" },
  92    { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" },
  93    { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" },
  94    { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" },
  95    { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" },
  96    { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" },
  97    { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" },
  98    { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
  99    { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" },
 100    { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" },
 101    { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" },
 102    { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" },
 103    { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
 104    { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
 105    { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" },
 106    { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" },
 107    { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" },
 108    { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" },
 109    { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" },
 110    { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" },
 111    { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" },
 112    { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" },
 113    { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" },
 114    { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" },
 115    { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" },
 116    { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" },
 117    { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" },
 118    { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
 119    { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" },
 120    { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" },
 121    { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" },
 122    { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" },
 123    { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" },
 124    { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" },
 125    { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" },
 126    { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" },
 127    { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" },
 128    { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" },
 129    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
 130    { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */
 131    { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */
 132    { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" },
 133    { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" },
 134    { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" },
 135    { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" },
 136    { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" },
 137    { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" },
 138    { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" },
 139    { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
 140    { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
 141    { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
 142 };
 143
 144 struct reg_names {
 145    int idx;
 146    const char *name;
 147 };
 148
 149 static struct reg_names reg_names[] = {
 150    { R200_PP_MISC, "R200_PP_MISC" },
 151    { R200_PP_FOG_COLOR, "R200_PP_FOG_COLOR" },
 152    { R200_RE_SOLID_COLOR, "R200_RE_SOLID_COLOR" },
 153    { R200_RB3D_BLENDCNTL, "R200_RB3D_BLENDCNTL" },
 154    { R200_RB3D_DEPTHOFFSET, "R200_RB3D_DEPTHOFFSET" },
 155    { R200_RB3D_DEPTHPITCH, "R200_RB3D_DEPTHPITCH" },
 156    { R200_RB3D_ZSTENCILCNTL, "R200_RB3D_ZSTENCILCNTL" },
 157    { R200_PP_CNTL, "R200_PP_CNTL" },
 158    { R200_RB3D_CNTL, "R200_RB3D_CNTL" },
 159    { R200_RB3D_COLOROFFSET, "R200_RB3D_COLOROFFSET" },
 160    { R200_RE_WIDTH_HEIGHT, "R200_RE_WIDTH_HEIGHT" },
 161    { R200_RB3D_COLORPITCH, "R200_RB3D_COLORPITCH" },
 162    { R200_SE_CNTL, "R200_SE_CNTL" },
 163    { R200_RE_CNTL, "R200_RE_CNTL" },
 164    { R200_RE_MISC, "R200_RE_MISC" },
 165    { R200_RE_STIPPLE_ADDR, "R200_RE_STIPPLE_ADDR" },
 166    { R200_RE_STIPPLE_DATA, "R200_RE_STIPPLE_DATA" },
 167    { R200_RE_LINE_PATTERN, "R200_RE_LINE_PATTERN" },
 168    { R200_RE_LINE_STATE, "R200_RE_LINE_STATE" },
 169    { R200_RE_SCISSOR_TL_0, "R200_RE_SCISSOR_TL_0" },
 170    { R200_RE_SCISSOR_BR_0, "R200_RE_SCISSOR_BR_0" },
 171    { R200_RE_SCISSOR_TL_1, "R200_RE_SCISSOR_TL_1" },
 172    { R200_RE_SCISSOR_BR_1, "R200_RE_SCISSOR_BR_1" },
 173    { R200_RE_SCISSOR_TL_2, "R200_RE_SCISSOR_TL_2" },
 174    { R200_RE_SCISSOR_BR_2, "R200_RE_SCISSOR_BR_2" },
 175    { R200_RB3D_DEPTHXY_OFFSET, "R200_RB3D_DEPTHXY_OFFSET" },
 176    { R200_RB3D_STENCILREFMASK, "R200_RB3D_STENCILREFMASK" },
 177    { R200_RB3D_ROPCNTL, "R200_RB3D_ROPCNTL" },
 178    { R200_RB3D_PLANEMASK, "R200_RB3D_PLANEMASK" },
 179    { R200_SE_VPORT_XSCALE, "R200_SE_VPORT_XSCALE" },
 180    { R200_SE_VPORT_XOFFSET, "R200_SE_VPORT_XOFFSET" },
 181    { R200_SE_VPORT_YSCALE, "R200_SE_VPORT_YSCALE" },
 182    { R200_SE_VPORT_YOFFSET, "R200_SE_VPORT_YOFFSET" },
 183    { R200_SE_VPORT_ZSCALE, "R200_SE_VPORT_ZSCALE" },
 184    { R200_SE_VPORT_ZOFFSET, "R200_SE_VPORT_ZOFFSET" },
 185    { R200_SE_ZBIAS_FACTOR, "R200_SE_ZBIAS_FACTOR" },
 186    { R200_SE_ZBIAS_CONSTANT, "R200_SE_ZBIAS_CONSTANT" },
 187    { R200_SE_LINE_WIDTH, "R200_SE_LINE_WIDTH" },
 188    { R200_SE_VAP_CNTL, "R200_SE_VAP_CNTL" },
 189    { R200_SE_VF_CNTL, "R200_SE_VF_CNTL" },
 190    { R200_SE_VTX_FMT_0, "R200_SE_VTX_FMT_0" },
 191    { R200_SE_VTX_FMT_1, "R200_SE_VTX_FMT_1" },
 192    { R200_SE_TCL_OUTPUT_VTX_FMT_0, "R200_SE_TCL_OUTPUT_VTX_FMT_0" },
 193    { R200_SE_TCL_OUTPUT_VTX_FMT_1, "R200_SE_TCL_OUTPUT_VTX_FMT_1" },
 194    { R200_SE_VTE_CNTL, "R200_SE_VTE_CNTL" },
 195    { R200_SE_VTX_NUM_ARRAYS, "R200_SE_VTX_NUM_ARRAYS" },
 196    { R200_SE_VTX_AOS_ATTR01, "R200_SE_VTX_AOS_ATTR01" },
 197    { R200_SE_VTX_AOS_ADDR0, "R200_SE_VTX_AOS_ADDR0" },
 198    { R200_SE_VTX_AOS_ADDR1, "R200_SE_VTX_AOS_ADDR1" },
 199    { R200_SE_VTX_AOS_ATTR23, "R200_SE_VTX_AOS_ATTR23" },
 200    { R200_SE_VTX_AOS_ADDR2, "R200_SE_VTX_AOS_ADDR2" },
 201    { R200_SE_VTX_AOS_ADDR3, "R200_SE_VTX_AOS_ADDR3" },
 202    { R200_SE_VTX_AOS_ATTR45, "R200_SE_VTX_AOS_ATTR45" },
 203    { R200_SE_VTX_AOS_ADDR4, "R200_SE_VTX_AOS_ADDR4" },
 204    { R200_SE_VTX_AOS_ADDR5, "R200_SE_VTX_AOS_ADDR5" },
 205    { R200_SE_VTX_AOS_ATTR67, "R200_SE_VTX_AOS_ATTR67" },
 206    { R200_SE_VTX_AOS_ADDR6, "R200_SE_VTX_AOS_ADDR6" },
 207    { R200_SE_VTX_AOS_ADDR7, "R200_SE_VTX_AOS_ADDR7" },
 208    { R200_SE_VTX_AOS_ATTR89, "R200_SE_VTX_AOS_ATTR89" },
 209    { R200_SE_VTX_AOS_ADDR8, "R200_SE_VTX_AOS_ADDR8" },
 210    { R200_SE_VTX_AOS_ADDR9, "R200_SE_VTX_AOS_ADDR9" },
 211    { R200_SE_VTX_AOS_ATTR1011, "R200_SE_VTX_AOS_ATTR1011" },
 212    { R200_SE_VTX_AOS_ADDR10, "R200_SE_VTX_AOS_ADDR10" },
 213    { R200_SE_VTX_AOS_ADDR11, "R200_SE_VTX_AOS_ADDR11" },
 214    { R200_SE_VF_MAX_VTX_INDX, "R200_SE_VF_MAX_VTX_INDX" },
 215    { R200_SE_VF_MIN_VTX_INDX, "R200_SE_VF_MIN_VTX_INDX" },
 216    { R200_SE_VTX_STATE_CNTL, "R200_SE_VTX_STATE_CNTL" },
 217    { R200_SE_TCL_VECTOR_INDX_REG, "R200_SE_TCL_VECTOR_INDX_REG" },
 218    { R200_SE_TCL_VECTOR_DATA_REG, "R200_SE_TCL_VECTOR_DATA_REG" },
 219    { R200_SE_TCL_SCALAR_INDX_REG, "R200_SE_TCL_SCALAR_INDX_REG" },
 220    { R200_SE_TCL_SCALAR_DATA_REG, "R200_SE_TCL_SCALAR_DATA_REG" },
 221    { R200_SE_TCL_MATRIX_SEL_0, "R200_SE_TCL_MATRIX_SEL_0" },
 222    { R200_SE_TCL_MATRIX_SEL_1, "R200_SE_TCL_MATRIX_SEL_1" },
 223    { R200_SE_TCL_MATRIX_SEL_2, "R200_SE_TCL_MATRIX_SEL_2" },
 224    { R200_SE_TCL_MATRIX_SEL_3, "R200_SE_TCL_MATRIX_SEL_3" },
 225    { R200_SE_TCL_MATRIX_SEL_4, "R200_SE_TCL_MATRIX_SEL_4" },
 226    { R200_SE_TCL_LIGHT_MODEL_CTL_0, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
 227    { R200_SE_TCL_LIGHT_MODEL_CTL_1, "R200_SE_TCL_LIGHT_MODEL_CTL_1" },
 228    { R200_SE_TCL_PER_LIGHT_CTL_0, "R200_SE_TCL_PER_LIGHT_CTL_0" },
 229    { R200_SE_TCL_PER_LIGHT_CTL_1, "R200_SE_TCL_PER_LIGHT_CTL_1" },
 230    { R200_SE_TCL_PER_LIGHT_CTL_2, "R200_SE_TCL_PER_LIGHT_CTL_2" },
 231    { R200_SE_TCL_PER_LIGHT_CTL_3, "R200_SE_TCL_PER_LIGHT_CTL_3" },
 232    { R200_SE_TCL_TEX_PROC_CTL_2, "R200_SE_TCL_TEX_PROC_CTL_2" },
 233    { R200_SE_TCL_TEX_PROC_CTL_3, "R200_SE_TCL_TEX_PROC_CTL_3" },
 234    { R200_SE_TCL_TEX_PROC_CTL_0, "R200_SE_TCL_TEX_PROC_CTL_0" },
 235    { R200_SE_TCL_TEX_PROC_CTL_1, "R200_SE_TCL_TEX_PROC_CTL_1" },
 236    { R200_SE_TC_TEX_CYL_WRAP_CTL, "R200_SE_TC_TEX_CYL_WRAP_CTL" },
 237    { R200_SE_TCL_UCP_VERT_BLEND_CTL, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
 238    { R200_SE_TCL_POINT_SPRITE_CNTL, "R200_SE_TCL_POINT_SPRITE_CNTL" },
 239    { R200_SE_VTX_ST_POS_0_X_4, "R200_SE_VTX_ST_POS_0_X_4" },
 240    { R200_SE_VTX_ST_POS_0_Y_4, "R200_SE_VTX_ST_POS_0_Y_4" },
 241    { R200_SE_VTX_ST_POS_0_Z_4, "R200_SE_VTX_ST_POS_0_Z_4" },
 242    { R200_SE_VTX_ST_POS_0_W_4, "R200_SE_VTX_ST_POS_0_W_4" },
 243    { R200_SE_VTX_ST_NORM_0_X, "R200_SE_VTX_ST_NORM_0_X" },
 244    { R200_SE_VTX_ST_NORM_0_Y, "R200_SE_VTX_ST_NORM_0_Y" },
 245    { R200_SE_VTX_ST_NORM_0_Z, "R200_SE_VTX_ST_NORM_0_Z" },
 246    { R200_SE_VTX_ST_PVMS, "R200_SE_VTX_ST_PVMS" },
 247    { R200_SE_VTX_ST_CLR_0_R, "R200_SE_VTX_ST_CLR_0_R" },
 248    { R200_SE_VTX_ST_CLR_0_G, "R200_SE_VTX_ST_CLR_0_G" },
 249    { R200_SE_VTX_ST_CLR_0_B, "R200_SE_VTX_ST_CLR_0_B" },
 250    { R200_SE_VTX_ST_CLR_0_A, "R200_SE_VTX_ST_CLR_0_A" },
 251    { R200_SE_VTX_ST_CLR_1_R, "R200_SE_VTX_ST_CLR_1_R" },
 252    { R200_SE_VTX_ST_CLR_1_G, "R200_SE_VTX_ST_CLR_1_G" },
 253    { R200_SE_VTX_ST_CLR_1_B, "R200_SE_VTX_ST_CLR_1_B" },
 254    { R200_SE_VTX_ST_CLR_1_A, "R200_SE_VTX_ST_CLR_1_A" },
 255    { R200_SE_VTX_ST_CLR_2_R, "R200_SE_VTX_ST_CLR_2_R" },
 256    { R200_SE_VTX_ST_CLR_2_G, "R200_SE_VTX_ST_CLR_2_G" },
 257    { R200_SE_VTX_ST_CLR_2_B, "R200_SE_VTX_ST_CLR_2_B" },
 258    { R200_SE_VTX_ST_CLR_2_A, "R200_SE_VTX_ST_CLR_2_A" },
 259    { R200_SE_VTX_ST_CLR_3_R, "R200_SE_VTX_ST_CLR_3_R" },
 260    { R200_SE_VTX_ST_CLR_3_G, "R200_SE_VTX_ST_CLR_3_G" },
 261    { R200_SE_VTX_ST_CLR_3_B, "R200_SE_VTX_ST_CLR_3_B" },
 262    { R200_SE_VTX_ST_CLR_3_A, "R200_SE_VTX_ST_CLR_3_A" },
 263    { R200_SE_VTX_ST_CLR_4_R, "R200_SE_VTX_ST_CLR_4_R" },
 264    { R200_SE_VTX_ST_CLR_4_G, "R200_SE_VTX_ST_CLR_4_G" },
 265    { R200_SE_VTX_ST_CLR_4_B, "R200_SE_VTX_ST_CLR_4_B" },
 266    { R200_SE_VTX_ST_CLR_4_A, "R200_SE_VTX_ST_CLR_4_A" },
 267    { R200_SE_VTX_ST_CLR_5_R, "R200_SE_VTX_ST_CLR_5_R" },
 268    { R200_SE_VTX_ST_CLR_5_G, "R200_SE_VTX_ST_CLR_5_G" },
 269    { R200_SE_VTX_ST_CLR_5_B, "R200_SE_VTX_ST_CLR_5_B" },
 270    { R200_SE_VTX_ST_CLR_5_A, "R200_SE_VTX_ST_CLR_5_A" },
 271    { R200_SE_VTX_ST_CLR_6_R, "R200_SE_VTX_ST_CLR_6_R" },
 272    { R200_SE_VTX_ST_CLR_6_G, "R200_SE_VTX_ST_CLR_6_G" },
 273    { R200_SE_VTX_ST_CLR_6_B, "R200_SE_VTX_ST_CLR_6_B" },
 274    { R200_SE_VTX_ST_CLR_6_A, "R200_SE_VTX_ST_CLR_6_A" },
 275    { R200_SE_VTX_ST_CLR_7_R, "R200_SE_VTX_ST_CLR_7_R" },
 276    { R200_SE_VTX_ST_CLR_7_G, "R200_SE_VTX_ST_CLR_7_G" },
 277    { R200_SE_VTX_ST_CLR_7_B, "R200_SE_VTX_ST_CLR_7_B" },
 278    { R200_SE_VTX_ST_CLR_7_A, "R200_SE_VTX_ST_CLR_7_A" },
 279    { R200_SE_VTX_ST_TEX_0_S, "R200_SE_VTX_ST_TEX_0_S" },
 280    { R200_SE_VTX_ST_TEX_0_T, "R200_SE_VTX_ST_TEX_0_T" },
 281    { R200_SE_VTX_ST_TEX_0_R, "R200_SE_VTX_ST_TEX_0_R" },
 282    { R200_SE_VTX_ST_TEX_0_Q, "R200_SE_VTX_ST_TEX_0_Q" },
 283    { R200_SE_VTX_ST_TEX_1_S, "R200_SE_VTX_ST_TEX_1_S" },
 284    { R200_SE_VTX_ST_TEX_1_T, "R200_SE_VTX_ST_TEX_1_T" },
 285    { R200_SE_VTX_ST_TEX_1_R, "R200_SE_VTX_ST_TEX_1_R" },
 286    { R200_SE_VTX_ST_TEX_1_Q, "R200_SE_VTX_ST_TEX_1_Q" },
 287    { R200_SE_VTX_ST_TEX_2_S, "R200_SE_VTX_ST_TEX_2_S" },
 288    { R200_SE_VTX_ST_TEX_2_T, "R200_SE_VTX_ST_TEX_2_T" },
 289    { R200_SE_VTX_ST_TEX_2_R, "R200_SE_VTX_ST_TEX_2_R" },
 290    { R200_SE_VTX_ST_TEX_2_Q, "R200_SE_VTX_ST_TEX_2_Q" },
 291    { R200_SE_VTX_ST_TEX_3_S, "R200_SE_VTX_ST_TEX_3_S" },
 292    { R200_SE_VTX_ST_TEX_3_T, "R200_SE_VTX_ST_TEX_3_T" },
 293    { R200_SE_VTX_ST_TEX_3_R, "R200_SE_VTX_ST_TEX_3_R" },
 294    { R200_SE_VTX_ST_TEX_3_Q, "R200_SE_VTX_ST_TEX_3_Q" },
 295    { R200_SE_VTX_ST_TEX_4_S, "R200_SE_VTX_ST_TEX_4_S" },
 296    { R200_SE_VTX_ST_TEX_4_T, "R200_SE_VTX_ST_TEX_4_T" },
 297    { R200_SE_VTX_ST_TEX_4_R, "R200_SE_VTX_ST_TEX_4_R" },
 298    { R200_SE_VTX_ST_TEX_4_Q, "R200_SE_VTX_ST_TEX_4_Q" },
 299    { R200_SE_VTX_ST_TEX_5_S, "R200_SE_VTX_ST_TEX_5_S" },
 300    { R200_SE_VTX_ST_TEX_5_T, "R200_SE_VTX_ST_TEX_5_T" },
 301    { R200_SE_VTX_ST_TEX_5_R, "R200_SE_VTX_ST_TEX_5_R" },
 302    { R200_SE_VTX_ST_TEX_5_Q, "R200_SE_VTX_ST_TEX_5_Q" },
 303    { R200_SE_VTX_ST_PNT_SPRT_SZ, "R200_SE_VTX_ST_PNT_SPRT_SZ" },
 304    { R200_SE_VTX_ST_DISC_FOG, "R200_SE_VTX_ST_DISC_FOG" },
 305    { R200_SE_VTX_ST_SHININESS_0, "R200_SE_VTX_ST_SHININESS_0" },
 306    { R200_SE_VTX_ST_SHININESS_1, "R200_SE_VTX_ST_SHININESS_1" },
 307    { R200_SE_VTX_ST_BLND_WT_0, "R200_SE_VTX_ST_BLND_WT_0" },
 308    { R200_SE_VTX_ST_BLND_WT_1, "R200_SE_VTX_ST_BLND_WT_1" },
 309    { R200_SE_VTX_ST_BLND_WT_2, "R200_SE_VTX_ST_BLND_WT_2" },
 310    { R200_SE_VTX_ST_BLND_WT_3, "R200_SE_VTX_ST_BLND_WT_3" },
 311    { R200_SE_VTX_ST_POS_1_X, "R200_SE_VTX_ST_POS_1_X" },
 312    { R200_SE_VTX_ST_POS_1_Y, "R200_SE_VTX_ST_POS_1_Y" },
 313    { R200_SE_VTX_ST_POS_1_Z, "R200_SE_VTX_ST_POS_1_Z" },
 314    { R200_SE_VTX_ST_POS_1_W, "R200_SE_VTX_ST_POS_1_W" },
 315    { R200_SE_VTX_ST_NORM_1_X, "R200_SE_VTX_ST_NORM_1_X" },
 316    { R200_SE_VTX_ST_NORM_1_Y, "R200_SE_VTX_ST_NORM_1_Y" },
 317    { R200_SE_VTX_ST_NORM_1_Z, "R200_SE_VTX_ST_NORM_1_Z" },
 318    { R200_SE_VTX_ST_USR_CLR_0_R, "R200_SE_VTX_ST_USR_CLR_0_R" },
 319    { R200_SE_VTX_ST_USR_CLR_0_G, "R200_SE_VTX_ST_USR_CLR_0_G" },
 320    { R200_SE_VTX_ST_USR_CLR_0_B, "R200_SE_VTX_ST_USR_CLR_0_B" },
 321    { R200_SE_VTX_ST_USR_CLR_0_A, "R200_SE_VTX_ST_USR_CLR_0_A" },
 322    { R200_SE_VTX_ST_USR_CLR_1_R, "R200_SE_VTX_ST_USR_CLR_1_R" },
 323    { R200_SE_VTX_ST_USR_CLR_1_G, "R200_SE_VTX_ST_USR_CLR_1_G" },
 324    { R200_SE_VTX_ST_USR_CLR_1_B, "R200_SE_VTX_ST_USR_CLR_1_B" },
 325    { R200_SE_VTX_ST_USR_CLR_1_A, "R200_SE_VTX_ST_USR_CLR_1_A" },
 326    { R200_SE_VTX_ST_CLR_0_PKD, "R200_SE_VTX_ST_CLR_0_PKD" },
 327    { R200_SE_VTX_ST_CLR_1_PKD, "R200_SE_VTX_ST_CLR_1_PKD" },
 328    { R200_SE_VTX_ST_CLR_2_PKD, "R200_SE_VTX_ST_CLR_2_PKD" },
 329    { R200_SE_VTX_ST_CLR_3_PKD, "R200_SE_VTX_ST_CLR_3_PKD" },
 330    { R200_SE_VTX_ST_CLR_4_PKD, "R200_SE_VTX_ST_CLR_4_PKD" },
 331    { R200_SE_VTX_ST_CLR_5_PKD, "R200_SE_VTX_ST_CLR_5_PKD" },
 332    { R200_SE_VTX_ST_CLR_6_PKD, "R200_SE_VTX_ST_CLR_6_PKD" },
 333    { R200_SE_VTX_ST_CLR_7_PKD, "R200_SE_VTX_ST_CLR_7_PKD" },
 334    { R200_SE_VTX_ST_POS_0_X_2, "R200_SE_VTX_ST_POS_0_X_2" },
 335    { R200_SE_VTX_ST_POS_0_Y_2, "R200_SE_VTX_ST_POS_0_Y_2" },
 336    { R200_SE_VTX_ST_PAR_CLR_LD, "R200_SE_VTX_ST_PAR_CLR_LD" },
 337    { R200_SE_VTX_ST_USR_CLR_PKD, "R200_SE_VTX_ST_USR_CLR_PKD" },
 338    { R200_SE_VTX_ST_POS_0_X_3, "R200_SE_VTX_ST_POS_0_X_3" },
 339    { R200_SE_VTX_ST_POS_0_Y_3, "R200_SE_VTX_ST_POS_0_Y_3" },
 340    { R200_SE_VTX_ST_POS_0_Z_3, "R200_SE_VTX_ST_POS_0_Z_3" },
 341    { R200_SE_VTX_ST_END_OF_PKT, "R200_SE_VTX_ST_END_OF_PKT" },
 342    { R200_RE_POINTSIZE, "R200_RE_POINTSIZE" },
 343    { R200_RE_TOP_LEFT, "R200_RE_TOP_LEFT" },
 344    { R200_RE_AUX_SCISSOR_CNTL, "R200_RE_AUX_SCISSOR_CNTL" },
 345    { R200_PP_TXFILTER_0, "R200_PP_TXFILTER_0" },
 346    { R200_PP_TXFORMAT_0, "R200_PP_TXFORMAT_0" },
 347    { R200_PP_TXSIZE_0, "R200_PP_TXSIZE_0" },
 348    { R200_PP_TXFORMAT_X_0, "R200_PP_TXFORMAT_X_0" },
 349    { R200_PP_TXPITCH_0, "R200_PP_TXPITCH_0" },
 350    { R200_PP_BORDER_COLOR_0, "R200_PP_BORDER_COLOR_0" },
 351    { R200_PP_CUBIC_FACES_0, "R200_PP_CUBIC_FACES_0" },
 352    { R200_PP_TXFILTER_1, "R200_PP_TXFILTER_1" },
 353    { R200_PP_TXFORMAT_1, "R200_PP_TXFORMAT_1" },
 354    { R200_PP_TXSIZE_1, "R200_PP_TXSIZE_1" },
 355    { R200_PP_TXFORMAT_X_1, "R200_PP_TXFORMAT_X_1" },
 356    { R200_PP_TXPITCH_1, "R200_PP_TXPITCH_1" },
 357    { R200_PP_BORDER_COLOR_1, "R200_PP_BORDER_COLOR_1" },
 358    { R200_PP_CUBIC_FACES_1, "R200_PP_CUBIC_FACES_1" },
 359    { R200_PP_TXFILTER_2, "R200_PP_TXFILTER_2" },
 360    { R200_PP_TXFORMAT_2, "R200_PP_TXFORMAT_2" },
 361    { R200_PP_TXSIZE_2, "R200_PP_TXSIZE_2" },
 362    { R200_PP_TXFORMAT_X_2, "R200_PP_TXFORMAT_X_2" },
 363    { R200_PP_TXPITCH_2, "R200_PP_TXPITCH_2" },
 364    { R200_PP_BORDER_COLOR_2, "R200_PP_BORDER_COLOR_2" },
 365    { R200_PP_CUBIC_FACES_2, "R200_PP_CUBIC_FACES_2" },
 366    { R200_PP_TXFILTER_3, "R200_PP_TXFILTER_3" },
 367    { R200_PP_TXFORMAT_3, "R200_PP_TXFORMAT_3" },
 368    { R200_PP_TXSIZE_3, "R200_PP_TXSIZE_3" },
 369    { R200_PP_TXFORMAT_X_3, "R200_PP_TXFORMAT_X_3" },
 370    { R200_PP_TXPITCH_3, "R200_PP_TXPITCH_3" },
 371    { R200_PP_BORDER_COLOR_3, "R200_PP_BORDER_COLOR_3" },
 372    { R200_PP_CUBIC_FACES_3, "R200_PP_CUBIC_FACES_3" },
 373    { R200_PP_TXFILTER_4, "R200_PP_TXFILTER_4" },
 374    { R200_PP_TXFORMAT_4, "R200_PP_TXFORMAT_4" },
 375    { R200_PP_TXSIZE_4, "R200_PP_TXSIZE_4" },
 376    { R200_PP_TXFORMAT_X_4, "R200_PP_TXFORMAT_X_4" },
 377    { R200_PP_TXPITCH_4, "R200_PP_TXPITCH_4" },
 378    { R200_PP_BORDER_COLOR_4, "R200_PP_BORDER_COLOR_4" },
 379    { R200_PP_CUBIC_FACES_4, "R200_PP_CUBIC_FACES_4" },
 380    { R200_PP_TXFILTER_5, "R200_PP_TXFILTER_5" },
 381    { R200_PP_TXFORMAT_5, "R200_PP_TXFORMAT_5" },
 382    { R200_PP_TXSIZE_5, "R200_PP_TXSIZE_5" },
 383    { R200_PP_TXFORMAT_X_5, "R200_PP_TXFORMAT_X_5" },
 384    { R200_PP_TXPITCH_5, "R200_PP_TXPITCH_5" },
 385    { R200_PP_BORDER_COLOR_5, "R200_PP_BORDER_COLOR_5" },
 386    { R200_PP_CUBIC_FACES_5, "R200_PP_CUBIC_FACES_5" },
 387    { R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" },
 388    { R200_PP_CUBIC_OFFSET_F1_0, "R200_PP_CUBIC_OFFSET_F1_0" },
 389    { R200_PP_CUBIC_OFFSET_F2_0, "R200_PP_CUBIC_OFFSET_F2_0" },
 390    { R200_PP_CUBIC_OFFSET_F3_0, "R200_PP_CUBIC_OFFSET_F3_0" },
 391    { R200_PP_CUBIC_OFFSET_F4_0, "R200_PP_CUBIC_OFFSET_F4_0" },
 392    { R200_PP_CUBIC_OFFSET_F5_0, "R200_PP_CUBIC_OFFSET_F5_0" },
 393    { R200_PP_TXOFFSET_1, "R200_PP_TXOFFSET_1" },
 394    { R200_PP_CUBIC_OFFSET_F1_1, "R200_PP_CUBIC_OFFSET_F1_1" },
 395    { R200_PP_CUBIC_OFFSET_F2_1, "R200_PP_CUBIC_OFFSET_F2_1" },
 396    { R200_PP_CUBIC_OFFSET_F3_1, "R200_PP_CUBIC_OFFSET_F3_1" },
 397    { R200_PP_CUBIC_OFFSET_F4_1, "R200_PP_CUBIC_OFFSET_F4_1" },
 398    { R200_PP_CUBIC_OFFSET_F5_1, "R200_PP_CUBIC_OFFSET_F5_1" },
 399    { R200_PP_TXOFFSET_2, "R200_PP_TXOFFSET_2" },
 400    { R200_PP_CUBIC_OFFSET_F1_2, "R200_PP_CUBIC_OFFSET_F1_2" },
 401    { R200_PP_CUBIC_OFFSET_F2_2, "R200_PP_CUBIC_OFFSET_F2_2" },
 402    { R200_PP_CUBIC_OFFSET_F3_2, "R200_PP_CUBIC_OFFSET_F3_2" },
 403    { R200_PP_CUBIC_OFFSET_F4_2, "R200_PP_CUBIC_OFFSET_F4_2" },
 404    { R200_PP_CUBIC_OFFSET_F5_2, "R200_PP_CUBIC_OFFSET_F5_2" },
 405    { R200_PP_TXOFFSET_3, "R200_PP_TXOFFSET_3" },
 406    { R200_PP_CUBIC_OFFSET_F1_3, "R200_PP_CUBIC_OFFSET_F1_3" },
 407    { R200_PP_CUBIC_OFFSET_F2_3, "R200_PP_CUBIC_OFFSET_F2_3" },
 408    { R200_PP_CUBIC_OFFSET_F3_3, "R200_PP_CUBIC_OFFSET_F3_3" },
 409    { R200_PP_CUBIC_OFFSET_F4_3, "R200_PP_CUBIC_OFFSET_F4_3" },
 410    { R200_PP_CUBIC_OFFSET_F5_3, "R200_PP_CUBIC_OFFSET_F5_3" },
 411    { R200_PP_TXOFFSET_4, "R200_PP_TXOFFSET_4" },
 412    { R200_PP_CUBIC_OFFSET_F1_4, "R200_PP_CUBIC_OFFSET_F1_4" },
 413    { R200_PP_CUBIC_OFFSET_F2_4, "R200_PP_CUBIC_OFFSET_F2_4" },
 414    { R200_PP_CUBIC_OFFSET_F3_4, "R200_PP_CUBIC_OFFSET_F3_4" },
 415    { R200_PP_CUBIC_OFFSET_F4_4, "R200_PP_CUBIC_OFFSET_F4_4" },
 416    { R200_PP_CUBIC_OFFSET_F5_4, "R200_PP_CUBIC_OFFSET_F5_4" },
 417    { R200_PP_TXOFFSET_5, "R200_PP_TXOFFSET_5" },
 418    { R200_PP_CUBIC_OFFSET_F1_5, "R200_PP_CUBIC_OFFSET_F1_5" },
 419    { R200_PP_CUBIC_OFFSET_F2_5, "R200_PP_CUBIC_OFFSET_F2_5" },
 420    { R200_PP_CUBIC_OFFSET_F3_5, "R200_PP_CUBIC_OFFSET_F3_5" },
 421    { R200_PP_CUBIC_OFFSET_F4_5, "R200_PP_CUBIC_OFFSET_F4_5" },
 422    { R200_PP_CUBIC_OFFSET_F5_5, "R200_PP_CUBIC_OFFSET_F5_5" },
 423    { R200_PP_TAM_DEBUG3, "R200_PP_TAM_DEBUG3" },
 424    { R200_PP_TFACTOR_0, "R200_PP_TFACTOR_0" },
 425    { R200_PP_TFACTOR_1, "R200_PP_TFACTOR_1" },
 426    { R200_PP_TFACTOR_2, "R200_PP_TFACTOR_2" },
 427    { R200_PP_TFACTOR_3, "R200_PP_TFACTOR_3" },
 428    { R200_PP_TFACTOR_4, "R200_PP_TFACTOR_4" },
 429    { R200_PP_TFACTOR_5, "R200_PP_TFACTOR_5" },
 430    { R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" },
 431    { R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" },
 432    { R200_PP_TXABLEND_0, "R200_PP_TXABLEND_0" },
 433    { R200_PP_TXABLEND2_0, "R200_PP_TXABLEND2_0" },
 434    { R200_PP_TXCBLEND_1, "R200_PP_TXCBLEND_1" },
 435    { R200_PP_TXCBLEND2_1, "R200_PP_TXCBLEND2_1" },
 436    { R200_PP_TXABLEND_1, "R200_PP_TXABLEND_1" },
 437    { R200_PP_TXABLEND2_1, "R200_PP_TXABLEND2_1" },
 438    { R200_PP_TXCBLEND_2, "R200_PP_TXCBLEND_2" },
 439    { R200_PP_TXCBLEND2_2, "R200_PP_TXCBLEND2_2" },
 440    { R200_PP_TXABLEND_2, "R200_PP_TXABLEND_2" },
 441    { R200_PP_TXABLEND2_2, "R200_PP_TXABLEND2_2" },
 442    { R200_PP_TXCBLEND_3, "R200_PP_TXCBLEND_3" },
 443    { R200_PP_TXCBLEND2_3, "R200_PP_TXCBLEND2_3" },
 444    { R200_PP_TXABLEND_3, "R200_PP_TXABLEND_3" },
 445    { R200_PP_TXABLEND2_3, "R200_PP_TXABLEND2_3" },
 446    { R200_PP_TXCBLEND_4, "R200_PP_TXCBLEND_4" },
 447    { R200_PP_TXCBLEND2_4, "R200_PP_TXCBLEND2_4" },
 448    { R200_PP_TXABLEND_4, "R200_PP_TXABLEND_4" },
 449    { R200_PP_TXABLEND2_4, "R200_PP_TXABLEND2_4" },
 450    { R200_PP_TXCBLEND_5, "R200_PP_TXCBLEND_5" },
 451    { R200_PP_TXCBLEND2_5, "R200_PP_TXCBLEND2_5" },
 452    { R200_PP_TXABLEND_5, "R200_PP_TXABLEND_5" },
 453    { R200_PP_TXABLEND2_5, "R200_PP_TXABLEND2_5" },
 454    { R200_PP_TXCBLEND_6, "R200_PP_TXCBLEND_6" },
 455    { R200_PP_TXCBLEND2_6, "R200_PP_TXCBLEND2_6" },
 456    { R200_PP_TXABLEND_6, "R200_PP_TXABLEND_6" },
 457    { R200_PP_TXABLEND2_6, "R200_PP_TXABLEND2_6" },
 458    { R200_PP_TXCBLEND_7, "R200_PP_TXCBLEND_7" },
 459    { R200_PP_TXCBLEND2_7, "R200_PP_TXCBLEND2_7" },
 460    { R200_PP_TXABLEND_7, "R200_PP_TXABLEND_7" },
 461    { R200_PP_TXABLEND2_7, "R200_PP_TXABLEND2_7" },
 462    { R200_RB3D_ABLENDCNTL, "R200_RB3D_ABLENDCNTL" },
 463    { R200_RB3D_CBLENDCNTL, "R200_RB3D_CBLENDCNTL" },
 464    { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
 465    { R200_PP_CNTL_X, "R200_PP_CNTL_X" },
 466    { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" },
 467    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
 468    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
 469    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
 470    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
 471 };
 472
 473 static struct reg_names scalar_names[] = {
 474    { R200_SS_LIGHT_DCD_ADDR, "R200_SS_LIGHT_DCD_ADDR" },
 475    { R200_SS_LIGHT_DCM_ADDR, "R200_SS_LIGHT_DCM_ADDR" },
 476    { R200_SS_LIGHT_SPOT_EXPONENT_ADDR, "R200_SS_LIGHT_SPOT_EXPONENT_ADDR" },
 477    { R200_SS_LIGHT_SPOT_CUTOFF_ADDR, "R200_SS_LIGHT_SPOT_CUTOFF_ADDR" },
 478    { R200_SS_LIGHT_SPECULAR_THRESH_ADDR, "R200_SS_LIGHT_SPECULAR_THRESH_ADDR" },
 479    { R200_SS_LIGHT_RANGE_CUTOFF_SQRD, "R200_SS_LIGHT_RANGE_CUTOFF_SQRD" },
 480    { R200_SS_LIGHT_RANGE_ATT_CONST, "R200_SS_LIGHT_RANGE_ATT_CONST" },
 481    { R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, "R200_SS_VERT_GUARD_CLIP_ADJ_ADDR" },
 482    { R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR, "R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR" },
 483    { R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR, "R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR" },
 484    { R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR, "R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR" },
 485    { R200_SS_MAT_0_SHININESS, "R200_SS_MAT_0_SHININESS" },
 486    { R200_SS_MAT_1_SHININESS, "R200_SS_MAT_1_SHININESS" },
 487    { 1000, "" },
 488 };
 489
 490 /* Puff these out to make them look like normal (dword) registers.
 491  */
 492 static struct reg_names vector_names[] = {
 493    { 0, "start" },
 494    { R200_VS_LIGHT_AMBIENT_ADDR, "R200_VS_LIGHT_AMBIENT_ADDR" },
 495    { R200_VS_LIGHT_DIFFUSE_ADDR, "R200_VS_LIGHT_DIFFUSE_ADDR" },
 496    { R200_VS_LIGHT_SPECULAR_ADDR, "R200_VS_LIGHT_SPECULAR_ADDR" },
 497    { R200_VS_LIGHT_DIRPOS_ADDR, "R200_VS_LIGHT_DIRPOS_ADDR" },
 498    { R200_VS_LIGHT_HWVSPOT_ADDR, "R200_VS_LIGHT_HWVSPOT_ADDR" },
 499    { R200_VS_LIGHT_ATTENUATION_ADDR, "R200_VS_LIGHT_ATTENUATION_ADDR" },
 500    { R200_VS_SPOT_DUAL_CONE, "R200_VS_SPOT_DUAL_CONE" },
 501    { R200_VS_GLOBAL_AMBIENT_ADDR, "R200_VS_GLOBAL_AMBIENT_ADDR" },
 502    { R200_VS_FOG_PARAM_ADDR, "R200_VS_FOG_PARAM_ADDR" },
 503    { R200_VS_EYE_VECTOR_ADDR, "R200_VS_EYE_VECTOR_ADDR" },
 504    { R200_VS_UCP_ADDR, "R200_VS_UCP_ADDR" },
 505    { R200_VS_PNT_SPRITE_VPORT_SCALE, "R200_VS_PNT_SPRITE_VPORT_SCALE" },
 506    { R200_VS_MATRIX_0_MV, "R200_VS_MATRIX_0_MV" },
 507    { R200_VS_MATRIX_1_INV_MV, "R200_VS_MATRIX_1_INV_MV" },
 508    { R200_VS_MATRIX_2_MVP, "R200_VS_MATRIX_2_MVP" },
 509    { R200_VS_MATRIX_3_TEX0, "R200_VS_MATRIX_3_TEX0" },
 510    { R200_VS_MATRIX_4_TEX1, "R200_VS_MATRIX_4_TEX1" },
 511    { R200_VS_MATRIX_5_TEX2, "R200_VS_MATRIX_5_TEX2" },
 512    { R200_VS_MATRIX_6_TEX3, "R200_VS_MATRIX_6_TEX3" },
 513    { R200_VS_MATRIX_7_TEX4, "R200_VS_MATRIX_7_TEX4" },
 514    { R200_VS_MATRIX_8_TEX5, "R200_VS_MATRIX_8_TEX5" },
 515    { R200_VS_MAT_0_EMISS, "R200_VS_MAT_0_EMISS" },
 516    { R200_VS_MAT_0_AMB, "R200_VS_MAT_0_AMB" },
 517    { R200_VS_MAT_0_DIF, "R200_VS_MAT_0_DIF" },
 518    { R200_VS_MAT_0_SPEC, "R200_VS_MAT_0_SPEC" },
 519    { R200_VS_MAT_1_EMISS, "R200_VS_MAT_1_EMISS" },
 520    { R200_VS_MAT_1_AMB, "R200_VS_MAT_1_AMB" },
 521    { R200_VS_MAT_1_DIF, "R200_VS_MAT_1_DIF" },
 522    { R200_VS_MAT_1_SPEC, "R200_VS_MAT_1_SPEC" },
 523    { R200_VS_EYE2CLIP_MTX, "R200_VS_EYE2CLIP_MTX" },
 524    { R200_VS_PNT_SPRITE_ATT_CONST, "R200_VS_PNT_SPRITE_ATT_CONST" },
 525    { R200_VS_PNT_SPRITE_EYE_IN_MODEL, "R200_VS_PNT_SPRITE_EYE_IN_MODEL" },
 526    { R200_VS_PNT_SPRITE_CLAMP, "R200_VS_PNT_SPRITE_CLAMP" },
 527    { R200_VS_MAX, "R200_VS_MAX" },
 528    { 1000, "" },
 529 };
 530
 531 union fi { float f; int i; };
 532
 533 #define ISVEC   1
 534 #define ISFLOAT 2
 535 #define TOUCHED 4
 536
 537 struct reg {
 538    int idx;
 539    struct reg_names *closest;
 540    int flags;
 541    union fi current;
 542    union fi *values;
 543    int nvalues;
 544    int nalloc;
 545    float vmin, vmax;
 546 };
 547
 548
 549 static struct reg regs[Elements(reg_names)+1];
 550 static struct reg scalars[512+1];
 551 static struct reg vectors[512*4+1];
 552
 553 static int total, total_changed, bufs;
 554
 555 static void init_regs( void )
 556 {
 557    struct reg_names *tmp;
 558    int i;
 559
 560    for (i = 0 ; i < Elements(regs) ; i++) {
 561       regs[i].idx = reg_names[i].idx;
 562       regs[i].closest = &reg_names[i];
 563       regs[i].flags = 0;
 564    }
 565
 566    for (i = 0, tmp = scalar_names ; i < Elements(scalars) ; i++) {
 567       if (tmp[1].idx == i) tmp++;
 568       scalars[i].idx = i;
 569       scalars[i].closest = tmp;
 570       scalars[i].flags = ISFLOAT;
 571    }
 572
 573    for (i = 0, tmp = vector_names ; i < Elements(vectors) ; i++) {
 574       if (tmp[1].idx*4 == i) tmp++;
 575       vectors[i].idx = i;
 576       vectors[i].closest = tmp;
 577       vectors[i].flags = ISFLOAT|ISVEC;
 578    }
 579
 580    regs[Elements(regs)-1].idx = -1;
 581    scalars[Elements(scalars)-1].idx = -1;
 582    vectors[Elements(vectors)-1].idx = -1;
 583 }
 584
 585 static int find_or_add_value( struct reg *reg, int val )
 586 {
 587    int j;
 588
 589    for ( j = 0 ; j < reg->nvalues ; j++)
 590       if ( val == reg->values[j].i )
 591          return 1;
 592
 593    if (j == reg->nalloc) {
 594       reg->nalloc += 5;
 595       reg->nalloc *= 2;
 596       reg->values = (union fi *) realloc( reg->values,
 597                                           reg->nalloc * sizeof(union fi) );
 598    }
 599
 600    reg->values[reg->nvalues++].i = val;
 601    return 0;
 602 }
 603
 604 static struct reg *lookup_reg( struct reg *tab, int reg )
 605 {
 606    int i;
 607
 608    for (i = 0 ; tab[i].idx != -1 ; i++) {
 609       if (tab[i].idx == reg)
 610          return &tab[i];
 611    }
 612
 613    fprintf(stderr, "*** unknown reg 0x%x\n", reg);
 614    return 0;
 615 }
 616
 617
 618 static const char *get_reg_name( struct reg *reg )
 619 {
 620    static char tmp[80];
 621
 622    if (reg->idx == reg->closest->idx)
 623       return reg->closest->name;
 624
 625
 626    if (reg->flags & ISVEC) {
 627       if (reg->idx/4 != reg->closest->idx)
 628          sprintf(tmp, "%s+%d[%d]",
 629                  reg->closest->name,
 630                  (reg->idx/4) - reg->closest->idx,
 631                  reg->idx%4);
 632       else
 633          sprintf(tmp, "%s[%d]", reg->closest->name, reg->idx%4);
 634    }
 635    else {
 636       if (reg->idx != reg->closest->idx)
 637          sprintf(tmp, "%s+%d", reg->closest->name, reg->idx - reg->closest->idx);
 638       else
 639          sprintf(tmp, "%s", reg->closest->name);
 640    }
 641
 642    return tmp;
 643 }
 644
 645 static int print_int_reg_assignment( struct reg *reg, int data )
 646 {
 647    int changed = (reg->current.i != data);
 648    int ever_seen = find_or_add_value( reg, data );
 649
 650    if (VERBOSE || (NORMAL && (changed || !ever_seen)))
 651        fprintf(stderr, "   %s <-- 0x%x", get_reg_name(reg), data);
 652
 653    if (NORMAL) {
 654       if (!ever_seen)
 655          fprintf(stderr, " *** BRAND NEW VALUE");
 656       else if (changed)
 657          fprintf(stderr, " *** CHANGED");
 658    }
 659
 660    reg->current.i = data;
 661
 662    if (VERBOSE || (NORMAL && (changed || !ever_seen)))
 663       fprintf(stderr, "\n");
 664
 665    return changed;
 666 }
 667
 668
 669 static int print_float_reg_assignment( struct reg *reg, float data )
 670 {
 671    int changed = (reg->current.f != data);
 672    int newmin = (data < reg->vmin);
 673    int newmax = (data > reg->vmax);
 674
 675    if (VERBOSE || (NORMAL && (newmin || newmax || changed)))
 676       fprintf(stderr, "   %s <-- %.3f", get_reg_name(reg), data);
 677
 678    if (NORMAL) {
 679       if (newmin) {
 680          fprintf(stderr, " *** NEW MIN (prev %.3f)", reg->vmin);
 681          reg->vmin = data;
 682       }
 683       else if (newmax) {
 684          fprintf(stderr, " *** NEW MAX (prev %.3f)", reg->vmax);
 685          reg->vmax = data;
 686       }
 687       else if (changed) {
 688          fprintf(stderr, " *** CHANGED");
 689       }
 690    }
 691
 692    reg->current.f = data;
 693
 694    if (VERBOSE || (NORMAL && (newmin || newmax || changed)))
 695       fprintf(stderr, "\n");
 696
 697    return changed;
 698 }
 699
 700 static int print_reg_assignment( struct reg *reg, int data )
 701 {
 702    reg->flags |= TOUCHED;
 703    if (reg->flags & ISFLOAT)
 704       return print_float_reg_assignment( reg, *(float *)&data );
 705    else
 706       return print_int_reg_assignment( reg, data );
 707 }
 708
 709 static void print_reg( struct reg *reg )
 710 {
 711    if (reg->flags & TOUCHED) {
 712       if (reg->flags & ISFLOAT) {
 713          fprintf(stderr, "   %s == %f\n", get_reg_name(reg), reg->current.f);
 714       } else {
 715          fprintf(stderr, "   %s == 0x%x\n", get_reg_name(reg), reg->current.i);
 716       }
 717    }
 718 }
 719
 720
 721 static void dump_state( void )
 722 {
 723    int i;
 724
 725    for (i = 0 ; i < Elements(regs) ; i++)
 726       print_reg( &regs[i] );
 727
 728    for (i = 0 ; i < Elements(scalars) ; i++)
 729       print_reg( &scalars[i] );
 730
 731    for (i = 0 ; i < Elements(vectors) ; i++)
 732       print_reg( &vectors[i] );
 733 }
 734
 735
 736
 737 static int radeon_emit_packets(
 738    drmRadeonCmdHeader header,
 739    drmRadeonCmdBuffer *cmdbuf )
 740 {
 741    int id = (int)header.packet.packet_id;
 742    int sz = packet[id].len;
 743    int *data = (int *)cmdbuf->buf;
 744    int i;
 745
 746    if (sz * sizeof(int) > cmdbuf->bufsz) {
 747       fprintf(stderr, "Packet overflows cmdbuf\n");
 748       return -EINVAL;
 749    }
 750
 751    if (!packet[id].name) {
 752       fprintf(stderr, "*** Unknown packet 0 nr %d\n", id );
 753       return -EINVAL;
 754    }
 755
 756
 757    if (VERBOSE)
 758       fprintf(stderr, "Packet 0 reg %s nr %d\n", packet[id].name, sz );
 759
 760    for ( i = 0 ; i < sz ; i++) {
 761       struct reg *reg = lookup_reg( regs, packet[id].start + i*4 );
 762       if (print_reg_assignment( reg, data[i] ))
 763          total_changed++;
 764       total++;
 765    }
 766
 767    cmdbuf->buf += sz * sizeof(int);
 768    cmdbuf->bufsz -= sz * sizeof(int);
 769    return 0;
 770 }
 771
 772
 773 static int radeon_emit_scalars(
 774    drmRadeonCmdHeader header,
 775    drmRadeonCmdBuffer *cmdbuf )
 776 {
 777    int sz = header.scalars.count;
 778    int *data = (int *)cmdbuf->buf;
 779    int start = header.scalars.offset;
 780    int stride = header.scalars.stride;
 781    int i;
 782
 783    if (VERBOSE)
 784       fprintf(stderr, "emit scalars, start %d stride %d nr %d (end %d)\n",
 785               start, stride, sz, start + stride * sz);
 786
 787
 788    for (i = 0 ; i < sz ; i++, start += stride) {
 789       struct reg *reg = lookup_reg( scalars, start );
 790       if (print_reg_assignment( reg, data[i] ))
 791          total_changed++;
 792       total++;
 793    }
 794
 795    cmdbuf->buf += sz * sizeof(int);
 796    cmdbuf->bufsz -= sz * sizeof(int);
 797    return 0;
 798 }
 799
 800
 801 static int radeon_emit_scalars2(
 802    drmRadeonCmdHeader header,
 803    drmRadeonCmdBuffer *cmdbuf )
 804 {
 805    int sz = header.scalars.count;
 806    int *data = (int *)cmdbuf->buf;
 807    int start = header.scalars.offset + 0x100;
 808    int stride = header.scalars.stride;
 809    int i;
 810
 811    if (VERBOSE)
 812       fprintf(stderr, "emit scalars2, start %d stride %d nr %d (end %d)\n",
 813               start, stride, sz, start + stride * sz);
 814
 815    if (start + stride * sz > 257) {
 816       fprintf(stderr, "emit scalars OVERFLOW %d/%d/%d\n", start, stride, sz);
 817       return -1;
 818    }
 819
 820    for (i = 0 ; i < sz ; i++, start += stride) {
 821       struct reg *reg = lookup_reg( scalars, start );
 822       if (print_reg_assignment( reg, data[i] ))
 823          total_changed++;
 824       total++;
 825    }
 826
 827    cmdbuf->buf += sz * sizeof(int);
 828    cmdbuf->bufsz -= sz * sizeof(int);
 829    return 0;
 830 }
 831
 832 /* Check: inf/nan/extreme-size?
 833  * Check: table start, end, nr, etc.
 834  */
 835 static int radeon_emit_vectors(
 836    drmRadeonCmdHeader header,
 837    drmRadeonCmdBuffer *cmdbuf )
 838 {
 839    int sz = header.vectors.count;
 840    int *data = (int *)cmdbuf->buf;
 841    int start = header.vectors.offset;
 842    int stride = header.vectors.stride;
 843    int i,j;
 844
 845    if (VERBOSE)
 846       fprintf(stderr, "emit vectors, start %d stride %d nr %d (end %d) (0x%x)\n",
 847               start, stride, sz, start + stride * sz, header.i);
 848
 849 /*    if (start + stride * (sz/4) > 128) { */
 850 /*       fprintf(stderr, "emit vectors OVERFLOW %d/%d/%d\n", start, stride, sz); */
 851 /*       return -1; */
 852 /*    } */
 853
 854    for (i = 0 ; i < sz ;  start += stride) {
 855       int changed = 0;
 856       for (j = 0 ; j < 4 ; i++,j++) {
 857          struct reg *reg = lookup_reg( vectors, start*4+j );
 858          if (print_reg_assignment( reg, data[i] ))
 859             changed = 1;
 860       }
 861       if (changed)
 862          total_changed += 4;
 863       total += 4;
 864    }
 865
 866
 867    cmdbuf->buf += sz * sizeof(int);
 868    cmdbuf->bufsz -= sz * sizeof(int);
 869    return 0;
 870 }
 871
 872 #if 0
 873 static int print_vertex_format( int vfmt )
 874 {
 875    if (NORMAL) {
 876       fprintf(stderr, "   %s(%x): %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 877               "vertex format",
 878               vfmt,
 879               "xy,",
 880               (vfmt & R200_VTX_Z0) ? "z," : "",
 881               (vfmt & R200_VTX_W0) ? "w0," : "",
 882               (vfmt & R200_VTX_FPCOLOR) ? "fpcolor," : "",
 883               (vfmt & R200_VTX_FPALPHA) ? "fpalpha," : "",
 884               (vfmt & R200_VTX_PKCOLOR) ? "pkcolor," : "",
 885               (vfmt & R200_VTX_FPSPEC) ? "fpspec," : "",
 886               (vfmt & R200_VTX_FPFOG) ? "fpfog," : "",
 887               (vfmt & R200_VTX_PKSPEC) ? "pkspec," : "",
 888               (vfmt & R200_VTX_ST0) ? "st0," : "",
 889               (vfmt & R200_VTX_ST1) ? "st1," : "",
 890               (vfmt & R200_VTX_Q1) ? "q1," : "",
 891               (vfmt & R200_VTX_ST2) ? "st2," : "",
 892               (vfmt & R200_VTX_Q2) ? "q2," : "",
 893               (vfmt & R200_VTX_ST3) ? "st3," : "",
 894               (vfmt & R200_VTX_Q3) ? "q3," : "",
 895               (vfmt & R200_VTX_Q0) ? "q0," : "",
 896               (vfmt & R200_VTX_N0) ? "n0," : "",
 897               (vfmt & R200_VTX_XY1) ? "xy1," : "",
 898               (vfmt & R200_VTX_Z1) ? "z1," : "",
 899               (vfmt & R200_VTX_W1) ? "w1," : "",
 900               (vfmt & R200_VTX_N1) ? "n1," : "");
 901
 902
 903       if (!find_or_add_value( &others[V_VTXFMT], vfmt ))
 904          fprintf(stderr, " *** NEW VALUE");
 905
 906       fprintf(stderr, "\n");
 907    }
 908
 909    return 0;
 910 }
 911 #endif
 912
 913 static char *primname[0x10] = {
 914    "NONE",
 915    "POINTS",
 916    "LINES",
 917    "LINE_STRIP",
 918    "TRIANGLES",
 919    "TRIANGLE_FAN",
 920    "TRIANGLE_STRIP",
 921    "RECT_LIST",
 922    0,
 923    "3VRT_POINTS",
 924    "3VRT_LINES",
 925    "POINT_SPRITES",
 926    "LINE_LOOP",
 927    "QUADS",
 928    "QUAD_STRIP",
 929    "POLYGON",
 930 };
 931
 932 static int print_prim_and_flags( int prim )
 933 {
 934    int numverts;
 935
 936    if (NORMAL)
 937       fprintf(stderr, "   %s(%x): %s%s%s%s%s%s\n",
 938               "prim flags",
 939               prim,
 940               ((prim & 0x30) == R200_VF_PRIM_WALK_IND) ? "IND," : "",
 941               ((prim & 0x30) == R200_VF_PRIM_WALK_LIST) ? "LIST," : "",
 942               ((prim & 0x30) == R200_VF_PRIM_WALK_RING) ? "RING," : "",
 943               (prim & R200_VF_COLOR_ORDER_RGBA) ? "RGBA," : "BGRA, ",
 944               (prim & R200_VF_INDEX_SZ_4) ? "INDX-32," : "",
 945               (prim & R200_VF_TCL_OUTPUT_VTX_ENABLE) ? "TCL_OUT_VTX," : "");
 946
 947    numverts = prim>>16;
 948
 949    if (NORMAL)
 950       fprintf(stderr, "   prim: %s numverts %d\n", primname[prim&0xf], numverts);
 951
 952    switch (prim & 0xf) {
 953    case R200_VF_PRIM_NONE:
 954    case R200_VF_PRIM_POINTS:
 955       if (numverts < 1) {
 956          fprintf(stderr, "Bad nr verts for line %d\n", numverts);
 957          return -1;
 958       }
 959       break;
 960    case R200_VF_PRIM_LINES:
 961    case R200_VF_PRIM_POINT_SPRITES:
 962       if ((numverts & 1) || numverts == 0) {
 963          fprintf(stderr, "Bad nr verts for line %d\n", numverts);
 964          return -1;
 965       }
 966       break;
 967    case R200_VF_PRIM_LINE_STRIP:
 968    case R200_VF_PRIM_LINE_LOOP:
 969       if (numverts < 2) {
 970          fprintf(stderr, "Bad nr verts for line_strip %d\n", numverts);
 971          return -1;
 972       }
 973       break;
 974    case R200_VF_PRIM_TRIANGLES:
 975    case R200_VF_PRIM_3VRT_POINTS:
 976    case R200_VF_PRIM_3VRT_LINES:
 977    case R200_VF_PRIM_RECT_LIST:
 978       if (numverts % 3 || numverts == 0) {
 979          fprintf(stderr, "Bad nr verts for tri %d\n", numverts);
 980          return -1;
 981       }
 982       break;
 983    case R200_VF_PRIM_TRIANGLE_FAN:
 984    case R200_VF_PRIM_TRIANGLE_STRIP:
 985    case R200_VF_PRIM_POLYGON:
 986       if (numverts < 3) {
 987          fprintf(stderr, "Bad nr verts for strip/fan %d\n", numverts);
 988          return -1;
 989       }
 990       break;
 991    case R200_VF_PRIM_QUADS:
 992       if (numverts % 4 || numverts == 0) {
 993          fprintf(stderr, "Bad nr verts for quad %d\n", numverts);
 994          return -1;
 995       }
 996       break;
 997    case R200_VF_PRIM_QUAD_STRIP:
 998       if (numverts % 2 || numverts < 4) {
 999          fprintf(stderr, "Bad nr verts for quadstrip %d\n", numverts);
1000          return -1;
1001       }
1002       break;
1003    default:
1004       fprintf(stderr, "Bad primitive\n");
1005       return -1;
1006    }
1007    return 0;
1008 }
1009
1010 /* build in knowledge about each packet type
1011  */
1012 static int radeon_emit_packet3( drmRadeonCmdBuffer *cmdbuf )
1013 {
1014    int cmdsz;
1015    int *cmd = (int *)cmdbuf->buf;
1016    int *tmp;
1017    int i, stride, size, start;
1018
1019    cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);
1020
1021    if ((cmd[0] & RADEON_CP_PACKET_MASK) != RADEON_CP_PACKET3 ||
1022        cmdsz * 4 > cmdbuf->bufsz ||
1023        cmdsz > RADEON_CP_PACKET_MAX_DWORDS) {
1024       fprintf(stderr, "Bad packet\n");
1025       return -EINVAL;
1026    }
1027
1028    switch( cmd[0] & ~RADEON_CP_PACKET_COUNT_MASK ) {
1029    case R200_CP_CMD_NOP:
1030       if (NORMAL)
1031          fprintf(stderr, "PACKET3_NOP, %d dwords\n", cmdsz);
1032       break;
1033    case R200_CP_CMD_NEXT_CHAR:
1034       if (NORMAL)
1035          fprintf(stderr, "PACKET3_NEXT_CHAR, %d dwords\n", cmdsz);
1036       break;
1037    case R200_CP_CMD_PLY_NEXTSCAN:
1038       if (NORMAL)
1039          fprintf(stderr, "PACKET3_PLY_NEXTSCAN, %d dwords\n", cmdsz);
1040       break;
1041    case R200_CP_CMD_SET_SCISSORS:
1042       if (NORMAL)
1043          fprintf(stderr, "PACKET3_SET_SCISSORS, %d dwords\n", cmdsz);
1044       break;
1045    case R200_CP_CMD_LOAD_MICROCODE:
1046       if (NORMAL)
1047          fprintf(stderr, "PACKET3_LOAD_MICROCODE, %d dwords\n", cmdsz);
1048       break;
1049    case R200_CP_CMD_WAIT_FOR_IDLE:
1050       if (NORMAL)
1051          fprintf(stderr, "PACKET3_WAIT_FOR_IDLE, %d dwords\n", cmdsz);
1052       break;
1053
1054    case R200_CP_CMD_3D_DRAW_VBUF:
1055       if (NORMAL)
1056          fprintf(stderr, "PACKET3_3D_DRAW_VBUF, %d dwords\n", cmdsz);
1057 /*       print_vertex_format(cmd[1]); */
1058       if (print_prim_and_flags(cmd[2]))
1059          return -EINVAL;
1060       break;
1061
1062    case R200_CP_CMD_3D_DRAW_IMMD:
1063       if (NORMAL)
1064          fprintf(stderr, "PACKET3_3D_DRAW_IMMD, %d dwords\n", cmdsz);
1065       break;
1066    case R200_CP_CMD_3D_DRAW_INDX: {
1067       int neltdwords;
1068       if (NORMAL)
1069          fprintf(stderr, "PACKET3_3D_DRAW_INDX, %d dwords\n", cmdsz);
1070 /*       print_vertex_format(cmd[1]); */
1071       if (print_prim_and_flags(cmd[2]))
1072          return -EINVAL;
1073       neltdwords = cmd[2]>>16;
1074       neltdwords += neltdwords & 1;
1075       neltdwords /= 2;
1076       if (neltdwords + 3 != cmdsz)
1077          fprintf(stderr, "Mismatch in DRAW_INDX, %d vs cmdsz %d\n",
1078                  neltdwords, cmdsz);
1079       break;
1080    }
1081    case R200_CP_CMD_LOAD_PALETTE:
1082       if (NORMAL)
1083          fprintf(stderr, "PACKET3_LOAD_PALETTE, %d dwords\n", cmdsz);
1084       break;
1085    case R200_CP_CMD_3D_LOAD_VBPNTR:
1086       if (NORMAL) {
1087          fprintf(stderr, "PACKET3_3D_LOAD_VBPNTR, %d dwords\n", cmdsz);
1088          fprintf(stderr, "   nr arrays: %d\n", cmd[1]);
1089       }
1090
1091       if (((cmd[1]/2)*3) + ((cmd[1]%2)*2) != cmdsz - 2) {
1092          fprintf(stderr, "  ****** MISMATCH %d/%d *******\n",
1093                  ((cmd[1]/2)*3) + ((cmd[1]%2)*2) + 2, cmdsz);
1094          return -EINVAL;
1095       }
1096
1097       if (NORMAL) {
1098          tmp = cmd+2;
1099          for (i = 0 ; i < cmd[1] ; i++) {
1100             if (i & 1) {
1101                stride = (tmp[0]>>24) & 0xff;
1102                size = (tmp[0]>>16) & 0xff;
1103                start = tmp[2];
1104                tmp += 3;
1105             }
1106             else {
1107                stride = (tmp[0]>>8) & 0xff;
1108                size = (tmp[0]) & 0xff;
1109                start = tmp[1];
1110             }
1111             fprintf(stderr, "   array %d: start 0x%x vsize %d vstride %d\n",
1112                     i, start, size, stride );
1113          }
1114       }
1115       break;
1116    case R200_CP_CMD_PAINT:
1117       if (NORMAL)
1118          fprintf(stderr, "PACKET3_CNTL_PAINT, %d dwords\n", cmdsz);
1119       break;
1120    case R200_CP_CMD_BITBLT:
1121       if (NORMAL)
1122          fprintf(stderr, "PACKET3_CNTL_BITBLT, %d dwords\n", cmdsz);
1123       break;
1124    case R200_CP_CMD_SMALLTEXT:
1125       if (NORMAL)
1126          fprintf(stderr, "PACKET3_CNTL_SMALLTEXT, %d dwords\n", cmdsz);
1127       break;
1128    case R200_CP_CMD_HOSTDATA_BLT:
1129       if (NORMAL)
1130          fprintf(stderr, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n",
1131               cmdsz);
1132       break;
1133    case R200_CP_CMD_POLYLINE:
1134       if (NORMAL)
1135          fprintf(stderr, "PACKET3_CNTL_POLYLINE, %d dwords\n", cmdsz);
1136       break;
1137    case R200_CP_CMD_POLYSCANLINES:
1138       if (NORMAL)
1139          fprintf(stderr, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n",
1140               cmdsz);
1141       break;
1142    case R200_CP_CMD_PAINT_MULTI:
1143       if (NORMAL)
1144          fprintf(stderr, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n",
1145               cmdsz);
1146       break;
1147    case R200_CP_CMD_BITBLT_MULTI:
1148       if (NORMAL)
1149          fprintf(stderr, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n",
1150               cmdsz);
1151       break;
1152    case R200_CP_CMD_TRANS_BITBLT:
1153       if (NORMAL)
1154          fprintf(stderr, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n",
1155               cmdsz);
1156       break;
1157    case R200_CP_CMD_3D_DRAW_VBUF_2:
1158       if (NORMAL)
1159          fprintf(stderr, "R200_CP_CMD_3D_DRAW_VBUF_2, %d dwords\n",
1160               cmdsz);
1161       if (print_prim_and_flags(cmd[1]))
1162          return -EINVAL;
1163       break;
1164    case R200_CP_CMD_3D_DRAW_IMMD_2:
1165       if (NORMAL)
1166          fprintf(stderr, "R200_CP_CMD_3D_DRAW_IMMD_2, %d dwords\n",
1167               cmdsz);
1168       if (print_prim_and_flags(cmd[1]))
1169          return -EINVAL;
1170       break;
1171    case R200_CP_CMD_3D_DRAW_INDX_2:
1172       if (NORMAL)
1173          fprintf(stderr, "R200_CP_CMD_3D_DRAW_INDX_2, %d dwords\n",
1174               cmdsz);
1175       if (print_prim_and_flags(cmd[1]))
1176          return -EINVAL;
1177       break;
1178    default:
1179       fprintf(stderr, "UNKNOWN PACKET, %d dwords\n", cmdsz);
1180       break;
1181    }
1182
1183    cmdbuf->buf += cmdsz * 4;
1184    cmdbuf->bufsz -= cmdsz * 4;
1185    return 0;
1186 }
1187
1188
1189 /* Check cliprects for bounds, then pass on to above:
1190  */
1191 static int radeon_emit_packet3_cliprect( drmRadeonCmdBuffer *cmdbuf )
1192 {
1193    XF86DRIClipRectRec *boxes = (XF86DRIClipRectRec *)cmdbuf->boxes;
1194    int i = 0;
1195
1196    if (VERBOSE && total_changed) {
1197       dump_state();
1198       total_changed = 0;
1199    }
1200
1201    if (NORMAL) {
1202       do {
1203          if ( i < cmdbuf->nbox ) {
1204             fprintf(stderr, "Emit box %d/%d %d,%d %d,%d\n",
1205                     i, cmdbuf->nbox,
1206                     boxes[i].x1, boxes[i].y1, boxes[i].x2, boxes[i].y2);
1207          }
1208       } while ( ++i < cmdbuf->nbox );
1209    }
1210
1211    if (cmdbuf->nbox == 1)
1212       cmdbuf->nbox = 0;
1213
1214    return radeon_emit_packet3( cmdbuf );
1215 }
1216
1217
1218 int r200SanityCmdBuffer( r200ContextPtr rmesa,
1219                            int nbox,
1220                            XF86DRIClipRectRec *boxes )
1221 {
1222    int idx;
1223    drmRadeonCmdBuffer cmdbuf;
1224    drmRadeonCmdHeader header;
1225    static int inited = 0;
1226
1227    if (!inited) {
1228       init_regs();
1229       inited = 1;
1230    }
1231
1232
1233    cmdbuf.buf = rmesa->store.cmd_buf;
1234    cmdbuf.bufsz = rmesa->store.cmd_used;
1235    cmdbuf.boxes = (drmClipRect *)boxes;
1236    cmdbuf.nbox = nbox;
1237
1238    while ( cmdbuf.bufsz >= sizeof(header) ) {
1239
1240       header.i = *(int *)cmdbuf.buf;
1241       cmdbuf.buf += sizeof(header);
1242       cmdbuf.bufsz -= sizeof(header);
1243
1244       switch (header.header.cmd_type) {
1245       case RADEON_CMD_PACKET:
1246          if (radeon_emit_packets( header, &cmdbuf )) {
1247             fprintf(stderr,"radeon_emit_packets failed\n");
1248             return -EINVAL;
1249          }
1250          break;
1251
1252       case RADEON_CMD_SCALARS:
1253          if (radeon_emit_scalars( header, &cmdbuf )) {
1254             fprintf(stderr,"radeon_emit_scalars failed\n");
1255             return -EINVAL;
1256          }
1257          break;
1258
1259       case RADEON_CMD_SCALARS2:
1260          if (radeon_emit_scalars2( header, &cmdbuf )) {
1261             fprintf(stderr,"radeon_emit_scalars failed\n");
1262             return -EINVAL;
1263          }
1264          break;
1265
1266       case RADEON_CMD_VECTORS:
1267          if (radeon_emit_vectors( header, &cmdbuf )) {
1268             fprintf(stderr,"radeon_emit_vectors failed\n");
1269             return -EINVAL;
1270          }
1271          break;
1272
1273       case RADEON_CMD_DMA_DISCARD:
1274          idx = header.dma.buf_idx;
1275          if (NORMAL)
1276             fprintf(stderr, "RADEON_CMD_DMA_DISCARD buf %d\n", idx);
1277          bufs++;
1278          break;
1279
1280       case RADEON_CMD_PACKET3:
1281          if (radeon_emit_packet3( &cmdbuf )) {
1282             fprintf(stderr,"radeon_emit_packet3 failed\n");
1283             return -EINVAL;
1284          }
1285          break;
1286
1287       case RADEON_CMD_PACKET3_CLIP:
1288          if (radeon_emit_packet3_cliprect( &cmdbuf )) {
1289             fprintf(stderr,"radeon_emit_packet3_clip failed\n");
1290             return -EINVAL;
1291          }
1292          break;
1293
1294       case RADEON_CMD_WAIT:
1295          break;
1296
1297       default:
1298          fprintf(stderr,"bad cmd_type %d at %p\n",
1299                    header.header.cmd_type,
1300                    cmdbuf.buf - sizeof(header));
1301          return -EINVAL;
1302       }
1303    }
1304
1305    if (0)
1306    {
1307       static int n = 0;
1308       n++;
1309       if (n == 10) {
1310          fprintf(stderr, "Bufs %d Total emitted %d real changes %d (%.2f%%)\n",
1311                  bufs,
1312                  total, total_changed,
1313                  ((float)total_changed/(float)total*100.0));
1314          fprintf(stderr, "Total emitted per buf: %.2f\n",
1315                  (float)total/(float)bufs);
1316          fprintf(stderr, "Real changes per buf: %.2f\n",
1317                  (float)total_changed/(float)bufs);
1318
1319          bufs = n = total = total_changed = 0;
1320       }
1321    }
1322
1323    fprintf(stderr, "leaving %s\n\n\n", __FUNCTION__);
1324
1325    return 0;
1326 }