1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_sanity.c,v 1.1 2002/10/30 12:51:52 alanh Exp $ */
2 /**************************************************************************
4 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
5 Tungsten Graphics Inc, Cedar Park, TX.
9 Permission is hereby granted, free of charge, to any person obtaining a
10 copy of this software and associated documentation files (the "Software"),
11 to deal in the Software without restriction, including without limitation
12 on the rights to use, copy, modify, merge, publish, distribute, sub
13 license, and/or sell copies of the Software, and to permit persons to whom
14 the Software is furnished to do so, subject to the following conditions:
16 The above copyright notice and this permission notice (including the next
17 paragraph) shall be included in all copies or substantial portions of the
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
23 ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
24 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
25 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
26 USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
41 #include "r200_context.h"
42 #include "r200_ioctl.h"
43 #include "r200_sanity.h"
44 #include "radeon_reg.h"
47 /* Set this '1' to get more verbiage.
49 #define MORE_VERBOSE 1
52 #define VERBOSE (R200_DEBUG & DEBUG_VERBOSE)
56 #define NORMAL (R200_DEBUG & DEBUG_VERBOSE)
60 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
61 * 1.3 cmdbuffers allow all previous state to be updated as well as
62 * the tcl scalar and vector areas.
68 } packet
[RADEON_MAX_STATE_PACKETS
] = {
69 { RADEON_PP_MISC
,7,"RADEON_PP_MISC" },
70 { RADEON_PP_CNTL
,3,"RADEON_PP_CNTL" },
71 { RADEON_RB3D_COLORPITCH
,1,"RADEON_RB3D_COLORPITCH" },
72 { RADEON_RE_LINE_PATTERN
,2,"RADEON_RE_LINE_PATTERN" },
73 { RADEON_SE_LINE_WIDTH
,1,"RADEON_SE_LINE_WIDTH" },
74 { RADEON_PP_LUM_MATRIX
,1,"RADEON_PP_LUM_MATRIX" },
75 { RADEON_PP_ROT_MATRIX_0
,2,"RADEON_PP_ROT_MATRIX_0" },
76 { RADEON_RB3D_STENCILREFMASK
,3,"RADEON_RB3D_STENCILREFMASK" },
77 { RADEON_SE_VPORT_XSCALE
,6,"RADEON_SE_VPORT_XSCALE" },
78 { RADEON_SE_CNTL
,2,"RADEON_SE_CNTL" },
79 { RADEON_SE_CNTL_STATUS
,1,"RADEON_SE_CNTL_STATUS" },
80 { RADEON_RE_MISC
,1,"RADEON_RE_MISC" },
81 { RADEON_PP_TXFILTER_0
,6,"RADEON_PP_TXFILTER_0" },
82 { RADEON_PP_BORDER_COLOR_0
,1,"RADEON_PP_BORDER_COLOR_0" },
83 { RADEON_PP_TXFILTER_1
,6,"RADEON_PP_TXFILTER_1" },
84 { RADEON_PP_BORDER_COLOR_1
,1,"RADEON_PP_BORDER_COLOR_1" },
85 { RADEON_PP_TXFILTER_2
,6,"RADEON_PP_TXFILTER_2" },
86 { RADEON_PP_BORDER_COLOR_2
,1,"RADEON_PP_BORDER_COLOR_2" },
87 { RADEON_SE_ZBIAS_FACTOR
,2,"RADEON_SE_ZBIAS_FACTOR" },
88 { RADEON_SE_TCL_OUTPUT_VTX_FMT
,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
89 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED
,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
90 { R200_PP_TXCBLEND_0
, 4, "R200_EMIT_PP_TXCBLEND_0" },
91 { R200_PP_TXCBLEND_1
, 4, "R200_PP_TXCBLEND_1" },
92 { R200_PP_TXCBLEND_2
, 4, "R200_PP_TXCBLEND_2" },
93 { R200_PP_TXCBLEND_3
, 4, "R200_PP_TXCBLEND_3" },
94 { R200_PP_TXCBLEND_4
, 4, "R200_PP_TXCBLEND_4" },
95 { R200_PP_TXCBLEND_5
, 4, "R200_PP_TXCBLEND_5" },
96 { R200_PP_TXCBLEND_6
, 4, "R200_PP_TXCBLEND_6" },
97 { R200_PP_TXCBLEND_7
, 4, "R200_PP_TXCBLEND_7" },
98 { R200_SE_TCL_LIGHT_MODEL_CTL_0
, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
99 { R200_PP_TFACTOR_0
, 6, "R200_PP_TFACTOR_0" },
100 { R200_SE_VTX_FMT_0
, 4, "R200_SE_VTX_FMT_0" },
101 { R200_SE_VAP_CNTL
, 1, "R200_SE_VAP_CNTL" },
102 { R200_SE_TCL_MATRIX_SEL_0
, 5, "R200_SE_TCL_MATRIX_SEL_0" },
103 { R200_SE_TCL_TEX_PROC_CTL_2
, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
104 { R200_SE_TCL_UCP_VERT_BLEND_CTL
, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
105 { R200_PP_TXFILTER_0
, 6, "R200_PP_TXFILTER_0" },
106 { R200_PP_TXFILTER_1
, 6, "R200_PP_TXFILTER_1" },
107 { R200_PP_TXFILTER_2
, 6, "R200_PP_TXFILTER_2" },
108 { R200_PP_TXFILTER_3
, 6, "R200_PP_TXFILTER_3" },
109 { R200_PP_TXFILTER_4
, 6, "R200_PP_TXFILTER_4" },
110 { R200_PP_TXFILTER_5
, 6, "R200_PP_TXFILTER_5" },
111 { R200_PP_TXOFFSET_0
, 1, "R200_PP_TXOFFSET_0" },
112 { R200_PP_TXOFFSET_1
, 1, "R200_PP_TXOFFSET_1" },
113 { R200_PP_TXOFFSET_2
, 1, "R200_PP_TXOFFSET_2" },
114 { R200_PP_TXOFFSET_3
, 1, "R200_PP_TXOFFSET_3" },
115 { R200_PP_TXOFFSET_4
, 1, "R200_PP_TXOFFSET_4" },
116 { R200_PP_TXOFFSET_5
, 1, "R200_PP_TXOFFSET_5" },
117 { R200_SE_VTE_CNTL
, 1, "R200_SE_VTE_CNTL" },
118 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL
, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
119 { R200_PP_TAM_DEBUG3
, 1, "R200_PP_TAM_DEBUG3" },
120 { R200_PP_CNTL_X
, 1, "R200_PP_CNTL_X" },
121 { R200_RB3D_DEPTHXY_OFFSET
, 1, "R200_RB3D_DEPTHXY_OFFSET" },
122 { R200_RE_AUX_SCISSOR_CNTL
, 1, "R200_RE_AUX_SCISSOR_CNTL" },
123 { R200_RE_SCISSOR_TL_0
, 2, "R200_RE_SCISSOR_TL_0" },
124 { R200_RE_SCISSOR_TL_1
, 2, "R200_RE_SCISSOR_TL_1" },
125 { R200_RE_SCISSOR_TL_2
, 2, "R200_RE_SCISSOR_TL_2" },
126 { R200_SE_VAP_CNTL_STATUS
, 1, "R200_SE_VAP_CNTL_STATUS" },
127 { R200_SE_VTX_STATE_CNTL
, 1, "R200_SE_VTX_STATE_CNTL" },
128 { R200_RE_POINTSIZE
, 1, "R200_RE_POINTSIZE" },
129 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0
, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
130 { R200_PP_CUBIC_FACES_0
, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */
131 { R200_PP_CUBIC_OFFSET_F1_0
, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */
132 { R200_PP_CUBIC_FACES_1
, 1, "R200_PP_CUBIC_FACES_1" },
133 { R200_PP_CUBIC_OFFSET_F1_1
, 5, "R200_PP_CUBIC_OFFSET_F1_1" },
134 { R200_PP_CUBIC_FACES_2
, 1, "R200_PP_CUBIC_FACES_2" },
135 { R200_PP_CUBIC_OFFSET_F1_2
, 5, "R200_PP_CUBIC_OFFSET_F1_2" },
136 { R200_PP_CUBIC_FACES_3
, 1, "R200_PP_CUBIC_FACES_3" },
137 { R200_PP_CUBIC_OFFSET_F1_3
, 5, "R200_PP_CUBIC_OFFSET_F1_3" },
138 { R200_PP_CUBIC_FACES_4
, 1, "R200_PP_CUBIC_FACES_4" },
139 { R200_PP_CUBIC_OFFSET_F1_4
, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
140 { R200_PP_CUBIC_FACES_5
, 1, "R200_PP_CUBIC_FACES_5" },
141 { R200_PP_CUBIC_OFFSET_F1_5
, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
142 { RADEON_PP_TEX_SIZE_0
, 2, "RADEON_PP_TEX_SIZE_0" },
143 { RADEON_PP_TEX_SIZE_1
, 2, "RADEON_PP_TEX_SIZE_1" },
144 { RADEON_PP_TEX_SIZE_2
, 2, "RADEON_PP_TEX_SIZE_2" },
145 { R200_RB3D_BLENDCOLOR
, 3, "R200_RB3D_BLENDCOLOR" },
153 static struct reg_names reg_names
[] = {
154 { R200_PP_MISC
, "R200_PP_MISC" },
155 { R200_PP_FOG_COLOR
, "R200_PP_FOG_COLOR" },
156 { R200_RE_SOLID_COLOR
, "R200_RE_SOLID_COLOR" },
157 { R200_RB3D_BLENDCNTL
, "R200_RB3D_BLENDCNTL" },
158 { R200_RB3D_DEPTHOFFSET
, "R200_RB3D_DEPTHOFFSET" },
159 { R200_RB3D_DEPTHPITCH
, "R200_RB3D_DEPTHPITCH" },
160 { R200_RB3D_ZSTENCILCNTL
, "R200_RB3D_ZSTENCILCNTL" },
161 { R200_PP_CNTL
, "R200_PP_CNTL" },
162 { R200_RB3D_CNTL
, "R200_RB3D_CNTL" },
163 { R200_RB3D_COLOROFFSET
, "R200_RB3D_COLOROFFSET" },
164 { R200_RE_WIDTH_HEIGHT
, "R200_RE_WIDTH_HEIGHT" },
165 { R200_RB3D_COLORPITCH
, "R200_RB3D_COLORPITCH" },
166 { R200_SE_CNTL
, "R200_SE_CNTL" },
167 { R200_RE_CNTL
, "R200_RE_CNTL" },
168 { R200_RE_MISC
, "R200_RE_MISC" },
169 { R200_RE_STIPPLE_ADDR
, "R200_RE_STIPPLE_ADDR" },
170 { R200_RE_STIPPLE_DATA
, "R200_RE_STIPPLE_DATA" },
171 { R200_RE_LINE_PATTERN
, "R200_RE_LINE_PATTERN" },
172 { R200_RE_LINE_STATE
, "R200_RE_LINE_STATE" },
173 { R200_RE_SCISSOR_TL_0
, "R200_RE_SCISSOR_TL_0" },
174 { R200_RE_SCISSOR_BR_0
, "R200_RE_SCISSOR_BR_0" },
175 { R200_RE_SCISSOR_TL_1
, "R200_RE_SCISSOR_TL_1" },
176 { R200_RE_SCISSOR_BR_1
, "R200_RE_SCISSOR_BR_1" },
177 { R200_RE_SCISSOR_TL_2
, "R200_RE_SCISSOR_TL_2" },
178 { R200_RE_SCISSOR_BR_2
, "R200_RE_SCISSOR_BR_2" },
179 { R200_RB3D_DEPTHXY_OFFSET
, "R200_RB3D_DEPTHXY_OFFSET" },
180 { R200_RB3D_STENCILREFMASK
, "R200_RB3D_STENCILREFMASK" },
181 { R200_RB3D_ROPCNTL
, "R200_RB3D_ROPCNTL" },
182 { R200_RB3D_PLANEMASK
, "R200_RB3D_PLANEMASK" },
183 { R200_SE_VPORT_XSCALE
, "R200_SE_VPORT_XSCALE" },
184 { R200_SE_VPORT_XOFFSET
, "R200_SE_VPORT_XOFFSET" },
185 { R200_SE_VPORT_YSCALE
, "R200_SE_VPORT_YSCALE" },
186 { R200_SE_VPORT_YOFFSET
, "R200_SE_VPORT_YOFFSET" },
187 { R200_SE_VPORT_ZSCALE
, "R200_SE_VPORT_ZSCALE" },
188 { R200_SE_VPORT_ZOFFSET
, "R200_SE_VPORT_ZOFFSET" },
189 { R200_SE_ZBIAS_FACTOR
, "R200_SE_ZBIAS_FACTOR" },
190 { R200_SE_ZBIAS_CONSTANT
, "R200_SE_ZBIAS_CONSTANT" },
191 { R200_SE_LINE_WIDTH
, "R200_SE_LINE_WIDTH" },
192 { R200_SE_VAP_CNTL
, "R200_SE_VAP_CNTL" },
193 { R200_SE_VF_CNTL
, "R200_SE_VF_CNTL" },
194 { R200_SE_VTX_FMT_0
, "R200_SE_VTX_FMT_0" },
195 { R200_SE_VTX_FMT_1
, "R200_SE_VTX_FMT_1" },
196 { R200_SE_TCL_OUTPUT_VTX_FMT_0
, "R200_SE_TCL_OUTPUT_VTX_FMT_0" },
197 { R200_SE_TCL_OUTPUT_VTX_FMT_1
, "R200_SE_TCL_OUTPUT_VTX_FMT_1" },
198 { R200_SE_VTE_CNTL
, "R200_SE_VTE_CNTL" },
199 { R200_SE_VTX_NUM_ARRAYS
, "R200_SE_VTX_NUM_ARRAYS" },
200 { R200_SE_VTX_AOS_ATTR01
, "R200_SE_VTX_AOS_ATTR01" },
201 { R200_SE_VTX_AOS_ADDR0
, "R200_SE_VTX_AOS_ADDR0" },
202 { R200_SE_VTX_AOS_ADDR1
, "R200_SE_VTX_AOS_ADDR1" },
203 { R200_SE_VTX_AOS_ATTR23
, "R200_SE_VTX_AOS_ATTR23" },
204 { R200_SE_VTX_AOS_ADDR2
, "R200_SE_VTX_AOS_ADDR2" },
205 { R200_SE_VTX_AOS_ADDR3
, "R200_SE_VTX_AOS_ADDR3" },
206 { R200_SE_VTX_AOS_ATTR45
, "R200_SE_VTX_AOS_ATTR45" },
207 { R200_SE_VTX_AOS_ADDR4
, "R200_SE_VTX_AOS_ADDR4" },
208 { R200_SE_VTX_AOS_ADDR5
, "R200_SE_VTX_AOS_ADDR5" },
209 { R200_SE_VTX_AOS_ATTR67
, "R200_SE_VTX_AOS_ATTR67" },
210 { R200_SE_VTX_AOS_ADDR6
, "R200_SE_VTX_AOS_ADDR6" },
211 { R200_SE_VTX_AOS_ADDR7
, "R200_SE_VTX_AOS_ADDR7" },
212 { R200_SE_VTX_AOS_ATTR89
, "R200_SE_VTX_AOS_ATTR89" },
213 { R200_SE_VTX_AOS_ADDR8
, "R200_SE_VTX_AOS_ADDR8" },
214 { R200_SE_VTX_AOS_ADDR9
, "R200_SE_VTX_AOS_ADDR9" },
215 { R200_SE_VTX_AOS_ATTR1011
, "R200_SE_VTX_AOS_ATTR1011" },
216 { R200_SE_VTX_AOS_ADDR10
, "R200_SE_VTX_AOS_ADDR10" },
217 { R200_SE_VTX_AOS_ADDR11
, "R200_SE_VTX_AOS_ADDR11" },
218 { R200_SE_VF_MAX_VTX_INDX
, "R200_SE_VF_MAX_VTX_INDX" },
219 { R200_SE_VF_MIN_VTX_INDX
, "R200_SE_VF_MIN_VTX_INDX" },
220 { R200_SE_VTX_STATE_CNTL
, "R200_SE_VTX_STATE_CNTL" },
221 { R200_SE_TCL_VECTOR_INDX_REG
, "R200_SE_TCL_VECTOR_INDX_REG" },
222 { R200_SE_TCL_VECTOR_DATA_REG
, "R200_SE_TCL_VECTOR_DATA_REG" },
223 { R200_SE_TCL_SCALAR_INDX_REG
, "R200_SE_TCL_SCALAR_INDX_REG" },
224 { R200_SE_TCL_SCALAR_DATA_REG
, "R200_SE_TCL_SCALAR_DATA_REG" },
225 { R200_SE_TCL_MATRIX_SEL_0
, "R200_SE_TCL_MATRIX_SEL_0" },
226 { R200_SE_TCL_MATRIX_SEL_1
, "R200_SE_TCL_MATRIX_SEL_1" },
227 { R200_SE_TCL_MATRIX_SEL_2
, "R200_SE_TCL_MATRIX_SEL_2" },
228 { R200_SE_TCL_MATRIX_SEL_3
, "R200_SE_TCL_MATRIX_SEL_3" },
229 { R200_SE_TCL_MATRIX_SEL_4
, "R200_SE_TCL_MATRIX_SEL_4" },
230 { R200_SE_TCL_LIGHT_MODEL_CTL_0
, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
231 { R200_SE_TCL_LIGHT_MODEL_CTL_1
, "R200_SE_TCL_LIGHT_MODEL_CTL_1" },
232 { R200_SE_TCL_PER_LIGHT_CTL_0
, "R200_SE_TCL_PER_LIGHT_CTL_0" },
233 { R200_SE_TCL_PER_LIGHT_CTL_1
, "R200_SE_TCL_PER_LIGHT_CTL_1" },
234 { R200_SE_TCL_PER_LIGHT_CTL_2
, "R200_SE_TCL_PER_LIGHT_CTL_2" },
235 { R200_SE_TCL_PER_LIGHT_CTL_3
, "R200_SE_TCL_PER_LIGHT_CTL_3" },
236 { R200_SE_TCL_TEX_PROC_CTL_2
, "R200_SE_TCL_TEX_PROC_CTL_2" },
237 { R200_SE_TCL_TEX_PROC_CTL_3
, "R200_SE_TCL_TEX_PROC_CTL_3" },
238 { R200_SE_TCL_TEX_PROC_CTL_0
, "R200_SE_TCL_TEX_PROC_CTL_0" },
239 { R200_SE_TCL_TEX_PROC_CTL_1
, "R200_SE_TCL_TEX_PROC_CTL_1" },
240 { R200_SE_TC_TEX_CYL_WRAP_CTL
, "R200_SE_TC_TEX_CYL_WRAP_CTL" },
241 { R200_SE_TCL_UCP_VERT_BLEND_CTL
, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
242 { R200_SE_TCL_POINT_SPRITE_CNTL
, "R200_SE_TCL_POINT_SPRITE_CNTL" },
243 { R200_SE_VTX_ST_POS_0_X_4
, "R200_SE_VTX_ST_POS_0_X_4" },
244 { R200_SE_VTX_ST_POS_0_Y_4
, "R200_SE_VTX_ST_POS_0_Y_4" },
245 { R200_SE_VTX_ST_POS_0_Z_4
, "R200_SE_VTX_ST_POS_0_Z_4" },
246 { R200_SE_VTX_ST_POS_0_W_4
, "R200_SE_VTX_ST_POS_0_W_4" },
247 { R200_SE_VTX_ST_NORM_0_X
, "R200_SE_VTX_ST_NORM_0_X" },
248 { R200_SE_VTX_ST_NORM_0_Y
, "R200_SE_VTX_ST_NORM_0_Y" },
249 { R200_SE_VTX_ST_NORM_0_Z
, "R200_SE_VTX_ST_NORM_0_Z" },
250 { R200_SE_VTX_ST_PVMS
, "R200_SE_VTX_ST_PVMS" },
251 { R200_SE_VTX_ST_CLR_0_R
, "R200_SE_VTX_ST_CLR_0_R" },
252 { R200_SE_VTX_ST_CLR_0_G
, "R200_SE_VTX_ST_CLR_0_G" },
253 { R200_SE_VTX_ST_CLR_0_B
, "R200_SE_VTX_ST_CLR_0_B" },
254 { R200_SE_VTX_ST_CLR_0_A
, "R200_SE_VTX_ST_CLR_0_A" },
255 { R200_SE_VTX_ST_CLR_1_R
, "R200_SE_VTX_ST_CLR_1_R" },
256 { R200_SE_VTX_ST_CLR_1_G
, "R200_SE_VTX_ST_CLR_1_G" },
257 { R200_SE_VTX_ST_CLR_1_B
, "R200_SE_VTX_ST_CLR_1_B" },
258 { R200_SE_VTX_ST_CLR_1_A
, "R200_SE_VTX_ST_CLR_1_A" },
259 { R200_SE_VTX_ST_CLR_2_R
, "R200_SE_VTX_ST_CLR_2_R" },
260 { R200_SE_VTX_ST_CLR_2_G
, "R200_SE_VTX_ST_CLR_2_G" },
261 { R200_SE_VTX_ST_CLR_2_B
, "R200_SE_VTX_ST_CLR_2_B" },
262 { R200_SE_VTX_ST_CLR_2_A
, "R200_SE_VTX_ST_CLR_2_A" },
263 { R200_SE_VTX_ST_CLR_3_R
, "R200_SE_VTX_ST_CLR_3_R" },
264 { R200_SE_VTX_ST_CLR_3_G
, "R200_SE_VTX_ST_CLR_3_G" },
265 { R200_SE_VTX_ST_CLR_3_B
, "R200_SE_VTX_ST_CLR_3_B" },
266 { R200_SE_VTX_ST_CLR_3_A
, "R200_SE_VTX_ST_CLR_3_A" },
267 { R200_SE_VTX_ST_CLR_4_R
, "R200_SE_VTX_ST_CLR_4_R" },
268 { R200_SE_VTX_ST_CLR_4_G
, "R200_SE_VTX_ST_CLR_4_G" },
269 { R200_SE_VTX_ST_CLR_4_B
, "R200_SE_VTX_ST_CLR_4_B" },
270 { R200_SE_VTX_ST_CLR_4_A
, "R200_SE_VTX_ST_CLR_4_A" },
271 { R200_SE_VTX_ST_CLR_5_R
, "R200_SE_VTX_ST_CLR_5_R" },
272 { R200_SE_VTX_ST_CLR_5_G
, "R200_SE_VTX_ST_CLR_5_G" },
273 { R200_SE_VTX_ST_CLR_5_B
, "R200_SE_VTX_ST_CLR_5_B" },
274 { R200_SE_VTX_ST_CLR_5_A
, "R200_SE_VTX_ST_CLR_5_A" },
275 { R200_SE_VTX_ST_CLR_6_R
, "R200_SE_VTX_ST_CLR_6_R" },
276 { R200_SE_VTX_ST_CLR_6_G
, "R200_SE_VTX_ST_CLR_6_G" },
277 { R200_SE_VTX_ST_CLR_6_B
, "R200_SE_VTX_ST_CLR_6_B" },
278 { R200_SE_VTX_ST_CLR_6_A
, "R200_SE_VTX_ST_CLR_6_A" },
279 { R200_SE_VTX_ST_CLR_7_R
, "R200_SE_VTX_ST_CLR_7_R" },
280 { R200_SE_VTX_ST_CLR_7_G
, "R200_SE_VTX_ST_CLR_7_G" },
281 { R200_SE_VTX_ST_CLR_7_B
, "R200_SE_VTX_ST_CLR_7_B" },
282 { R200_SE_VTX_ST_CLR_7_A
, "R200_SE_VTX_ST_CLR_7_A" },
283 { R200_SE_VTX_ST_TEX_0_S
, "R200_SE_VTX_ST_TEX_0_S" },
284 { R200_SE_VTX_ST_TEX_0_T
, "R200_SE_VTX_ST_TEX_0_T" },
285 { R200_SE_VTX_ST_TEX_0_R
, "R200_SE_VTX_ST_TEX_0_R" },
286 { R200_SE_VTX_ST_TEX_0_Q
, "R200_SE_VTX_ST_TEX_0_Q" },
287 { R200_SE_VTX_ST_TEX_1_S
, "R200_SE_VTX_ST_TEX_1_S" },
288 { R200_SE_VTX_ST_TEX_1_T
, "R200_SE_VTX_ST_TEX_1_T" },
289 { R200_SE_VTX_ST_TEX_1_R
, "R200_SE_VTX_ST_TEX_1_R" },
290 { R200_SE_VTX_ST_TEX_1_Q
, "R200_SE_VTX_ST_TEX_1_Q" },
291 { R200_SE_VTX_ST_TEX_2_S
, "R200_SE_VTX_ST_TEX_2_S" },
292 { R200_SE_VTX_ST_TEX_2_T
, "R200_SE_VTX_ST_TEX_2_T" },
293 { R200_SE_VTX_ST_TEX_2_R
, "R200_SE_VTX_ST_TEX_2_R" },
294 { R200_SE_VTX_ST_TEX_2_Q
, "R200_SE_VTX_ST_TEX_2_Q" },
295 { R200_SE_VTX_ST_TEX_3_S
, "R200_SE_VTX_ST_TEX_3_S" },
296 { R200_SE_VTX_ST_TEX_3_T
, "R200_SE_VTX_ST_TEX_3_T" },
297 { R200_SE_VTX_ST_TEX_3_R
, "R200_SE_VTX_ST_TEX_3_R" },
298 { R200_SE_VTX_ST_TEX_3_Q
, "R200_SE_VTX_ST_TEX_3_Q" },
299 { R200_SE_VTX_ST_TEX_4_S
, "R200_SE_VTX_ST_TEX_4_S" },
300 { R200_SE_VTX_ST_TEX_4_T
, "R200_SE_VTX_ST_TEX_4_T" },
301 { R200_SE_VTX_ST_TEX_4_R
, "R200_SE_VTX_ST_TEX_4_R" },
302 { R200_SE_VTX_ST_TEX_4_Q
, "R200_SE_VTX_ST_TEX_4_Q" },
303 { R200_SE_VTX_ST_TEX_5_S
, "R200_SE_VTX_ST_TEX_5_S" },
304 { R200_SE_VTX_ST_TEX_5_T
, "R200_SE_VTX_ST_TEX_5_T" },
305 { R200_SE_VTX_ST_TEX_5_R
, "R200_SE_VTX_ST_TEX_5_R" },
306 { R200_SE_VTX_ST_TEX_5_Q
, "R200_SE_VTX_ST_TEX_5_Q" },
307 { R200_SE_VTX_ST_PNT_SPRT_SZ
, "R200_SE_VTX_ST_PNT_SPRT_SZ" },
308 { R200_SE_VTX_ST_DISC_FOG
, "R200_SE_VTX_ST_DISC_FOG" },
309 { R200_SE_VTX_ST_SHININESS_0
, "R200_SE_VTX_ST_SHININESS_0" },
310 { R200_SE_VTX_ST_SHININESS_1
, "R200_SE_VTX_ST_SHININESS_1" },
311 { R200_SE_VTX_ST_BLND_WT_0
, "R200_SE_VTX_ST_BLND_WT_0" },
312 { R200_SE_VTX_ST_BLND_WT_1
, "R200_SE_VTX_ST_BLND_WT_1" },
313 { R200_SE_VTX_ST_BLND_WT_2
, "R200_SE_VTX_ST_BLND_WT_2" },
314 { R200_SE_VTX_ST_BLND_WT_3
, "R200_SE_VTX_ST_BLND_WT_3" },
315 { R200_SE_VTX_ST_POS_1_X
, "R200_SE_VTX_ST_POS_1_X" },
316 { R200_SE_VTX_ST_POS_1_Y
, "R200_SE_VTX_ST_POS_1_Y" },
317 { R200_SE_VTX_ST_POS_1_Z
, "R200_SE_VTX_ST_POS_1_Z" },
318 { R200_SE_VTX_ST_POS_1_W
, "R200_SE_VTX_ST_POS_1_W" },
319 { R200_SE_VTX_ST_NORM_1_X
, "R200_SE_VTX_ST_NORM_1_X" },
320 { R200_SE_VTX_ST_NORM_1_Y
, "R200_SE_VTX_ST_NORM_1_Y" },
321 { R200_SE_VTX_ST_NORM_1_Z
, "R200_SE_VTX_ST_NORM_1_Z" },
322 { R200_SE_VTX_ST_USR_CLR_0_R
, "R200_SE_VTX_ST_USR_CLR_0_R" },
323 { R200_SE_VTX_ST_USR_CLR_0_G
, "R200_SE_VTX_ST_USR_CLR_0_G" },
324 { R200_SE_VTX_ST_USR_CLR_0_B
, "R200_SE_VTX_ST_USR_CLR_0_B" },
325 { R200_SE_VTX_ST_USR_CLR_0_A
, "R200_SE_VTX_ST_USR_CLR_0_A" },
326 { R200_SE_VTX_ST_USR_CLR_1_R
, "R200_SE_VTX_ST_USR_CLR_1_R" },
327 { R200_SE_VTX_ST_USR_CLR_1_G
, "R200_SE_VTX_ST_USR_CLR_1_G" },
328 { R200_SE_VTX_ST_USR_CLR_1_B
, "R200_SE_VTX_ST_USR_CLR_1_B" },
329 { R200_SE_VTX_ST_USR_CLR_1_A
, "R200_SE_VTX_ST_USR_CLR_1_A" },
330 { R200_SE_VTX_ST_CLR_0_PKD
, "R200_SE_VTX_ST_CLR_0_PKD" },
331 { R200_SE_VTX_ST_CLR_1_PKD
, "R200_SE_VTX_ST_CLR_1_PKD" },
332 { R200_SE_VTX_ST_CLR_2_PKD
, "R200_SE_VTX_ST_CLR_2_PKD" },
333 { R200_SE_VTX_ST_CLR_3_PKD
, "R200_SE_VTX_ST_CLR_3_PKD" },
334 { R200_SE_VTX_ST_CLR_4_PKD
, "R200_SE_VTX_ST_CLR_4_PKD" },
335 { R200_SE_VTX_ST_CLR_5_PKD
, "R200_SE_VTX_ST_CLR_5_PKD" },
336 { R200_SE_VTX_ST_CLR_6_PKD
, "R200_SE_VTX_ST_CLR_6_PKD" },
337 { R200_SE_VTX_ST_CLR_7_PKD
, "R200_SE_VTX_ST_CLR_7_PKD" },
338 { R200_SE_VTX_ST_POS_0_X_2
, "R200_SE_VTX_ST_POS_0_X_2" },
339 { R200_SE_VTX_ST_POS_0_Y_2
, "R200_SE_VTX_ST_POS_0_Y_2" },
340 { R200_SE_VTX_ST_PAR_CLR_LD
, "R200_SE_VTX_ST_PAR_CLR_LD" },
341 { R200_SE_VTX_ST_USR_CLR_PKD
, "R200_SE_VTX_ST_USR_CLR_PKD" },
342 { R200_SE_VTX_ST_POS_0_X_3
, "R200_SE_VTX_ST_POS_0_X_3" },
343 { R200_SE_VTX_ST_POS_0_Y_3
, "R200_SE_VTX_ST_POS_0_Y_3" },
344 { R200_SE_VTX_ST_POS_0_Z_3
, "R200_SE_VTX_ST_POS_0_Z_3" },
345 { R200_SE_VTX_ST_END_OF_PKT
, "R200_SE_VTX_ST_END_OF_PKT" },
346 { R200_RE_POINTSIZE
, "R200_RE_POINTSIZE" },
347 { R200_RE_TOP_LEFT
, "R200_RE_TOP_LEFT" },
348 { R200_RE_AUX_SCISSOR_CNTL
, "R200_RE_AUX_SCISSOR_CNTL" },
349 { R200_PP_TXFILTER_0
, "R200_PP_TXFILTER_0" },
350 { R200_PP_TXFORMAT_0
, "R200_PP_TXFORMAT_0" },
351 { R200_PP_TXSIZE_0
, "R200_PP_TXSIZE_0" },
352 { R200_PP_TXFORMAT_X_0
, "R200_PP_TXFORMAT_X_0" },
353 { R200_PP_TXPITCH_0
, "R200_PP_TXPITCH_0" },
354 { R200_PP_BORDER_COLOR_0
, "R200_PP_BORDER_COLOR_0" },
355 { R200_PP_CUBIC_FACES_0
, "R200_PP_CUBIC_FACES_0" },
356 { R200_PP_TXFILTER_1
, "R200_PP_TXFILTER_1" },
357 { R200_PP_TXFORMAT_1
, "R200_PP_TXFORMAT_1" },
358 { R200_PP_TXSIZE_1
, "R200_PP_TXSIZE_1" },
359 { R200_PP_TXFORMAT_X_1
, "R200_PP_TXFORMAT_X_1" },
360 { R200_PP_TXPITCH_1
, "R200_PP_TXPITCH_1" },
361 { R200_PP_BORDER_COLOR_1
, "R200_PP_BORDER_COLOR_1" },
362 { R200_PP_CUBIC_FACES_1
, "R200_PP_CUBIC_FACES_1" },
363 { R200_PP_TXFILTER_2
, "R200_PP_TXFILTER_2" },
364 { R200_PP_TXFORMAT_2
, "R200_PP_TXFORMAT_2" },
365 { R200_PP_TXSIZE_2
, "R200_PP_TXSIZE_2" },
366 { R200_PP_TXFORMAT_X_2
, "R200_PP_TXFORMAT_X_2" },
367 { R200_PP_TXPITCH_2
, "R200_PP_TXPITCH_2" },
368 { R200_PP_BORDER_COLOR_2
, "R200_PP_BORDER_COLOR_2" },
369 { R200_PP_CUBIC_FACES_2
, "R200_PP_CUBIC_FACES_2" },
370 { R200_PP_TXFILTER_3
, "R200_PP_TXFILTER_3" },
371 { R200_PP_TXFORMAT_3
, "R200_PP_TXFORMAT_3" },
372 { R200_PP_TXSIZE_3
, "R200_PP_TXSIZE_3" },
373 { R200_PP_TXFORMAT_X_3
, "R200_PP_TXFORMAT_X_3" },
374 { R200_PP_TXPITCH_3
, "R200_PP_TXPITCH_3" },
375 { R200_PP_BORDER_COLOR_3
, "R200_PP_BORDER_COLOR_3" },
376 { R200_PP_CUBIC_FACES_3
, "R200_PP_CUBIC_FACES_3" },
377 { R200_PP_TXFILTER_4
, "R200_PP_TXFILTER_4" },
378 { R200_PP_TXFORMAT_4
, "R200_PP_TXFORMAT_4" },
379 { R200_PP_TXSIZE_4
, "R200_PP_TXSIZE_4" },
380 { R200_PP_TXFORMAT_X_4
, "R200_PP_TXFORMAT_X_4" },
381 { R200_PP_TXPITCH_4
, "R200_PP_TXPITCH_4" },
382 { R200_PP_BORDER_COLOR_4
, "R200_PP_BORDER_COLOR_4" },
383 { R200_PP_CUBIC_FACES_4
, "R200_PP_CUBIC_FACES_4" },
384 { R200_PP_TXFILTER_5
, "R200_PP_TXFILTER_5" },
385 { R200_PP_TXFORMAT_5
, "R200_PP_TXFORMAT_5" },
386 { R200_PP_TXSIZE_5
, "R200_PP_TXSIZE_5" },
387 { R200_PP_TXFORMAT_X_5
, "R200_PP_TXFORMAT_X_5" },
388 { R200_PP_TXPITCH_5
, "R200_PP_TXPITCH_5" },
389 { R200_PP_BORDER_COLOR_5
, "R200_PP_BORDER_COLOR_5" },
390 { R200_PP_CUBIC_FACES_5
, "R200_PP_CUBIC_FACES_5" },
391 { R200_PP_TXOFFSET_0
, "R200_PP_TXOFFSET_0" },
392 { R200_PP_CUBIC_OFFSET_F1_0
, "R200_PP_CUBIC_OFFSET_F1_0" },
393 { R200_PP_CUBIC_OFFSET_F2_0
, "R200_PP_CUBIC_OFFSET_F2_0" },
394 { R200_PP_CUBIC_OFFSET_F3_0
, "R200_PP_CUBIC_OFFSET_F3_0" },
395 { R200_PP_CUBIC_OFFSET_F4_0
, "R200_PP_CUBIC_OFFSET_F4_0" },
396 { R200_PP_CUBIC_OFFSET_F5_0
, "R200_PP_CUBIC_OFFSET_F5_0" },
397 { R200_PP_TXOFFSET_1
, "R200_PP_TXOFFSET_1" },
398 { R200_PP_CUBIC_OFFSET_F1_1
, "R200_PP_CUBIC_OFFSET_F1_1" },
399 { R200_PP_CUBIC_OFFSET_F2_1
, "R200_PP_CUBIC_OFFSET_F2_1" },
400 { R200_PP_CUBIC_OFFSET_F3_1
, "R200_PP_CUBIC_OFFSET_F3_1" },
401 { R200_PP_CUBIC_OFFSET_F4_1
, "R200_PP_CUBIC_OFFSET_F4_1" },
402 { R200_PP_CUBIC_OFFSET_F5_1
, "R200_PP_CUBIC_OFFSET_F5_1" },
403 { R200_PP_TXOFFSET_2
, "R200_PP_TXOFFSET_2" },
404 { R200_PP_CUBIC_OFFSET_F1_2
, "R200_PP_CUBIC_OFFSET_F1_2" },
405 { R200_PP_CUBIC_OFFSET_F2_2
, "R200_PP_CUBIC_OFFSET_F2_2" },
406 { R200_PP_CUBIC_OFFSET_F3_2
, "R200_PP_CUBIC_OFFSET_F3_2" },
407 { R200_PP_CUBIC_OFFSET_F4_2
, "R200_PP_CUBIC_OFFSET_F4_2" },
408 { R200_PP_CUBIC_OFFSET_F5_2
, "R200_PP_CUBIC_OFFSET_F5_2" },
409 { R200_PP_TXOFFSET_3
, "R200_PP_TXOFFSET_3" },
410 { R200_PP_CUBIC_OFFSET_F1_3
, "R200_PP_CUBIC_OFFSET_F1_3" },
411 { R200_PP_CUBIC_OFFSET_F2_3
, "R200_PP_CUBIC_OFFSET_F2_3" },
412 { R200_PP_CUBIC_OFFSET_F3_3
, "R200_PP_CUBIC_OFFSET_F3_3" },
413 { R200_PP_CUBIC_OFFSET_F4_3
, "R200_PP_CUBIC_OFFSET_F4_3" },
414 { R200_PP_CUBIC_OFFSET_F5_3
, "R200_PP_CUBIC_OFFSET_F5_3" },
415 { R200_PP_TXOFFSET_4
, "R200_PP_TXOFFSET_4" },
416 { R200_PP_CUBIC_OFFSET_F1_4
, "R200_PP_CUBIC_OFFSET_F1_4" },
417 { R200_PP_CUBIC_OFFSET_F2_4
, "R200_PP_CUBIC_OFFSET_F2_4" },
418 { R200_PP_CUBIC_OFFSET_F3_4
, "R200_PP_CUBIC_OFFSET_F3_4" },
419 { R200_PP_CUBIC_OFFSET_F4_4
, "R200_PP_CUBIC_OFFSET_F4_4" },
420 { R200_PP_CUBIC_OFFSET_F5_4
, "R200_PP_CUBIC_OFFSET_F5_4" },
421 { R200_PP_TXOFFSET_5
, "R200_PP_TXOFFSET_5" },
422 { R200_PP_CUBIC_OFFSET_F1_5
, "R200_PP_CUBIC_OFFSET_F1_5" },
423 { R200_PP_CUBIC_OFFSET_F2_5
, "R200_PP_CUBIC_OFFSET_F2_5" },
424 { R200_PP_CUBIC_OFFSET_F3_5
, "R200_PP_CUBIC_OFFSET_F3_5" },
425 { R200_PP_CUBIC_OFFSET_F4_5
, "R200_PP_CUBIC_OFFSET_F4_5" },
426 { R200_PP_CUBIC_OFFSET_F5_5
, "R200_PP_CUBIC_OFFSET_F5_5" },
427 { R200_PP_TAM_DEBUG3
, "R200_PP_TAM_DEBUG3" },
428 { R200_PP_TFACTOR_0
, "R200_PP_TFACTOR_0" },
429 { R200_PP_TFACTOR_1
, "R200_PP_TFACTOR_1" },
430 { R200_PP_TFACTOR_2
, "R200_PP_TFACTOR_2" },
431 { R200_PP_TFACTOR_3
, "R200_PP_TFACTOR_3" },
432 { R200_PP_TFACTOR_4
, "R200_PP_TFACTOR_4" },
433 { R200_PP_TFACTOR_5
, "R200_PP_TFACTOR_5" },
434 { R200_PP_TXCBLEND_0
, "R200_PP_TXCBLEND_0" },
435 { R200_PP_TXCBLEND2_0
, "R200_PP_TXCBLEND2_0" },
436 { R200_PP_TXABLEND_0
, "R200_PP_TXABLEND_0" },
437 { R200_PP_TXABLEND2_0
, "R200_PP_TXABLEND2_0" },
438 { R200_PP_TXCBLEND_1
, "R200_PP_TXCBLEND_1" },
439 { R200_PP_TXCBLEND2_1
, "R200_PP_TXCBLEND2_1" },
440 { R200_PP_TXABLEND_1
, "R200_PP_TXABLEND_1" },
441 { R200_PP_TXABLEND2_1
, "R200_PP_TXABLEND2_1" },
442 { R200_PP_TXCBLEND_2
, "R200_PP_TXCBLEND_2" },
443 { R200_PP_TXCBLEND2_2
, "R200_PP_TXCBLEND2_2" },
444 { R200_PP_TXABLEND_2
, "R200_PP_TXABLEND_2" },
445 { R200_PP_TXABLEND2_2
, "R200_PP_TXABLEND2_2" },
446 { R200_PP_TXCBLEND_3
, "R200_PP_TXCBLEND_3" },
447 { R200_PP_TXCBLEND2_3
, "R200_PP_TXCBLEND2_3" },
448 { R200_PP_TXABLEND_3
, "R200_PP_TXABLEND_3" },
449 { R200_PP_TXABLEND2_3
, "R200_PP_TXABLEND2_3" },
450 { R200_PP_TXCBLEND_4
, "R200_PP_TXCBLEND_4" },
451 { R200_PP_TXCBLEND2_4
, "R200_PP_TXCBLEND2_4" },
452 { R200_PP_TXABLEND_4
, "R200_PP_TXABLEND_4" },
453 { R200_PP_TXABLEND2_4
, "R200_PP_TXABLEND2_4" },
454 { R200_PP_TXCBLEND_5
, "R200_PP_TXCBLEND_5" },
455 { R200_PP_TXCBLEND2_5
, "R200_PP_TXCBLEND2_5" },
456 { R200_PP_TXABLEND_5
, "R200_PP_TXABLEND_5" },
457 { R200_PP_TXABLEND2_5
, "R200_PP_TXABLEND2_5" },
458 { R200_PP_TXCBLEND_6
, "R200_PP_TXCBLEND_6" },
459 { R200_PP_TXCBLEND2_6
, "R200_PP_TXCBLEND2_6" },
460 { R200_PP_TXABLEND_6
, "R200_PP_TXABLEND_6" },
461 { R200_PP_TXABLEND2_6
, "R200_PP_TXABLEND2_6" },
462 { R200_PP_TXCBLEND_7
, "R200_PP_TXCBLEND_7" },
463 { R200_PP_TXCBLEND2_7
, "R200_PP_TXCBLEND2_7" },
464 { R200_PP_TXABLEND_7
, "R200_PP_TXABLEND_7" },
465 { R200_PP_TXABLEND2_7
, "R200_PP_TXABLEND2_7" },
466 { R200_RB3D_BLENDCOLOR
, "R200_RB3D_BLENDCOLOR" },
467 { R200_RB3D_ABLENDCNTL
, "R200_RB3D_ABLENDCNTL" },
468 { R200_RB3D_CBLENDCNTL
, "R200_RB3D_CBLENDCNTL" },
469 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL
, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
470 { R200_PP_CNTL_X
, "R200_PP_CNTL_X" },
471 { R200_SE_VAP_CNTL_STATUS
, "R200_SE_VAP_CNTL_STATUS" },
472 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0
, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
473 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1
, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
474 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2
, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
475 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3
, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
478 static struct reg_names scalar_names
[] = {
479 { R200_SS_LIGHT_DCD_ADDR
, "R200_SS_LIGHT_DCD_ADDR" },
480 { R200_SS_LIGHT_DCM_ADDR
, "R200_SS_LIGHT_DCM_ADDR" },
481 { R200_SS_LIGHT_SPOT_EXPONENT_ADDR
, "R200_SS_LIGHT_SPOT_EXPONENT_ADDR" },
482 { R200_SS_LIGHT_SPOT_CUTOFF_ADDR
, "R200_SS_LIGHT_SPOT_CUTOFF_ADDR" },
483 { R200_SS_LIGHT_SPECULAR_THRESH_ADDR
, "R200_SS_LIGHT_SPECULAR_THRESH_ADDR" },
484 { R200_SS_LIGHT_RANGE_CUTOFF_SQRD
, "R200_SS_LIGHT_RANGE_CUTOFF_SQRD" },
485 { R200_SS_LIGHT_RANGE_ATT_CONST
, "R200_SS_LIGHT_RANGE_ATT_CONST" },
486 { R200_SS_VERT_GUARD_CLIP_ADJ_ADDR
, "R200_SS_VERT_GUARD_CLIP_ADJ_ADDR" },
487 { R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR
, "R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR" },
488 { R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR
, "R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR" },
489 { R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR
, "R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR" },
490 { R200_SS_MAT_0_SHININESS
, "R200_SS_MAT_0_SHININESS" },
491 { R200_SS_MAT_1_SHININESS
, "R200_SS_MAT_1_SHININESS" },
495 /* Puff these out to make them look like normal (dword) registers.
497 static struct reg_names vector_names
[] = {
499 { R200_VS_LIGHT_AMBIENT_ADDR
, "R200_VS_LIGHT_AMBIENT_ADDR" },
500 { R200_VS_LIGHT_DIFFUSE_ADDR
, "R200_VS_LIGHT_DIFFUSE_ADDR" },
501 { R200_VS_LIGHT_SPECULAR_ADDR
, "R200_VS_LIGHT_SPECULAR_ADDR" },
502 { R200_VS_LIGHT_DIRPOS_ADDR
, "R200_VS_LIGHT_DIRPOS_ADDR" },
503 { R200_VS_LIGHT_HWVSPOT_ADDR
, "R200_VS_LIGHT_HWVSPOT_ADDR" },
504 { R200_VS_LIGHT_ATTENUATION_ADDR
, "R200_VS_LIGHT_ATTENUATION_ADDR" },
505 { R200_VS_SPOT_DUAL_CONE
, "R200_VS_SPOT_DUAL_CONE" },
506 { R200_VS_GLOBAL_AMBIENT_ADDR
, "R200_VS_GLOBAL_AMBIENT_ADDR" },
507 { R200_VS_FOG_PARAM_ADDR
, "R200_VS_FOG_PARAM_ADDR" },
508 { R200_VS_EYE_VECTOR_ADDR
, "R200_VS_EYE_VECTOR_ADDR" },
509 { R200_VS_UCP_ADDR
, "R200_VS_UCP_ADDR" },
510 { R200_VS_PNT_SPRITE_VPORT_SCALE
, "R200_VS_PNT_SPRITE_VPORT_SCALE" },
511 { R200_VS_MATRIX_0_MV
, "R200_VS_MATRIX_0_MV" },
512 { R200_VS_MATRIX_1_INV_MV
, "R200_VS_MATRIX_1_INV_MV" },
513 { R200_VS_MATRIX_2_MVP
, "R200_VS_MATRIX_2_MVP" },
514 { R200_VS_MATRIX_3_TEX0
, "R200_VS_MATRIX_3_TEX0" },
515 { R200_VS_MATRIX_4_TEX1
, "R200_VS_MATRIX_4_TEX1" },
516 { R200_VS_MATRIX_5_TEX2
, "R200_VS_MATRIX_5_TEX2" },
517 { R200_VS_MATRIX_6_TEX3
, "R200_VS_MATRIX_6_TEX3" },
518 { R200_VS_MATRIX_7_TEX4
, "R200_VS_MATRIX_7_TEX4" },
519 { R200_VS_MATRIX_8_TEX5
, "R200_VS_MATRIX_8_TEX5" },
520 { R200_VS_MAT_0_EMISS
, "R200_VS_MAT_0_EMISS" },
521 { R200_VS_MAT_0_AMB
, "R200_VS_MAT_0_AMB" },
522 { R200_VS_MAT_0_DIF
, "R200_VS_MAT_0_DIF" },
523 { R200_VS_MAT_0_SPEC
, "R200_VS_MAT_0_SPEC" },
524 { R200_VS_MAT_1_EMISS
, "R200_VS_MAT_1_EMISS" },
525 { R200_VS_MAT_1_AMB
, "R200_VS_MAT_1_AMB" },
526 { R200_VS_MAT_1_DIF
, "R200_VS_MAT_1_DIF" },
527 { R200_VS_MAT_1_SPEC
, "R200_VS_MAT_1_SPEC" },
528 { R200_VS_EYE2CLIP_MTX
, "R200_VS_EYE2CLIP_MTX" },
529 { R200_VS_PNT_SPRITE_ATT_CONST
, "R200_VS_PNT_SPRITE_ATT_CONST" },
530 { R200_VS_PNT_SPRITE_EYE_IN_MODEL
, "R200_VS_PNT_SPRITE_EYE_IN_MODEL" },
531 { R200_VS_PNT_SPRITE_CLAMP
, "R200_VS_PNT_SPRITE_CLAMP" },
532 { R200_VS_MAX
, "R200_VS_MAX" },
536 union fi
{ float f
; int i
; };
544 struct reg_names
*closest
;
554 static struct reg regs
[Elements(reg_names
)+1];
555 static struct reg scalars
[512+1];
556 static struct reg vectors
[512*4+1];
558 static int total
, total_changed
, bufs
;
560 static void init_regs( void )
562 struct reg_names
*tmp
;
565 for (i
= 0 ; i
< Elements(regs
) ; i
++) {
566 regs
[i
].idx
= reg_names
[i
].idx
;
567 regs
[i
].closest
= ®_names
[i
];
571 for (i
= 0, tmp
= scalar_names
; i
< Elements(scalars
) ; i
++) {
572 if (tmp
[1].idx
== i
) tmp
++;
574 scalars
[i
].closest
= tmp
;
575 scalars
[i
].flags
= ISFLOAT
;
578 for (i
= 0, tmp
= vector_names
; i
< Elements(vectors
) ; i
++) {
579 if (tmp
[1].idx
*4 == i
) tmp
++;
581 vectors
[i
].closest
= tmp
;
582 vectors
[i
].flags
= ISFLOAT
|ISVEC
;
585 regs
[Elements(regs
)-1].idx
= -1;
586 scalars
[Elements(scalars
)-1].idx
= -1;
587 vectors
[Elements(vectors
)-1].idx
= -1;
590 static int find_or_add_value( struct reg
*reg
, int val
)
594 for ( j
= 0 ; j
< reg
->nvalues
; j
++)
595 if ( val
== reg
->values
[j
].i
)
598 if (j
== reg
->nalloc
) {
601 reg
->values
= (union fi
*) realloc( reg
->values
,
602 reg
->nalloc
* sizeof(union fi
) );
605 reg
->values
[reg
->nvalues
++].i
= val
;
609 static struct reg
*lookup_reg( struct reg
*tab
, int reg
)
613 for (i
= 0 ; tab
[i
].idx
!= -1 ; i
++) {
614 if (tab
[i
].idx
== reg
)
618 fprintf(stderr
, "*** unknown reg 0x%x\n", reg
);
623 static const char *get_reg_name( struct reg
*reg
)
627 if (reg
->idx
== reg
->closest
->idx
)
628 return reg
->closest
->name
;
631 if (reg
->flags
& ISVEC
) {
632 if (reg
->idx
/4 != reg
->closest
->idx
)
633 sprintf(tmp
, "%s+%d[%d]",
635 (reg
->idx
/4) - reg
->closest
->idx
,
638 sprintf(tmp
, "%s[%d]", reg
->closest
->name
, reg
->idx
%4);
641 if (reg
->idx
!= reg
->closest
->idx
)
642 sprintf(tmp
, "%s+%d", reg
->closest
->name
, reg
->idx
- reg
->closest
->idx
);
644 sprintf(tmp
, "%s", reg
->closest
->name
);
650 static int print_int_reg_assignment( struct reg
*reg
, int data
)
652 int changed
= (reg
->current
.i
!= data
);
653 int ever_seen
= find_or_add_value( reg
, data
);
655 if (VERBOSE
|| (NORMAL
&& (changed
|| !ever_seen
)))
656 fprintf(stderr
, " %s <-- 0x%x", get_reg_name(reg
), data
);
660 fprintf(stderr
, " *** BRAND NEW VALUE");
662 fprintf(stderr
, " *** CHANGED");
665 reg
->current
.i
= data
;
667 if (VERBOSE
|| (NORMAL
&& (changed
|| !ever_seen
)))
668 fprintf(stderr
, "\n");
674 static int print_float_reg_assignment( struct reg
*reg
, float data
)
676 int changed
= (reg
->current
.f
!= data
);
677 int newmin
= (data
< reg
->vmin
);
678 int newmax
= (data
> reg
->vmax
);
680 if (VERBOSE
|| (NORMAL
&& (newmin
|| newmax
|| changed
)))
681 fprintf(stderr
, " %s <-- %.3f", get_reg_name(reg
), data
);
685 fprintf(stderr
, " *** NEW MIN (prev %.3f)", reg
->vmin
);
689 fprintf(stderr
, " *** NEW MAX (prev %.3f)", reg
->vmax
);
693 fprintf(stderr
, " *** CHANGED");
697 reg
->current
.f
= data
;
699 if (VERBOSE
|| (NORMAL
&& (newmin
|| newmax
|| changed
)))
700 fprintf(stderr
, "\n");
705 static int print_reg_assignment( struct reg
*reg
, int data
)
707 reg
->flags
|= TOUCHED
;
708 if (reg
->flags
& ISFLOAT
)
709 return print_float_reg_assignment( reg
, *(float *)&data
);
711 return print_int_reg_assignment( reg
, data
);
714 static void print_reg( struct reg
*reg
)
716 if (reg
->flags
& TOUCHED
) {
717 if (reg
->flags
& ISFLOAT
) {
718 fprintf(stderr
, " %s == %f\n", get_reg_name(reg
), reg
->current
.f
);
720 fprintf(stderr
, " %s == 0x%x\n", get_reg_name(reg
), reg
->current
.i
);
726 static void dump_state( void )
730 for (i
= 0 ; i
< Elements(regs
) ; i
++)
731 print_reg( ®s
[i
] );
733 for (i
= 0 ; i
< Elements(scalars
) ; i
++)
734 print_reg( &scalars
[i
] );
736 for (i
= 0 ; i
< Elements(vectors
) ; i
++)
737 print_reg( &vectors
[i
] );
742 static int radeon_emit_packets(
743 drm_radeon_cmd_header_t header
,
744 drm_radeon_cmd_buffer_t
*cmdbuf
)
746 int id
= (int)header
.packet
.packet_id
;
747 int sz
= packet
[id
].len
;
748 int *data
= (int *)cmdbuf
->buf
;
751 if (sz
* sizeof(int) > cmdbuf
->bufsz
) {
752 fprintf(stderr
, "Packet overflows cmdbuf\n");
756 if (!packet
[id
].name
) {
757 fprintf(stderr
, "*** Unknown packet 0 nr %d\n", id
);
763 fprintf(stderr
, "Packet 0 reg %s nr %d\n", packet
[id
].name
, sz
);
765 for ( i
= 0 ; i
< sz
; i
++) {
766 struct reg
*reg
= lookup_reg( regs
, packet
[id
].start
+ i
*4 );
767 if (print_reg_assignment( reg
, data
[i
] ))
772 cmdbuf
->buf
+= sz
* sizeof(int);
773 cmdbuf
->bufsz
-= sz
* sizeof(int);
778 static int radeon_emit_scalars(
779 drm_radeon_cmd_header_t header
,
780 drm_radeon_cmd_buffer_t
*cmdbuf
)
782 int sz
= header
.scalars
.count
;
783 int *data
= (int *)cmdbuf
->buf
;
784 int start
= header
.scalars
.offset
;
785 int stride
= header
.scalars
.stride
;
789 fprintf(stderr
, "emit scalars, start %d stride %d nr %d (end %d)\n",
790 start
, stride
, sz
, start
+ stride
* sz
);
793 for (i
= 0 ; i
< sz
; i
++, start
+= stride
) {
794 struct reg
*reg
= lookup_reg( scalars
, start
);
795 if (print_reg_assignment( reg
, data
[i
] ))
800 cmdbuf
->buf
+= sz
* sizeof(int);
801 cmdbuf
->bufsz
-= sz
* sizeof(int);
806 static int radeon_emit_scalars2(
807 drm_radeon_cmd_header_t header
,
808 drm_radeon_cmd_buffer_t
*cmdbuf
)
810 int sz
= header
.scalars
.count
;
811 int *data
= (int *)cmdbuf
->buf
;
812 int start
= header
.scalars
.offset
+ 0x100;
813 int stride
= header
.scalars
.stride
;
817 fprintf(stderr
, "emit scalars2, start %d stride %d nr %d (end %d)\n",
818 start
, stride
, sz
, start
+ stride
* sz
);
820 if (start
+ stride
* sz
> 258) {
821 fprintf(stderr
, "emit scalars OVERFLOW %d/%d/%d\n", start
, stride
, sz
);
825 for (i
= 0 ; i
< sz
; i
++, start
+= stride
) {
826 struct reg
*reg
= lookup_reg( scalars
, start
);
827 if (print_reg_assignment( reg
, data
[i
] ))
832 cmdbuf
->buf
+= sz
* sizeof(int);
833 cmdbuf
->bufsz
-= sz
* sizeof(int);
837 /* Check: inf/nan/extreme-size?
838 * Check: table start, end, nr, etc.
840 static int radeon_emit_vectors(
841 drm_radeon_cmd_header_t header
,
842 drm_radeon_cmd_buffer_t
*cmdbuf
)
844 int sz
= header
.vectors
.count
;
845 int *data
= (int *)cmdbuf
->buf
;
846 int start
= header
.vectors
.offset
;
847 int stride
= header
.vectors
.stride
;
851 fprintf(stderr
, "emit vectors, start %d stride %d nr %d (end %d) (0x%x)\n",
852 start
, stride
, sz
, start
+ stride
* sz
, header
.i
);
854 /* if (start + stride * (sz/4) > 128) { */
855 /* fprintf(stderr, "emit vectors OVERFLOW %d/%d/%d\n", start, stride, sz); */
859 for (i
= 0 ; i
< sz
; start
+= stride
) {
861 for (j
= 0 ; j
< 4 ; i
++,j
++) {
862 struct reg
*reg
= lookup_reg( vectors
, start
*4+j
);
863 if (print_reg_assignment( reg
, data
[i
] ))
872 cmdbuf
->buf
+= sz
* sizeof(int);
873 cmdbuf
->bufsz
-= sz
* sizeof(int);
878 static int print_vertex_format( int vfmt
)
881 fprintf(stderr
, " %s(%x): %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
885 (vfmt
& R200_VTX_Z0
) ? "z," : "",
886 (vfmt
& R200_VTX_W0
) ? "w0," : "",
887 (vfmt
& R200_VTX_FPCOLOR
) ? "fpcolor," : "",
888 (vfmt
& R200_VTX_FPALPHA
) ? "fpalpha," : "",
889 (vfmt
& R200_VTX_PKCOLOR
) ? "pkcolor," : "",
890 (vfmt
& R200_VTX_FPSPEC
) ? "fpspec," : "",
891 (vfmt
& R200_VTX_FPFOG
) ? "fpfog," : "",
892 (vfmt
& R200_VTX_PKSPEC
) ? "pkspec," : "",
893 (vfmt
& R200_VTX_ST0
) ? "st0," : "",
894 (vfmt
& R200_VTX_ST1
) ? "st1," : "",
895 (vfmt
& R200_VTX_Q1
) ? "q1," : "",
896 (vfmt
& R200_VTX_ST2
) ? "st2," : "",
897 (vfmt
& R200_VTX_Q2
) ? "q2," : "",
898 (vfmt
& R200_VTX_ST3
) ? "st3," : "",
899 (vfmt
& R200_VTX_Q3
) ? "q3," : "",
900 (vfmt
& R200_VTX_Q0
) ? "q0," : "",
901 (vfmt
& R200_VTX_N0
) ? "n0," : "",
902 (vfmt
& R200_VTX_XY1
) ? "xy1," : "",
903 (vfmt
& R200_VTX_Z1
) ? "z1," : "",
904 (vfmt
& R200_VTX_W1
) ? "w1," : "",
905 (vfmt
& R200_VTX_N1
) ? "n1," : "");
908 if (!find_or_add_value( &others
[V_VTXFMT
], vfmt
))
909 fprintf(stderr
, " *** NEW VALUE");
911 fprintf(stderr
, "\n");
918 static char *primname
[0x10] = {
937 static int print_prim_and_flags( int prim
)
942 fprintf(stderr
, " %s(%x): %s%s%s%s%s%s\n",
945 ((prim
& 0x30) == R200_VF_PRIM_WALK_IND
) ? "IND," : "",
946 ((prim
& 0x30) == R200_VF_PRIM_WALK_LIST
) ? "LIST," : "",
947 ((prim
& 0x30) == R200_VF_PRIM_WALK_RING
) ? "RING," : "",
948 (prim
& R200_VF_COLOR_ORDER_RGBA
) ? "RGBA," : "BGRA, ",
949 (prim
& R200_VF_INDEX_SZ_4
) ? "INDX-32," : "",
950 (prim
& R200_VF_TCL_OUTPUT_VTX_ENABLE
) ? "TCL_OUT_VTX," : "");
955 fprintf(stderr
, " prim: %s numverts %d\n", primname
[prim
&0xf], numverts
);
957 switch (prim
& 0xf) {
958 case R200_VF_PRIM_NONE
:
959 case R200_VF_PRIM_POINTS
:
961 fprintf(stderr
, "Bad nr verts for line %d\n", numverts
);
965 case R200_VF_PRIM_LINES
:
966 case R200_VF_PRIM_POINT_SPRITES
:
967 if ((numverts
& 1) || numverts
== 0) {
968 fprintf(stderr
, "Bad nr verts for line %d\n", numverts
);
972 case R200_VF_PRIM_LINE_STRIP
:
973 case R200_VF_PRIM_LINE_LOOP
:
975 fprintf(stderr
, "Bad nr verts for line_strip %d\n", numverts
);
979 case R200_VF_PRIM_TRIANGLES
:
980 case R200_VF_PRIM_3VRT_POINTS
:
981 case R200_VF_PRIM_3VRT_LINES
:
982 case R200_VF_PRIM_RECT_LIST
:
983 if (numverts
% 3 || numverts
== 0) {
984 fprintf(stderr
, "Bad nr verts for tri %d\n", numverts
);
988 case R200_VF_PRIM_TRIANGLE_FAN
:
989 case R200_VF_PRIM_TRIANGLE_STRIP
:
990 case R200_VF_PRIM_POLYGON
:
992 fprintf(stderr
, "Bad nr verts for strip/fan %d\n", numverts
);
996 case R200_VF_PRIM_QUADS
:
997 if (numverts
% 4 || numverts
== 0) {
998 fprintf(stderr
, "Bad nr verts for quad %d\n", numverts
);
1002 case R200_VF_PRIM_QUAD_STRIP
:
1003 if (numverts
% 2 || numverts
< 4) {
1004 fprintf(stderr
, "Bad nr verts for quadstrip %d\n", numverts
);
1009 fprintf(stderr
, "Bad primitive\n");
1015 /* build in knowledge about each packet type
1017 static int radeon_emit_packet3( drm_radeon_cmd_buffer_t
*cmdbuf
)
1020 int *cmd
= (int *)cmdbuf
->buf
;
1022 int i
, stride
, size
, start
;
1024 cmdsz
= 2 + ((cmd
[0] & RADEON_CP_PACKET_COUNT_MASK
) >> 16);
1026 if ((cmd
[0] & RADEON_CP_PACKET_MASK
) != RADEON_CP_PACKET3
||
1027 cmdsz
* 4 > cmdbuf
->bufsz
||
1028 cmdsz
> RADEON_CP_PACKET_MAX_DWORDS
) {
1029 fprintf(stderr
, "Bad packet\n");
1033 switch( cmd
[0] & ~RADEON_CP_PACKET_COUNT_MASK
) {
1034 case R200_CP_CMD_NOP
:
1036 fprintf(stderr
, "PACKET3_NOP, %d dwords\n", cmdsz
);
1038 case R200_CP_CMD_NEXT_CHAR
:
1040 fprintf(stderr
, "PACKET3_NEXT_CHAR, %d dwords\n", cmdsz
);
1042 case R200_CP_CMD_PLY_NEXTSCAN
:
1044 fprintf(stderr
, "PACKET3_PLY_NEXTSCAN, %d dwords\n", cmdsz
);
1046 case R200_CP_CMD_SET_SCISSORS
:
1048 fprintf(stderr
, "PACKET3_SET_SCISSORS, %d dwords\n", cmdsz
);
1050 case R200_CP_CMD_LOAD_MICROCODE
:
1052 fprintf(stderr
, "PACKET3_LOAD_MICROCODE, %d dwords\n", cmdsz
);
1054 case R200_CP_CMD_WAIT_FOR_IDLE
:
1056 fprintf(stderr
, "PACKET3_WAIT_FOR_IDLE, %d dwords\n", cmdsz
);
1059 case R200_CP_CMD_3D_DRAW_VBUF
:
1061 fprintf(stderr
, "PACKET3_3D_DRAW_VBUF, %d dwords\n", cmdsz
);
1062 /* print_vertex_format(cmd[1]); */
1063 if (print_prim_and_flags(cmd
[2]))
1067 case R200_CP_CMD_3D_DRAW_IMMD
:
1069 fprintf(stderr
, "PACKET3_3D_DRAW_IMMD, %d dwords\n", cmdsz
);
1071 case R200_CP_CMD_3D_DRAW_INDX
: {
1074 fprintf(stderr
, "PACKET3_3D_DRAW_INDX, %d dwords\n", cmdsz
);
1075 /* print_vertex_format(cmd[1]); */
1076 if (print_prim_and_flags(cmd
[2]))
1078 neltdwords
= cmd
[2]>>16;
1079 neltdwords
+= neltdwords
& 1;
1081 if (neltdwords
+ 3 != cmdsz
)
1082 fprintf(stderr
, "Mismatch in DRAW_INDX, %d vs cmdsz %d\n",
1086 case R200_CP_CMD_LOAD_PALETTE
:
1088 fprintf(stderr
, "PACKET3_LOAD_PALETTE, %d dwords\n", cmdsz
);
1090 case R200_CP_CMD_3D_LOAD_VBPNTR
:
1092 fprintf(stderr
, "PACKET3_3D_LOAD_VBPNTR, %d dwords\n", cmdsz
);
1093 fprintf(stderr
, " nr arrays: %d\n", cmd
[1]);
1096 if (((cmd
[1]/2)*3) + ((cmd
[1]%2)*2) != cmdsz
- 2) {
1097 fprintf(stderr
, " ****** MISMATCH %d/%d *******\n",
1098 ((cmd
[1]/2)*3) + ((cmd
[1]%2)*2) + 2, cmdsz
);
1104 for (i
= 0 ; i
< cmd
[1] ; i
++) {
1106 stride
= (tmp
[0]>>24) & 0xff;
1107 size
= (tmp
[0]>>16) & 0xff;
1112 stride
= (tmp
[0]>>8) & 0xff;
1113 size
= (tmp
[0]) & 0xff;
1116 fprintf(stderr
, " array %d: start 0x%x vsize %d vstride %d\n",
1117 i
, start
, size
, stride
);
1121 case R200_CP_CMD_PAINT
:
1123 fprintf(stderr
, "PACKET3_CNTL_PAINT, %d dwords\n", cmdsz
);
1125 case R200_CP_CMD_BITBLT
:
1127 fprintf(stderr
, "PACKET3_CNTL_BITBLT, %d dwords\n", cmdsz
);
1129 case R200_CP_CMD_SMALLTEXT
:
1131 fprintf(stderr
, "PACKET3_CNTL_SMALLTEXT, %d dwords\n", cmdsz
);
1133 case R200_CP_CMD_HOSTDATA_BLT
:
1135 fprintf(stderr
, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n",
1138 case R200_CP_CMD_POLYLINE
:
1140 fprintf(stderr
, "PACKET3_CNTL_POLYLINE, %d dwords\n", cmdsz
);
1142 case R200_CP_CMD_POLYSCANLINES
:
1144 fprintf(stderr
, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n",
1147 case R200_CP_CMD_PAINT_MULTI
:
1149 fprintf(stderr
, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n",
1152 case R200_CP_CMD_BITBLT_MULTI
:
1154 fprintf(stderr
, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n",
1157 case R200_CP_CMD_TRANS_BITBLT
:
1159 fprintf(stderr
, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n",
1162 case R200_CP_CMD_3D_DRAW_VBUF_2
:
1164 fprintf(stderr
, "R200_CP_CMD_3D_DRAW_VBUF_2, %d dwords\n",
1166 if (print_prim_and_flags(cmd
[1]))
1169 case R200_CP_CMD_3D_DRAW_IMMD_2
:
1171 fprintf(stderr
, "R200_CP_CMD_3D_DRAW_IMMD_2, %d dwords\n",
1173 if (print_prim_and_flags(cmd
[1]))
1176 case R200_CP_CMD_3D_DRAW_INDX_2
:
1178 fprintf(stderr
, "R200_CP_CMD_3D_DRAW_INDX_2, %d dwords\n",
1180 if (print_prim_and_flags(cmd
[1]))
1184 fprintf(stderr
, "UNKNOWN PACKET, %d dwords\n", cmdsz
);
1188 cmdbuf
->buf
+= cmdsz
* 4;
1189 cmdbuf
->bufsz
-= cmdsz
* 4;
1194 /* Check cliprects for bounds, then pass on to above:
1196 static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t
*cmdbuf
)
1198 drm_clip_rect_t
*boxes
= (drm_clip_rect_t
*)cmdbuf
->boxes
;
1201 if (VERBOSE
&& total_changed
) {
1208 if ( i
< cmdbuf
->nbox
) {
1209 fprintf(stderr
, "Emit box %d/%d %d,%d %d,%d\n",
1211 boxes
[i
].x1
, boxes
[i
].y1
, boxes
[i
].x2
, boxes
[i
].y2
);
1213 } while ( ++i
< cmdbuf
->nbox
);
1216 if (cmdbuf
->nbox
== 1)
1219 return radeon_emit_packet3( cmdbuf
);
1223 int r200SanityCmdBuffer( r200ContextPtr rmesa
,
1225 drm_clip_rect_t
*boxes
)
1228 drm_radeon_cmd_buffer_t cmdbuf
;
1229 drm_radeon_cmd_header_t header
;
1230 static int inited
= 0;
1238 cmdbuf
.buf
= rmesa
->store
.cmd_buf
;
1239 cmdbuf
.bufsz
= rmesa
->store
.cmd_used
;
1240 cmdbuf
.boxes
= (drm_clip_rect_t
*)boxes
;
1243 while ( cmdbuf
.bufsz
>= sizeof(header
) ) {
1245 header
.i
= *(int *)cmdbuf
.buf
;
1246 cmdbuf
.buf
+= sizeof(header
);
1247 cmdbuf
.bufsz
-= sizeof(header
);
1249 switch (header
.header
.cmd_type
) {
1250 case RADEON_CMD_PACKET
:
1251 if (radeon_emit_packets( header
, &cmdbuf
)) {
1252 fprintf(stderr
,"radeon_emit_packets failed\n");
1257 case RADEON_CMD_SCALARS
:
1258 if (radeon_emit_scalars( header
, &cmdbuf
)) {
1259 fprintf(stderr
,"radeon_emit_scalars failed\n");
1264 case RADEON_CMD_SCALARS2
:
1265 if (radeon_emit_scalars2( header
, &cmdbuf
)) {
1266 fprintf(stderr
,"radeon_emit_scalars failed\n");
1271 case RADEON_CMD_VECTORS
:
1272 if (radeon_emit_vectors( header
, &cmdbuf
)) {
1273 fprintf(stderr
,"radeon_emit_vectors failed\n");
1278 case RADEON_CMD_DMA_DISCARD
:
1279 idx
= header
.dma
.buf_idx
;
1281 fprintf(stderr
, "RADEON_CMD_DMA_DISCARD buf %d\n", idx
);
1285 case RADEON_CMD_PACKET3
:
1286 if (radeon_emit_packet3( &cmdbuf
)) {
1287 fprintf(stderr
,"radeon_emit_packet3 failed\n");
1292 case RADEON_CMD_PACKET3_CLIP
:
1293 if (radeon_emit_packet3_cliprect( &cmdbuf
)) {
1294 fprintf(stderr
,"radeon_emit_packet3_clip failed\n");
1299 case RADEON_CMD_WAIT
:
1303 fprintf(stderr
,"bad cmd_type %d at %p\n",
1304 header
.header
.cmd_type
,
1305 cmdbuf
.buf
- sizeof(header
));
1315 fprintf(stderr
, "Bufs %d Total emitted %d real changes %d (%.2f%%)\n",
1317 total
, total_changed
,
1318 ((float)total_changed
/(float)total
*100.0));
1319 fprintf(stderr
, "Total emitted per buf: %.2f\n",
1320 (float)total
/(float)bufs
);
1321 fprintf(stderr
, "Real changes per buf: %.2f\n",
1322 (float)total_changed
/(float)bufs
);
1324 bufs
= n
= total
= total_changed
= 0;
1328 fprintf(stderr
, "leaving %s\n\n\n", __FUNCTION__
);